KR900003767B1 - Disc device - Google Patents

Abstract

The disc drive device includes the motor (2) for rotating the disc, a magnetic head (5) for reading and writing the data on the disc, a magnetic head carrying appts. for positioning the magnetic head at the valid region, a magnetic head location sensor (11) for obtaining the second output voltage level, an on-detection circuit (17) for detecting the power on-state of the magnetic head and a recalibration means for positioning the magnetic head on the reference track.

Description

Disk unit

1 is a block diagram showing a disk device according to an embodiment of the present invention.

FIG. 2 is a front view showing the positional relationship between the track zero sensor of FIG.

3 is a circuit diagram showing in detail the stepping motor control driving circuit of FIG.

4 is a circuit diagram showing the control circuit 23 and a part thereof related to the FIG.

5, 6, and 7 are wave diagrams representing the A-I point states of FIGS. 3 and 4, respectively.

* Explanation of symbols for main parts of the drawings

1: disc 2: motor

5: magnetic head 8: step-in motor

10: control drive circuit 11: track zero sensor

14: interlator 17: power-on detection circuit

The present invention relates to a floppy disk device or similar disk device for reading / writing signal data, and more particularly, to a circuit for positioning a transducer on a reference track upon power up.

In the case of reading / writing (lead / write) data by the floppy disk device, for example, as shown in US Patent No. 4,594,620, the magnetic head (converter) is connected to the track zero or reference track in response to the power supply. Determine your location. In order to determine the position of this magnetic head to the track zero, the disk apparatus has a magnetic head (transducer) position sensor called a power-on detection circuit and a track zero sensor. In general, the track zero sensor is composed of a light emitting element, a light receiving element, and a hot interferer (light shielding plate) which is integrally moved with the magnetic head, so that the track zero position of the magnetic head can be detected by the output of the light receiving element. Consists of

However, when the magnetic head is in the track zero position, since the optical path between the light emitting element and the light receiving element is interrupted by an interlator, for example, a high level output is generated from the light receiving element. In general, the track zero sensor generates a high level output even if the magnetic head is located in the non-effective area outside the track zero, since the hot interleaver blocks the optical path as in the case of the track zero. For this reason, in the conventional disk device, a stopper is provided for restricting the movement of the magnetic head outward from the track zero position. The stopper is arranged to limit the movement of the carriage supporting the magnetic head in correspondence with the track zero position of the magnetic head.

However, in order to determine the track zero position by the stopper, it is necessary to precisely fine tune the position of the stopper, which has been a difficult task. Now, the floppy disk device has been described, but there are the same problems in various disk devices, that is, data conversion or storage devices, which are required to determine the position of the converter on the reference track.

It is therefore an object of the present invention to provide a disk apparatus which can easily position the transducer on a reference track.

SUMMARY OF THE INVENTION The present invention for solving the above problems and achieving the above object comprises an effective area including an effective track for reading and / or writing data and an invalid area having substantially no relation to reading and / or writing of the data. An apparatus for reading and / or recording data using a recording medium disk in which the track in the effective area closest to the ineffective area is arranged concentrically, and is a reference track, comprising: disk rotating means for rotating the disk; A transducer for converting data in relation to the disc, a transducer moving means configured to move the transducer in the radial direction of the disc, to move the transducer in the effective area, and to determine the position even in the non-effective area; Output of a voltage level of one and a second voltage level different from the first voltage level. And the transducer position sensor 11 configured to obtain an output of the second voltage level not only when the transformer is located on the reference track but also when the transformer is located on an invalid area adjacent to the reference track. ) And a power source for detecting the switching of the power supply of the data conversion position to the ON state are connected to the detection circuit 17, the converter moving means, the transducer position sensor 11, and the power ON detection circuit 17. The transducer is placed on the reference track in response to a signal indicating the switching of the power supply obtained from the power supply ON detection circuit 17, and the transducer position sensor 11 is switched off when the power supply is switched on. Even if the output of the second voltage level occurs, the converter position is not considered to be located on the reference track based on this, and the transducer position is responsive to the output of the second voltage level. The converter moving means is controlled to obtain an output of the first voltage level from the stand 11, and then the converter moving means is controlled to obtain an output of the second voltage level from the converter position sensor 11 to refer to the converter. A disk unit constituted by a recalibration allowance for determining position on a track.

In the above invention, even if the output of the second voltage level indicating the reference track detection is detected from the transducer position sensor at power-on, the output of the first voltage level is not terminated without terminating the positioning of the converter to the reference track. Move the transducer to the position where it occurs and then return it on the reference track. Therefore, since the stopper is not provided or the correct stopper is not installed, even if a wrong reference track detection output (pseudo reference track detection output) occurs from the transducer position sensor, this is automatically corrected.

Next, a floppy disk device according to an embodiment of the present invention will be described with reference to FIGS.

In Fig. 1, reference numeral 1 denotes a flexible magnetic disk, which is generally called a floppy disk. The disk 1 is provided with track zero T ₀ as a reference track at the most main track, and a plurality of tracks are arranged concentrically from track to inward track T _n . Therefore, the outer side of the track zero T ₀ is an invalid area, and the inner side is an effective area. (2) is a disk rotation motor, which rotates the disk (1) on the rotating table (3) coupled thereto. The control drive circuit 4 connected to the motor 2 drives the motor 2 at constant speed in response to a signal transmitted from the host side device.

5 is a magnetic head as a transducer for reading / writing data, and is supported by the carriage 6. The carriage 6 is guided in the radial direction of the disk 1 by the guide shaft 7. In order to move the magnetic head 5 and the carriage 6 in the disk radial direction, a stepped motor 8 and a lead screw 9 are provided. The lead screw 9 is coupled to the motor 8 which is a step, and converts the rotational movement of the motor 8 which is a step into the linear motion of the carriage 6. Furthermore, steel balls (not shown) provided in the carriage 6 are engaged with the grooves of the lead screw 9. The rotation-linear motion conversion is not limited to the lead screw 9, but may be a steel belt or the like. In this embodiment, when the first phase winding of the four phase windings of the step-in motor 8 is excited, the magnetic head 5 is located at the track zero.

The control drive circuit 10 connected to the step-in motor 8 controls and drives the step-in motor 8 to determine the position of the magnetic head 5. In this embodiment, the four-phase step-in motor 8 is driven by the one-phase excitation method.

Reference numeral 11 denotes a track zero sensor transducer position sensor, which detects a track zero position of the magnetic head 5. The track zero sensor 11 includes a light emitting element 12 and a light receiving element 13 opposing the light emitting element 12. The tracker 14 is integrated with the carriage 6, i.e., the light shielding body corresponds to the track zero. When it is in the position, light reaching the light receiving element 13 from the light emitting element 12 is cut off, and a track zero detection signal is generated, which is configured to be supplied to the control driving circuit 10 by the line 1la. . In addition, as illustrated in FIG. 2, the position of the interlifter 14 when the magnetic head 5 is inward of the track T ₀ is indicated by a dashed line, and when it is outside. The position of is indicated by the dotted line. In the case of the dashed line, since the light directed from the light emitting element 12 to the light receiving element 13 is not blocked by the interleaver 14, the output of the low level (first voltage level) from the track zero sensor 11 is reduced. When the interpreter 14 is positioned so as to correspond to the track zero T ₀ of the magnetic head 5, as indicated by the solid line, the high level (twelfth voltage level) from the track zero sensor 11 is generated. The track zero detection signal is generated, and at the position of the interruper 14 indicated by the dotted line, the optical path from the light emitting element to the light receiving element 14 is blocked by the interluft 14 as in the case of the solid line. Therefore, a pseudo track zero detection signal of a high level (second voltage level) is generated, and the sensor output is sent to the control drive circuit 10.

Denoted at 15 in FIG. 2 is a stopper made up of a part of the frame supporting the motors 2, 8, etc., which restricts the carriage 6 from moving to the outer circumference of the disc 1 more than necessary. Part. However, it is not necessary to exactly match the stopper 15 with the track zero as in the prior art, and it is sufficient to correspond to any position toward the outer circumference than the track zero T ₀ of the magnetic head 5.

In FIG. 1, the power supply line 16 of this disk apparatus is connected to the motor control drive circuit 4 and the motor control drive circuit 10 which is a step. Although the power supply line 16 is shown by one line in this figure, for example, two power supply lines of 12 volts and a 5 volt power supply line may be provided.

17 is a power supply ON detection circuit, which is connected to the power supply line 16, for example, has a built-in voltage comparator, and outputs an output line indicating the power supply ON in response to the power supply voltage rising above a predetermined level. Supply to control drive circuit 10 from 17a.

3 shows the step-in-motor control drive circuit 10 in detail. The control drive circuit 10 is connected to the output line 11a of the track zero sensor 11 and the output line 17a of the power ON detection circuit 17 described in FIG. An external step signal line 18 for inputting an external step signal from the controller and a step direction signal line 19 are connected, and the track zero setting end signal line 20 for supplying the track zero signal to the host side device again. Is installed.

In Fig. 3, reference numeral 21 denotes a known excitation signal generating circuit. In this embodiment, the motor 8, which is a step, includes the first, second, third and fourth phase windings 8a and 8b. ), (8c), (8d), and is driven in a single phase excitation method, so the four output lines (21a), (21b), (21c), (d) to the first phase, the second phase, The third and fourth phase excitation signals are sequentially output. The drive circuit 22 connected to the excitation signal generation circuit 21 is a circuit that responds to the excitation signal and sends a current through the winding of the motor 8 which is a phase step designated by the excitation signal. More specifically, the drive circuit 22 includes switches S ₁ , which are connected in series with the first to fourth windings 8a, 8b, 8c, and 8d of the step-in motor 8. S ₂ , S ₃ , and S ₄ are included, and the switches S ₁ , S ₂ , S ₃ , and S ₄ are selectively controlled to be ON and OFF to supply current to the preferred winding of the step-up motor 8. It is configured to. Moreover, switches S _{1 to} S ₄ are generally composed of NAND gates.

When the step pulse and the step direction signal are supplied to the excitation signal generation circuit 2l, the step-in motor 8 is driven correspondingly. However, in order to perform a recalibration operation at power-on, that is, in response to power-on, the magnetic head 5 of FIG. 1 is positioned at the track zero T ₀ of the disk 1. In order to obtain the initial state, various circuits are added.

Reference numeral 23 denotes a recalibration control circuit, which controls various controls for positioning the magnetic head 5 at the track zero at power-on according to the present invention. For this reason, the power supply ON detection output line 17a and the track zero sensor output line 11a are connected to this control circuit 23, and the lines 24, 25, and 26 are connected. , (27), (28), (29), (30) and (31) are connected. This control circuit 23 will be described later in detail with reference to FIG.

Numeral 32 is an NOR gate of AND type, with one input terminal connected to the step signal line 18 and the other input terminal connected to the output line 26 of the control circuit 23. . The NOR gate 32 is provided so as to prohibit the external step signal only during the recalibration period at power-on, and generates a high level output only when both inputs are at a low level.

Reference numeral 33 denotes an internal step pulse generation circuit, which is connected to the output line 27 of the control circuit 23 and generates an internal step pulse at a constant period T when the output line 27 is in a low level state. When the output line 27 reaches a high level, generation of the internal step pulse is stopped. The internal step pulse generation circuit 33 is composed of, for example, a clock pulse generator and a binary counter. The internal step pulse generation circuit 33 generates a pulse when the counter counts a constant value of the clock pulse, and then resets it to a constant value again. It is configured to generate a pulse at the time of counting. The internal step pulse generation circuit 33 may be constituted by a CR oscillator or the like other than a counter. This internal step pulse generation circuit 33 is also used to drive the stepping motor 8 by an external step pulse. For this reason, the output line of the NOR gate 32 is connected to the internal step generation circuit 33. As shown in FIG. That is, the stepping motor 8 of this embodiment is configured such that the movement amount of one track pitch is obtained in two steps. Therefore, it is configured to respond to one external step pulse supplied from the line 18 in response to the movement of one track, and generate the internal step pulse after a certain period from the external step pulse. In other words, the internal step pulses during recalibration and the internal step pulses for compensating the external step pulses are configured using a common counter.

Reference numeral 35 is an OR gate, where one input terminal is connected to the output of the NOR gate 32, the other input terminal is connected to the line 34, and this output terminal is connected to the excitation signal generation circuit 21. It is connected to the step driving period signal generating circuit 36. Therefore, the OR gate 35 supplies both the external step pulse and the internal step pulse to the excitation signal generation circuit 21.

The step driving period signal generating circuit 36 outputs two types of signals substantially corresponding to the period during which the magnetic head 5 is step driven in response to an external step pulse or an internal step pulse obtained through the OR gate 35. It is a circuit which sends out from the lines 24 and 25, and supplies this to the recalibration control 23. As shown in FIG. More specifically, this step driving period signal generation circuit 36 is composed of a retriable (retreeable) single-precision vibrator constructed using a binary counter. The first output line 24 slaughtered from the circuit 36 has a high level in response to the first step pulse of one group, and an output which returns to a low level after a predetermined time T ₁ from the last step pulse. The output is fed to the second output line 25 at a low level in response to the first step pulse and returns to a high level after a predetermined time T ₂ from the last step pulse. In addition, T <T ₂ <T ₁ is set. The counter in this circuit 36 is also used for forming the power supply voltage switching signal of the stepping motor 8. This power supply voltage switching signal is for supplying a voltage of 12V to the stepping motor 8 at the first step pulse, and switching from a voltage supply of 12V to a voltage supply of 5V after a certain time from the last step pulse for power saving. will be.

Reference numeral 38 denotes a D flip-flop for magnetic head movement direction latches, the data input terminal of which is connected to the step direction signal line 19, and the clock input terminal of which is connected to the output terminal of the NOR gate 32. The output terminal is connected to the excitation signal generation circuit 21 through the OR gate 39. If the D flip-flop 38 is provided, the step direction signal is latched. Therefore, even if the step direction signal changes between the next external step signal, the previous step until the next external step signal is generated. The direction signal is maintained. Since the external step pulse is inputted to the clock input terminal CK through the NOR gate 32, the input of the external step direction signal is prohibited during the recalibration operation.

The AND gate 40 has four inputs and has a signal output line 29, a track zero sensor output line 11a, and a first phase excitation detection line showing the initial termination of the control circuit 23. It is connected to the NOT circuit 41 connected to 31 and the output of the OR gate 39. As a result, the track zero setting end signal is obtained at the output line 20 of the AND gate 40.

Reference numeral 42 is a switch for automatically setting track zero upon power-on and is connected in series with a line 28 between the ground OV and the control circuit 23. Since the line 28 is connected to the positive power supply terminal 44 through the resistor 43, a low level signal is sent to the line 28 when the switch 42 is ON, and a high level signal when the switch 42 is OFF. Is sent. In addition, when the switch 42 is ON, recalibration at the time of power supply is enabled.

Next, FIG. 4 is shown in detail showing the recalibration control circuit 23 of FIG. 3 and a circuit related thereto. The control circuit 23 includes an RS flip flop 45, a NOT circuit 46, a NAND gate 47, an OR type NAND gate 48, a NOT circuit 49, a NAND gate 50, NAND gate 51, NAND gate 52 of OR type, RS flip flop 53, two NAND gates 54, 55, two NOT circuits 56, 57, two NAND gates (58), (60), AND gate 61, and NAND gate 62 of OR type. In detail, the flip-flop 45 is for determining the track zero automatic setting period when the power is turned on, and the set terminal 8 is connected to the power-on detection circuit output line 17a through the NOT circuit 46. The reset terminal R is connected to the output terminal of the OR type NAND gate 48. One input terminal of the NAND gate 47 is connected to the track-zero automatic setting signal line 28 at power-on, and the other input is connected to the track-zero sensor output line 11a through the NOT circuit 49. This output terminal is connected to one input terminal of the NAND gate 48. The other input terminal of the NAND gate 48 is connected to the output terminal of the NAND gate 60. The Q output terminal of the flip flop 45 is connected to the AND type NOR gate 32 via the line 26 and to the input terminal of the AND gate 61 and the OR type NAND gate 62, respectively. .

One input terminal of the AND gate 50 has a power supply contacting the detection signal line 17a via a NOT circuit 46, and the other input terminal is connected to the track-zero sensor output line 11a. .

One input terminal of the NAND gate 51 is connected to the output terminal of the NOT circuit 46, and the other input terminal is connected to the output terminal of the NOT circuit 49. One input terminal of the OR type NAND gate 52 is connected to the output terminal of the NAND gate 51 of the previous stage, and the other input terminal is connected to the output terminal of the NAND gate 58.

The set terminal S of the flip flop 53 is connected to the output terminal of the AND gate 50, the reset terminal R is connected to the output terminal of the NAND gate 52, and the Q output terminal is an AND gate. It is connected to the input terminal of the 61 and the NAND gate 54.

One of the other two input terminals of the NAND gate 54 is connected to the NOT circuit 49 output terminal, and the other is connected to the step driving period signal line 24.

출력단자에 접속되어있으며, 두번째의 입력단자는 트랙영 센서 출력라인(11a)에 접속되고, 세번째의 입력단자는 스텝구동기간 신호출력라인(24)에 접속되고, 네번째의 입력단자가 특정상 여자검출수단으로서의 제 1 상 여자검출라인(31)에 접속되어 있다. NAND 게이트(54)의 출력단자는 OR 타입의 NAND 게이트(62)의 입력단자에 접속되어있음과 동시에 NOT 회로(56)를 통하여 NAND 게이트(58)의 입력단자에 접속되어있다. NAND 게이트(55)의 출력단자는 OR 타입의 NAND 게이트(62)의 입력단자에 접속되어있는 동시에 NOT 회로(57)를 통하여 NAND 게이트(60)의 입력단자에 접속되어 있다.The first input terminal of the NAND gate 55 is of the flip flop 53.

The second input terminal is connected to the track zero sensor output line 11a, the third input terminal is connected to the step output period signal output line 24, and the fourth input terminal is specifically excited. It is connected to the 1st phase excitation detection line 31 as a detection means. The output terminal of the NAND gate 54 is connected to the input terminal of the OR type NAND gate 62 and is connected to the input terminal of the NAND gate 58 via the NOT circuit 56. The output terminal of the NAND gate 55 is connected to the input terminal of the OR type NAND gate 62 and is connected to the input terminal of the NAND gate 60 via the NOT circuit 57.

Each input terminal of the two NAND gates 58, 60 is connected to the step driving period signal output line 25, respectively. An internal step direction signal line 30 is derived from the output terminal of the AND gate 61, which is connected to the input terminal of the OR gate 39.

An internal step control signal line 27 is derived from the output terminal of the OR type NAND gate 62.

출력단자에 접속되어있다. 이 AND 게이트(40)는, 제 3 도에서도 표시되고 있다. 더우기, NOR 게이트(32), OR 게이트(39), NOT 회로(41)도 제 3 도에서 보여주고 있다.One input terminal of the AND gate 40 is the flip-flop 45

It is connected to the output terminal. This AND gate 40 is also shown in FIG. Moreover, the NOR gate 32, OR gate 39, and NOT circuit 41 are also shown in FIG.

In the timing chart of FIG. 5, the switch 42 of FIG. 3 is turned ON, the track zero automatic setting signal line 28 is grounded when the power is turned on, and the optical path of the track zero sensor 11 is connected to the hot interceptor. in the state in which 14 is cut off, showing a case where the start of the supply voltage on the power line 16 at the time point t _1. When the power is turned on at t ₁ , the power supply voltage gradually rises as indicated by the broken line in Fig. 5 (a), and the power ON detection circuit 17 is turned on at the time t ₂ when it is slightly delayed from the turned on time. A high level power-on detection signal, indicated by the solid line in a), is generated, which is input to the control circuit 23 by the line 17a. On the other hand, the track zero sensor 11 generates a track zero sensor output of a high level (second voltage level) as shown in FIG. 5 (b), which is inputted to the control circuit 23 by the line 11a. do. In this embodiment, the first phase winding of the stepping motor 8 is a reference, and the stepping motor 8 is obtained so that the track zero position of the magnetic head 5 is obtained when the first phase winding is excited. And the position of the magnetic head 5 are related. In addition, the excitation signal generating circuit 21 is configured so that the first phase winding is excited in synchronization with the power supply. For this reason, as in FIG. 5 (g), the first phase is excited at t ₂ and the first phase excitation detection line 31 is brought to a high level.

When the input power from the 5 degrees of t _1, t ₁ -t ₂ the period from t ₂ to a power supply ON detection signal is at a high level is the low level. In response to the low level period of t _l -t ₂ , a high level trigger signal is generated from the NOT circuit 46, the flip-flop 45 is set, and a high level output showing that the recalibration operation is in progress at the Q output terminal. Obtained. For this reason, the input of the external step signal in which the AND type NOR gate 32 may be supplied from the line 18 is prohibited. Therefore, the period in which the flip flop 45 is set operates as an internal step pulse.

In the period t _1- t ₂ , since both inputs of the AND gate 50 are at a high level, this output is also at a high level. As a result, the flip flop 53 is triggered, and the Q output is at a high level. This flip flop 53 is for internally obtaining a step direction signal.

After t ₂ when the two flip flops 45 and 53 are set, both inputs of the AND gate 61 become high level, so the outputs of the line 30 and the OR gate 39 also become high level. , A high level output (first direction signal) is generated showing stepping as in FIG. 5 (c).

Furthermore, since the D flip flop 38 shown in FIG. 3 is reset in the period in which the flip flop 45 of FIG. 4 is set, even if an external step direction signal is input from the line 19, the external Is not input to the OR gate 39.

출력이 저레벨이므로, 양쪽의 NAND 게이트(54),(55)의 출력이 고레벨로 된다. 이 결과, OR 게이트 타입의 NAND 게이트(62)의 전 입력이 고레벨로 되며, 이 NAND 게이트(62)의 출력라인(27)의 내부 스텝 제어신호는 제 5 도(h)에서와 같이 저레벨로 유지된다.At t ₂ , the output of the NOT circuit 49, which is one input of the NAND gate 54, is low level, and the flip-flop 53, which is one input of the NAND gate 55, is low.

Since the output is low level, the outputs of both NAND gates 54 and 55 become high level. As a result, all inputs of the OR gate type NAND gate 62 become high level, and the internal step control signal of the output line 27 of the NAND gate 62 remains low level as shown in FIG. do.

Since the internal step pulse generation circuit 33 of FIG. 3 is configured so that the control signal line 27 is added at a low level and generates the internal step pulse at a constant period T, as shown in FIG. An internal pulse is generated at T ₃ , which is supplied to the excitation signal generation circuit 21 through the OR gate 35 in FIG. 3. As a result, as shown in Fig. 5 (g), the first phase excitation is released, and instead, the second phase is excited, and when the next internal step pulse is generated at T ₄ , the third phase is excited. When the first internal step pulse is generated at T _3, in response to this, a high level output is generated from the output line 24 of the step driving period signal generating circuit 36 as shown in FIG. 25, the low-level output occurs in reverse as in FIG. 5 (f). In the case of FIG. 5, since the hedo 5 moves by one track pitch in two steps, a second internal step pulse is generated at T ₄ , thereby moving to the track T ₁ of the magnetic head 5. In this example, the output of the track-young sensor 11 switches to the low level as in FIG. 5 (b) at t ₅ . As a result, when all the inputs of the AND gate 54 become high level, this output switches to the low level. For this reason, one input of the OR type NAND gate 62 becomes low level, and this output switches to high level as shown in FIG. 5 (h). Since the internal step pulse generation circuit 33 of FIG. 3 is configured so as not to generate internal step pulses in the period in which the control signal line 27 is at a high level, the internal step pulse generation in FIG. It stops. For this reason, the magnetic head 5 stops at the track T ₁ . If at t ₂ the time the magnetic head (5) so far, the track zero been described for the case that the T _0, if at t ₂ the time the magnetic head 5, the track zero T ₀ all located shifted outward, it gailcheung many inner step The magnetic head 5 is moved to the track T ₁ by this.

The signal of the output line 25 in the step driving period signal generating circuit 36 (FIG. 5F) is brought to a low level in synchronization with the first internal step pulse due to the operation of the retriable monostable multivibrator. At the time point t ₆ at which T _B elapses from the second pulse, the signal returns to the high level as shown in FIG. 5 (f). Thus, when the line 25 goes high at t ₆ , since both inputs of the NAND gate 58 go high, this output goes low, which is inverted by the OR type NAND gate 52 and flipped. The flop 53 is added as a reject signal, and the step direction flip flop 53 is reset, and as a result, the step direction signal of the OR gate 39 becomes at t ₆ , as shown in FIG. It becomes low level and a stepout (second direction) is set.

When the signal of the output line 34 of the step driving period signal generating circuit 36 becomes high level at t ₃ by the first step pulse as shown in FIG. _It returns to the low level at time t ₇ after time T _A has elapsed from _four . When the flip flop 53 becomes low at t ₆ , since one input of the NAND gate 54 of FIG. 4 becomes low level, this output switches to a high level, and eventually, the OR type NAND gate 62 The output line 27 is brought to a low level as shown in FIG. 5 (f), and the internal step pulse generation circuit 33 is added. As shown in Fig. 5 (d), when the internal step pulse is generated at t ₈ , the step-direction signal in Fig. 5 (c) is stepped out (second direction), so that the second phase excitation signal is And the first phase excitation signal is generated again at t ₁₀ .

When the internal step pulse is generated at t ₈ , the outputs of FIGS. 5E and 5F are inverted correspondingly. Exciting the second phase winding at t ₈ moves from track T ₁ of magnetic head 5 toward track T ₀ . For this reason, the interruper 14 is located in the optical path of the track-young sensor 11 at t ₉ , and the track- zero sensor output is at a high level (second voltage level) as shown in FIG.

Then, if an internal step pulse occurs at t ₁₀ , it is excited in the first phase, and the magnetic head 5 is positioned at the track zero. at t _10, as in the first phase excitation detection signal is also (g) 5 (specific phase detection signal), if the high level before the input of the fourth-degree NAND gate 55 is at a high level at t _10. That is, the output of the flip-flop 53, which is the first input of the NAND gate 55, is already reset at t ₆ and is at a high level. Since the second input is a track-zero sensor output, the output is already at high level at t ₉ . Since the third input is the signal of FIG. 5 (e), it is at a high level, and the fourth input is at the high level at t ₁₀ because the first phase is an excitation detection signal, and the output is switched to the low level. As a result, the output line 27 of the OR type NAND gate 62 becomes high level as shown in FIG. 5 (h), and generation of internal step pulses when the power is turned on is prohibited.

On the other hand, if the flip-flop 53 is reset at t ₆ and the first phase excitation detection signal is subsequently at a high level, the output of the NAND gate 55 is at a low level at t _{10. As} a result, the NAND gate 60 The input terminal becomes a high level on one side of Thereafter, when the signal of the line 25 as shown in FIG. 5 (f) at t ₁₁ switches to a high level, since both inputs of the NAND gate 60 become a high level, this output becomes a low level, The output of the NAND gate 48 switches to the high level, and the flip flop 45 is reset.

출력이 고레벨로 되기 때문에, AND 게이트(40)의 전 입력이 고레벨로 되고, 제 5 도(1)에서와 같이, 고레벨의 트랙영 설정 종료 신호(정확한 트랙영 신호)가 발생하고, 이것이 호스트측 장치에게 라인(20)으로 공급된다. 또한, t₁₁에서 플립플럽(45)의 Q 출력이 저레벨로되기 때문에, AND 타입의 NOR 게이트(32)에 의한 외부로부터의 스텝펄스의 입력금지가 해제되고, 또한, 제 3 도의 D 플립플립(38)에 의한 외부로부터의 스텝방향 신호의 입력금지가 해제된다.If the flip flop 45 is reset at t ₁₁ ,

Since the output is at a high level, all the inputs of the AND gate 40 are at a high level, and as shown in FIG. 5, a high level track zero setting end signal (exact track zero signal) is generated, which is the host side. The device is fed into line 20. In addition, since the Q output of the flip-flop 45 becomes low at t ₁₁ , the input prohibition of the step pulse from the outside by the AND-type NOR gate 32 is canceled, and the D flip-flop of FIG. The input prohibition of the step direction signal from the outside by 38) is released.

At the time of power-on, the operation between the case where the hor interlator 14 is at the position indicated by the solid line in FIG. 2 and the position at the dotted line are substantially the same. In other words, even when the horn interlator 14 is in the position indicated by the solid line when the power is turned on, and the magnetic head 5 is accurately positioned at the track zero T ₀ , it is distinguished from the position of the dotted line. Since it is difficult to detect, both are regarded as the same and the same operation occurs. Now, if the interruper 14 is in the dotted line position, for example, the rotor of the stepping motor 8 is stopped in correspondence with the third phase winding, the six internal phases after the first phase excitation at the time of power-on. Step pulses are generated, and excitation is performed in the order of the second, third, and fourth phases due to the operation that is the step when the power is turned on, and again in the order of the first phase, the second phase, and the third phase. As a result, a state corresponding to t ₅ in FIG. ₅ is obtained.

In FIG. 6, when the power is turned on, the switch 42 of FIG. 3 is set to ON, the line 28 of FIG. 4 is grounded, and the light path of the track-zero sensor 11 Displays the operation in the state of not blocking.

When the power is turned on at t ₁ in FIG. 6, as in FIG. 6 (a), a high level power ON detection signal is obtained at t ₂ . Then, the flip flop 45 of FIG. 4 receives a trigger input in the period t ₁ -t ₂ as in the case of FIG. 5 and enters the set state. As a result, the external step pulse is inhibited by the NOR gate 32 of FIG. 3 and the external step direction signal is inhibited by the D flop flop 38.

Since at t ₂ and, near it is Figure 6 (b) a track zero sensor output is low-level, without even turning on the power output of the AND gate 50 are at a high level, the flip-flop 53 is not set, the Q The output terminal goes low. As a result, the step direction signal of the output line of the OR gate 39 becomes low level as shown in Fig. 6C, and the stepout (second direction) is set. At the time T ₂ , the output line 27 of the NAND gate 62 is at a low level as in FIG. 5 as in FIG. 6 (h), and the internal step pulse generation circuit 33 in FIG. And internal step pulses of FIG. 6 (d) are generated. At power-on, the first phase excitation signal is generated as shown in Fig. 6 (g), and then the step-out control is performed, so that t ₃ , t ₄ , t ₅ , t ₆ , t ₇ of Fig. 6 (d) is In response to the pulses occurring at, t ₈ , t ₉ , t ₁₁ , the stepping motor 8 is a fourth phase, a third phase, a second phase, a first phase, a fourth phase, a third phase, a second The phases are excited in the order of the first phase. Thus, when t ₁₀ is reached, the track zero sensor output becomes high level as in FIG. 6 (b), and then the same operation as after t ₉ in FIG. 5, and the correct magnetic head corresponding to the first phase ( A track zero position of 5) is obtained.

In FIG. 7, since the internal recalibration is unnecessary, the optical path of the track zero sensor 11 is turned on when the power supply is turned on while the switch 42 of FIG. 3 is set to OFF. Displays the operation when blocking. In this case, it is necessary to set the correct track zero position at power-on due to control from the host side device. For this reason, it is required to make the output of the track young sensor 11 low.

That is, even if the output of the track zero sensor 11 at a high level at the time of power supply is unknown, whether or not it is a true track zero position is unknown. Move to and wait for the command of the host side position. In more detail, when the power is turned on at t ₁ , as in the case of FIG. 5, the flip flops 45 and 53 of FIG. 4 are set, and internal step pulses are generated as in FIG. 7 (d). At the same time, a high-level step-in is set as in Fig. 7C. When an internal step pulse is generated at t ₃ and t ₄ , and the track zero sensor output of FIG. 7 (b) at t _{5 is} lowered, all the inputs of the NAND gate 54 become high level, and the output becomes low level. do. As a result, the output line of the NAND gate 62 becomes high leg as shown in FIG. 7 (h), and generation of internal step pulses is prohibited. When the track zero sensor output in Fig. 7 (b) becomes low at t ₅ , the output of the NOT circuit 49 becomes high level, and both inputs of the NAND gate 47 become high level. As a result, the output of the NAND gate 47 becomes low level, the high level russet signal is generated from the next NAND gate 48, and the flip-flop 45 is reset. This enables control by the host side device.

In addition, when the switch 42 is set to ON and the power is turned on without the interleaver 14 blocking the optical path of the track-young sensor 11, both inputs of the NAND gate 47 are at a high level. The output goes to a low level, and as a result, the output of the NAND gate 48 goes to a high level. For this reason, the flip flop 45 is reset and a recalibration operation | movement does not generate | occur | produce. Therefore, the positioning of the magnetic head 5 is made by the host side apparatus.

This invention is not limited to the above-mentioned embodiment, For example, the following modified example is possible.

(A) Instead of the stepping motor 8, the present invention can be applied to the case of using a voice coil motor, a DC motor, a linear motor, or the like.

(B) Even though the detection accuracy of the track zero sensor 11 is poor, for example, the magnetic head 5 is located on the track T ₁ or T ₂ adjacent to the track zero T ₀ , a high level track zero is achieved. It can also be applied when generating sensor output.

(C) The correspondence relation between the number of steps of the motor 8, which is a step, and the amount of movement of the magnetic head 5 can be applied to the case where it differs from the embodiment, for example, four step one track or one step one track. have.

(D) It is also applicable to the case in which the track-young sensor 11 is configured by using a rotation converter or a micro switch.

(E) It is also possible to correspond to the track zero on the basis of the step other than the first phase of the stepping motor 8. It is also possible to use a 1-2 phase excitation stepping motor.

(F) The two signals shown in Figs. 5 (e) and (f) may be formed by two analog tribable monostable multivibrators in response to step pulses without being configured by a counter.

(G) Applicable to optical disk devices and fixed magnetic disk devices.

As is evident from the above, according to the present invention, the setting of the track zero position at the time of power supply can be performed without involving mechanical positioning means. Therefore, the disk device can be easily manufactured.

Claims (6)

An effective area including an effective track for reading and / or writing data and a non-effective area substantially unrelated to reading and / or writing of data are arranged in a concentric shape and within the closest valid area to the non-effective area. An apparatus for reading and / or recording data using a recording medium disk having a track as a reference track, the disk rotating means for rotating the disk, a converter for converting data in relation to the disk, and a converter. A transducer moving means configured to move the transducer in the effective area and to position it in the non-effective area, and to output an output of the first voltage level and a different value from the first voltage level. Configured to generate an output of a voltage level of 2, only when the transducer is on the reference track In addition, even when located on the non-effective area adjacent to the reference track, the converter position sensor 11 configured to obtain the output of the second voltage level and switching to the ON state of the power supply of this data converter are provided. Switching to the ON state of the power supply obtained from the power ON detection circuit 17, connected to the ON detection circuit 17 for detecting the power supply, the converter moving means, the transducer position sensor 11, and the power ON detection circuit 17. In response to a signal indicating, the transducer is positioned on the reference track, and even when the output of the second voltage level is generated from the transducer position sensor 11 at the time of switching to the ON state, This means that the transducer moving means is adapted to obtain the output of the first voltage level from the transducer position sensor 11 in response to the output of the second voltage level without regard to the transducer being located on the reference track. And recalibration means for controlling the transducer moving means so as to obtain an output of the second voltage level from the transducer position sensor (11) to determine the position on the reference track. A disk apparatus according to claim 1, wherein the transducer moving means comprises a motor which is a step for moving the transducer in the radial direction of the disk. The recalibration means according to claim 2, wherein the recalibration means comprises: a step pulse generation circuit 33 connected to a motor which is a step, a power supply ON detection circuit 17, a transducer position sensor 11 and a step pulse generation; The converter is connected to the circuit 33 and in response to the output indicating the switching of the power source obtained from the power source ON detection circuit 17 to the ON state and the output of the second voltage level obtained from the converter position sensor 11. A first direction signal is generated to move from the reference track into the effective area, and a step pulse is generated to supply a step pulse to the step-in motor while controlling the step-in motor with the first direction signal. By controlling the circuit 33, in response to the output of the first voltage level obtained from the transducer position sensor 11 as a result of the control, a second direction signal for moving the transducer toward the reference track is generated, andWhile controlling the step-in motor with the direction signal of 2, the step pulse generating circuit 33 is controlled to supply the step pulse to the step-in motor, and then the output of the transducer position sensor 11 is supplied to the second. A recalibration control circuit for controlling the step pulse generating circuit 33 to stop the supply of the motor which is the step of the stub pulse in response to the switching to the voltage level, and to position the transducer on the reference track. (23) A disk device provided with a. The converter calibration sensor according to claim 3, wherein the recalibration control circuit 23 further comprises an output and a transducer position sensor 11 indicating the switching of the power supply obtained from the power supply ON detection circuit 17 to the ON state. Responsive to the output of the first voltage level obtained from the C1), a second direction signal is generated, and the second direction signal is used to control the step-in motor and to supply the step pulse to the step-in motor. The step pulse generation circuit 33 is controlled, and then the step pulse is set so that the supply of the step pulse to the motor which is the step of the step pulse is stopped in response to the output of the transducer position sensor 11 being switched to the second voltage level. And control means for controlling the generating circuit (33), thereby determining the position of the transducer on the reference track. The motor according to claim 3, wherein the motor, which is a step, has a plurality of windings, the windings of the particular phase of the windings of the plurality of phases are arranged so as to correspond to the positions of the reference tracks of the converter, and the windings are one-phase excitation. The recalibration means has a specific phase excitation detecting means 31 which detects whether or not the winding of a specific phase is excited, and the recalibration means has a recalibration control. The all-circuit 23 is also connected to the specific phase excitation detecting means 31 and steps from the step pulse generation circuit 33 in response to a detection signal showing the excitation of the winding of the specific phase obtained in the generation period of the second direction signal. And a means for stopping the supply of the step pulse to the in-motor. The transducer position detecting sensor (11) according to claim 1 is characterized in that the transducer position detecting sensor (11) is centered on an interruper (14) fixed to a portion displaced together with the transducer in the transducer moving means and a passage of the interluft (14). And a light receiving element 13 disposed on one side and a light receiving element 13 disposed opposite to the light emitting element 12 on the other side centering on the passageway of the interlufter 14.

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