KR900002421B1 - Drive controller for inverter - Google Patents

Abstract

The PWM signal comprises a data region and a halt region in each carrier period. The carrier period and data unit time are controlled by independent digital values produced by microcomputers independent of each other or by use of different timers. The data unit time is modified by an output of a power source voltage fluctuation detector, thus providing a constant voltagefrequency characteristic.

Description

Inverter drive control device

1 is a block diagram of an inverter system.

2 is a block diagram of an inverter system for an air conditioner.

3 is a voltage waveform diagram applied to a transistor and a compressor in the system.

4 is an explanatory diagram of a "carrier" in the system.

5 (a) and 5 (b) are explanatory diagrams of different voltages applied to the compressor, respectively.

6 (a) and 6 (b) are timing diagrams of a data area for explaining " HALT " and carrier period T _{0 in} the system, respectively.

7 is a v / f pattern diagram when the data unit timer T ₂ in the system is constant.

8 (a) and 8 (b) are timing diagrams of different data areas respectively describing the data unit timer T ₂ .

9 is a diagram of a v / f pattern when the data unit timer T ₂ is changed.

10A and 10B are timing diagrams of data regions of different constant voltage regions.

11 is a v / f pattern diagram including a constant voltage region.

12 is a v / f pattern diagram including a low frequency voltage boost.

13 is a circuit diagram of an inverter drive control apparatus showing one embodiment of the present invention.

14 is a block diagram of the inverter drive control device.

Fig. 15 is a v / f pattern diagram in which a voltage boost is realized in the inverter drive control apparatus.

Fig. 16 is a timing chart of a data area employing digital processing in an inverter drive control device.

Fig. 17 is a flowchart illustrating a carrier period (T ₀ ) processing in the inverter drive control apparatus.

18 is a flowchart of a data unit timer T ₂ processing in the inverter drive control apparatus.

Fig. 19 is an explanatory diagram of a PWM data area in a ROM in the inverter drive control device.

20 is a v / f pattern diagram for fluctuations in power supply voltage of an inverter drive control apparatus showing one embodiment of the present invention.

21 is a circuit diagram of an inverter driving device showing one embodiment of the present invention.

22 is a block diagram of the inverter door control device.

23 is a flowchart illustrating a carrier period (T ₀ ) processing in the inverter drive control apparatus.

24 is a flowchart illustrating a data unit timer (T ₂ ) processing in the inverter drive control apparatus.

* Explanation of symbols for main parts of the drawings

(1): rectifier smoothing part (2): inverter

(3) Compressor (4) Inverter drive control circuit

(5): first microcomputer (6): second microcomputer

(7): Reference frequency oscillation circuit (8) (9): System clock

10: T ₀ timer divider (first timer means)

(11) T ₂ timer divider (second timer means)

12: first control unit 13: second control unit

14: address counter 15: ROM of a second microcomputer,

(16) data latch of the second microcomputer

(17): ROM of the first microcomputer

(18): power supply voltage fluctuation detection circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter drive control device suitable for drive control of a compressor such as an air conditioner or a refrigerator, or an induction motor having a relatively small output for industrial use.

Several methods such as RAM and PWM are known for controlling the inverter for driving the motor. Among them, the sine wave approximate floating-width PWM method is used for power supply, light weight of the device, reduction of radio noise, noise and vibration. It is excellent in terms of the back and has been used a lot recently.

As shown in FIGS. 3 and 5 in the sinusoidal approximation floating width PWM method, a PWM algorithm is generated to approximate the integral value of the voltage applied to the motor windings to the sinusoidal wave.

Here, the "HALT" method which is the basis of the present invention will be described as a conventional example.

1 is a block diagram of an inverter system. (1) is a rectifier smoothing part which generates direct current from a commercial power supply, (2) is an inverter, (3) an electric motor, and (4) is an inverter drive control circuit.

Next, an example configured for an air conditioner is shown in FIG. (1 ') is a smooth rectifier, (2') is an inverter using a transistor, (3 ') is a compressor, (4') is an inverter drive control circuit, (4a) is a PWM algorithm generator, and (4b) is The photocoupler 4c is a driver for supplying the base current of the transistor.

The signal generated by the PWM algorithm generating section 4a is optically insulated and amplified by the photoelectric coupler 4b, supplied to the driver 4c, amplified by current, and then supplied to the inverter 2 ', and the three-phase compressor ( 3 '). The transistors of the inverter 2 'are composed of three pairs of upper and lower pairs, and the upper arm and the lower arm perform inverted switching operations, respectively, and are not ON at the same time.

3 shows a signal applied to each transistor and a voltage waveform applied to a compressor.

u, v, and w represent the base signals of the transistors of the upper arm, respectively. In addition, u-v, v-w, and 2-u are voltage waveforms applied to each winding of the compressor 3 ', respectively. As is apparent from the figure, the voltage applied to the compressor is configured to approximate a sine wave when integrated, and the period of this voltage pattern determines the rotation speed of the compressor.

Next, the PWM algorithm will be described. 4 shows the concept of "carrier".

In Fig. 4, the half period of the sine wave is divided into constants N. This (N) is called "carrier", and the N equalized period T ₀ is called "carrier period".

If voltage data is given as a pulse width for each carrier period T ₀ , an algorithm can be configured as in the third diagram.

Next, the voltage value applied to the compressor in FIG. 5 will be described. In the case where a constant voltage is generated in the algorithm shown in FIG. 5 (a), if each pulse width is increased proportionally, the waveform becomes the same as that of FIG. 5 (b), and the integral value also increases proportionally. In other words, the output voltage can be increased or decreased in proportion to the pulse width.

Next, the pulse width and "HALT" for determining the voltage will be described with reference to FIG.

There are a plurality of divided data area times in the carrier period T ₀ , and the rest of the time is also called a "HALT" area. Voltage data is not output in this HALT area.

Now, for carrier period T ₀ (1), it is assumed that the data area time is sufficiently short. This state is shown in FIG. Next, as shown in Fig. 6 (b), the carrier period T ₀ is set to 1/2, which is referred to as T ₀ (2). If the data area time is constant at this time, the frequency f is doubled (carrier period 1/2) and the output voltage V is also doubled. This is because the pulse width relative to the carrier period T ₀ is doubled.

Therefore, assuming that the data area time is constant, if the carrier period T ₀ is changed, the frequency f changes in inverse proportion to the carrier period T ₀ , and the voltage V increases or decreases in proportion to the frequency f.

The shape of this v / f pattern is shown in FIG.

At this time, the "HALT" period also changes as a "pause of data" period.

Next, the data area will be described in detail with reference to FIG.

The data area described in FIG. 6 is divided into integers K, and the divided mood periods are referred to as the data unit timer T ₂ . That is, the voltage is divided into logic patterns with K resolutions, and this value is given by the data unit timer T ₂ .

As a matter of course, as the values of the carrier wave N and the number of data k described above become larger, the voltage applied to the compressor can be approached to the sine wave.

In Fig. 8A, the carrier period T ₀ is set to T ₀ (1) and the data unit timer T ₂ is set to T ₂ (1). Next, as shown in Fig. 8B, the data unit timer T ₂ is doubled to be T ₂ (2). At this time, the data area trial (T ₂ (2) x k) is doubled, and the "HALT" time is relatively reduced.

At this time, the output voltage (V) is doubled. If the carrier period T ₀ is changed again to this result, each V / f pattern is equal to the ninth degree.

Next, in FIG. 9, as the voltage V rises, the " HALT " area shown in FIG. 8 decreases. If it rises further, the "HALT" area disappears. Compressor applied voltage is a limit if the smoothed, rectified DC voltage value is constant. Therefore, if the frequency (f) is increased above this advantage, the voltage (V) is no longer increased, so the constant voltage change.

This shape is explained using FIG. As shown in FIG. 10A, the "HALT" region is referred to as 0, and the carrier period T ₀ (3) is divided by the number of data K to give a data unit timer T ₂ (1). That is, it _{Tø (3) K × T 2} (1). Next, as shown in FIG. 10 (b), when the frequency is raised and the carrier period Tø is Tø (4), T ₂ (3) becomes (T ₂ (4) = K × T ₂ (3). At this time, since the data area time ratio in the carrier period T ₀ becomes the same, both voltages are constant, which is shown in FIG.

Next, the relationship between the inverter output and the load will be described.

Inverter output has voltage proportional to power if the load is resistive.

On the other hand, as for the compressor, the amount of work is proportional to the amount of refrigerant pushed out of the cylinder, so when the rotation speed is low, the amount of pushing is small, and when the rotation speed is high, the amount of pushing is also increased.

In other words, a constant proportionality between frequency and output voltage is required.

However, the actual electric motor (motor for a compressor) increases iron loss, copper loss, etc. in the low frequency region, and thus, a so-called boolean that increases and corrects the voltage in the low frequency region, as shown in FIG. Requires test function.

In the conventional example, the carrier period T ₀ and the data unit timer T ₂ are configured by the analog timer, the frequency is set by the timer of the carrier frequency period T ₀ , and the timer of the carrier period T ₀ is established. The booster curve was realized by correcting the timer of the data unit timer T ₀ according to the set value of.

The maximum advantage of the "HALT" method is simply changing the values of the carrier period (T ₀ ) and the data unit timer (T ₂ ), so that the PWM algorithm generation pattern can be realized in one cycle for all frequency ranges. It is.

Although the configuration of the conventional example is as described above, when the carrier period T ₀ and the data unit timer T ₂ are configured as an analog timer, fine correction of each timer value is possible with an external component, and the carrier period T _{0 is obtained.} ), The data unit timer (T ₂ ) can be adjusted independently, but the range of the frequency used is wide, and if you want to approximate it by a sine wave, the carrier (N), It is necessary to change the number of data K.

That is, in the low frequency region, the waveform resolution becomes coarse and the waveform is disturbed. Therefore, it is necessary to set the carrier wave N and the data number K to a large value. At high frequencies, the carrier wave N and the data number K If it is large, the switching speed of the transistor becomes a problem, and the downtime of the transistor having the upper and lower arms increases in proportion, resulting in a decrease in the output voltage. Therefore, it is necessary to select a smaller value for both the carrier wave N and the number K of data. .

In the analog timer method shown in the conventional example, the switching of the PWM generation data itself, which is accompanied by a change in the number of carriers and data, may be performed by selecting an external data area such as a ROM. It is difficult to do it smoothly. When the carrier cycle T ₀ and the data unit timer T ₂ are shifted slightly even, the target frequency and voltage are changed to different values for a moment. Therefore, the power transistor is destroyed during overcurrent or lock of the compressor. It may be related to, and there is a considerable problem. In the case of the analog timer, problems such as drift caused by temperature change in frequency, newness problems such as deterioration of age, and system configuration are complicated. It is included.

In addition, the conventional example has a boost function in the low frequency region as described above, but outputs a PWM waveform having a v / f characteristic similar to that of the twelfth degree with respect to the change in the power supply voltage. In this case, for example, when the power supply voltage is lowered, the PWM output voltage naturally decreases, which causes problems such as lowering the torque of the compressor, increasing the current value, accompanying breakdown of the compressor, and lowering the efficiency.

The present invention eliminates the above-described conventional problems, and sets the carrier period T ₀ and the data unit timer T ₂ to independent digital values, respectively, and thus the carrier period T ₀ and the data unit timer T _2. ) To determine frequency and voltage, and to calibrate the data unit timer (T ₂ ) to obtain a constant V / f output characteristic against fluctuations in power supply voltage. The present invention aims to realize a high performance and to realize an efficient operation of the compressor.

In addition, using two microcomputers, the first microcomputer has various types of carrier waves and data numbers according to the application, and can be configured in various types of sine-wave approximation PWM drive control devices. will be.

In addition, by controlling the carrier period (T ₀ ) and the data unit timer (T ₂ ) by using the same reference frequency, it is an object to eliminate the error of each other, enabling high-precision control of both frequency and voltage. .

Hereinafter, the inverter drive control apparatus of the present invention will be described with reference to FIGS. 13 to 19 showing one embodiment thereof.

13 is a circuit diagram and FIG. 14 is a block diagram.

In FIG. 13, 5 is a 1st microcomputer, and 6 is a 2nd microcomputer. Denoted at 7 is a reference frequency power generation circuit, which is input to the OSC terminal of each microcomputer 5,6. The first microcomputer 5 is input with a commercial frequency input of 50/60 Hz and f-set, which is a rotation frequency command of the motor. In addition, from the first microcomputer 5 to the second microcomputer 6, a carrier period T ₀ signal produced by the first microcomputer 5 and a data unit timer made by the second microcomputer 6 are used. T ₂ data for (T ₂ ) is output. Then, the PWM signal is output from the second microcomputer 6 to the motor.

14 is a block diagram. The 50/60 Hz input to the first microcomputer 5 is a commercial frequency input for making a sequence timer for the system. In order to drive the compressor, a means for gradually changing the frequency toward the target frequency is required, but a timer giving a change speed of this frequency is configured as this input. f-set is the input that gives the target frequency, and the frequency slowly approaches toward the value set at this input.

The reference oscillation input is divided in each of the system clocks 8 and 9 to obtain a system clock output. The system clocks (8) and (9) are inputted to the T ₀ timer divider (10), the T ₂ timer divider (11), the first and second control units (12) and the first and second control units. In (12) and (13), it is a reference for generating a carrier period T ₀ and a data unit timer T ₂ while executing a program.

The division value of the carrier period T ₀ and the data unit timer T ₂ is input to the ROM 17 of the first microcomputer corresponding to each frequency, and is input to the first microcomputer 5. When the data of the carrier period T ₀ and the data unit timer T ₂ corresponding to the f-set input value pass through the first control unit 12, the data of the carrier period T ₀ is divided by the T ₀ timer divider. And the data of the data unit timer T ₂ is set from the first control unit 12 to the T ₂ timer divider 11 of the second microcomputer 6.

The carrier period T ₀ made in the first microcomputer 5 is input to the second micro computer 6 and interrupts the intervention with the data unit timer T ₂ made in the second microcomputer 6. Through the processing, the second control unit 13 of the second microcomputer 6 is sequentially input via the address counter 14 to sequentially access the ROM 15 in which the PWM data is stored, and the second control unit 13 U, v, w phase data are sequentially output via the data latch 16 indicated by.

Functions required for system control, for example, refrigeration cycle processing, communication processing with the indoor control microphone of the separate air tone, four-way valve, fan motor processing, current control, defrost control is the first microcomputer ( It is processed by the first control part 12 of 5).

Next, the outline of the digital processing will be described with reference to FIGS. 15 and 16. FIG.

15 is a v / f pattern diagram for realizing the boost of the low frequency region according to the present invention.

As described above, the v / f slope is determined by the data unit timer T ₂ and the frequency f is determined by the carrier period T ₀ , so that the voltage of each desired boosted frequency shown in FIG. It is sufficient to float at the intersection of the value and T ₂ (X) and output the combination of each T ₀ -T ₂ as data.

Fig. 16 explains the digital processing of the region where the " HALT " region is short.

Let the number of data K be 6 here and call the data (D ₀ )-(D ₂ ). Set the data unit timer to (T ₂ ) and the carrier period to (T ₀ ).

First, when the " HALT " time is larger than the carrier period T ₀ , as shown in FIG. 8, the " HALT " is output, and then the signal wait of the carrier period T ₀ becomes the next data D ₁ . Is output in synchronization with the next conveyance period T ₀ .

After following the "HALT" time, the output data unit of the timer (T ₂₎ "HALT" man hours of the next carrier period (T ₀₎ that is a data unit of the timer (T ₂₎ when arrived in a short range than the data ( Outputs D ₁ ) ~ (D ₆ ). At this time, the output time of the data (D ₁ ) to (D6) remains the data unit timer (T ₂ ).

When the carrier period T ₀ comes next during the output of the data D ₆ , the next "HALT" is not output, and the data D ₆ is continuously output only the period of the data unit timer T ₂ . do. In the meantime, the address of the PWM pattern data is set to +2. This means that data D ₁ is skipped and accessed. Here, the PWM pattern data is determined so that the data before and after each " HALT ", that is, the data D ₁ , is the same logical value in advance. Since the data D ₆ outputted secondly is the same as the next data D ₁ , the result is as if the " HALT " area disappears and the data is continuously output.

If the frequency becomes larger, the "HALT" period is necessarily the data unit timer T ₂ , but the existence rate of the "HALT" itself decreases, and in total, the ratio of the "HALT" period falls and the voltage rises.

When the voltage reaches the upper limit, the " HALT " period disappears completely, _{resulting in} a relationship of T _{1 / SB> = 6T 2} . This state has already been explained using FIG.

In order to increase the frequency, the carrier period T ₀ may be shortened as it is while maintaining the relationship of T ₀ = 6T ₂ .

Next, the flowchart art which implements an Example is shown in FIG. 17, FIG.

17 shows the T ₀ timer section processed by the first microcomputer 5. FIG. 18 shows the data contents of the T ₂ timer and PWM 15 processed by the microcomputer 6 of FIG.

In the PWM data area in the ROM shown in FIG. 19, sinusoidal PWM waveforms are continuously stored for a first period, and u _H , v _H , w _H , u _L , w _L , data, and the "HALT" period are stored. The displayed data and the data and data indicating the end of one data cycle are allocated.

Moreover, the timing of actual waveform output is shown in FIG. 16 shows one output in u, v, and w.

First, as shown in FIG. 17, the first microcomputer 5 inputs the target frequency f-set, and reads T ₀ data and T ₂ data according to the frequency from the table of the ROM 17. Outputting T ₂ data to the second microcomputer 6, setting the T ₀ timer, and similarly outputting the T ₀ signal to the second microcomputer 6 through the determination of the time-up. do.

Next, as shown in FIG. 18, the second microcomputer 6 first initializes the PWM data, reads the T ₂ data output from the first microcomputer 5, and sets the T ₂ timer. Wait for the time-up and move on to the next program. There, the PWM data is read from the ROM and the data end is determined. Since it is not a data end at first, HALT determination is made next. In this case, since it is the first data, it becomes "N" and outputs data. Then read the second data. This repetition outputs data sequentially. After the data is outputted to D ₆ , "HALT" becomes "Y", and at this point, the interruption interruption signal and the carrier period T? Sent by the first microcomputer 5 are determined. If the carrier period Tø has not been input at this point, outputs "HALT", waits until the interruption of the carrier period Tø comes, and returns to the origin when the carrier period Tø is accepted as the interruption input. Then, the next data D ₁ is output.

When "HALT" becomes "Y" and the interruption interruption input of the carrier period Tø at this point is "Y", the home position is immediately +1 to output the PWM data address and output the next data D ₁ . Return to

By the way, in the last data of one cycle of data, the determination of the data end is "Y", the last data is outputted, and the PWM data is initialized before entering the next cycle and returned to the beginning.

In this manner, data for one cycle is sequentially output, the frequency f and the voltage V are determined by the values of the carrier period Tø and the data unit timer T ₂ to obtain a desired PWM pattern. .

If there is no change in the PWM data, the carrier period Tø, and the data unit timer T ₂ , the data is repeatedly output as before. When the carrier period Tø and the data unit timer T ₂ are changed, the PWM pattern remains the same as before, and the frequency and the voltage change, respectively. When the head address of the data address is changed, a PWM pattern having a different carrier N and data number K is selected. Thus, by preparing a plurality of PWM data patterns, for example, using a PWM data pattern with a large number of low frequencies, a sinusoidal approximation with higher resolution can be realized. The head address of this data address, the carrier period Tø, and the data unit timer T ₂ are compared and calculated for the capability as an air conditioner, current, temperature setting, and the like, and are determined in advance by the first microcomputer 5.

In this manner, a sinusoidal approximation part PWM algorithm can be generated to smoothly control the number of revolutions of the compressor.

Next, the inverter drive control apparatus of the present invention is provided in which the power supply voltage fluctuation detecting means is provided so that the V / f output characteristics are constant even when the power supply voltage fluctuations are used. Explain.

20 is a V / f pattern diagram. (a) is the case where the power supply voltage is rated and the boost of the low frequency range mentioned above is added. (b) is a V / f pattern when the power supply voltage is high, and (c) is a low power supply voltage. Now, if the frequency is (fo), in the case of (a), the data unit timer T ₂ is a value of (K), but in order to obtain the V / f pattern of (b), the data unit timer T ₂ is set to K. To obtain -3 and to obtain the V / f pattern of (c), the data unit timer T ₂ may be set to K + 2. That is, the V / f slope is determined by the data unit timer T ₂ , and in order to make V / f constant with respect to the power supply voltage variation, when the power supply voltage is low, the data unit timer T ₂ is increased to increase the voltage (V). It is possible to make the output voltage at the rated voltage close to the output voltage at high rated voltage and to close the output voltage at the rated voltage by lowering the data unit timer (T ₂ ) to lower the voltage (V) when the power supply voltage is high. .

By the way, if this data unit timer T ₂ is changed from (K) to K-3 and K + 2, it is also possible to change the date and time, but it is K when moving from K to K-3. In the case of shifting through -1 and K-2 and shifting to K + 2, if the change is made through the steps as if passing through K + 1, the compressor can be made smoothly without any burden on the compressor.

FIG. 21 is a circuit diagram and FIG. 22 is a block diagram.

FIG. 21 shows a power supply voltage fluctuation detecting circuit in FIG.

Numeral 18 denotes a power supply voltage fluctuation detecting circuit and includes a comparator 19. The power supply voltage is stepped down by the transformer 20 and smoothed in the rectifier circuit 21 and the condenser 22. The voltage is compared with the reference voltage in the comparator 19 to detect the change in the power supply voltage. As a result, a signal of "H" when the power supply voltage is high and "L" when it is low is input to the first microcomputer 5. In addition, by increasing the number of comparators 19, the ratio of power supply voltage fluctuation can be detected in more detail.

FIG. 22 is a block diagram and the same as the block diagram of FIG. 14, and the output of the comparator of the power supply voltage fluctuation detecting circuit 18 of FIG. 21 is input to the controller 12 of the first microcomputer 5 as a boost signal. Then, the booster data for correcting the data unit timer T ₂ from the control unit 12 is output to the second microcomputer 6.

23 and 24 show flowchart art for realizing this embodiment. FIG. 23 shows the T ° timer portion processed by the microcomputer 5 of FIG. FIG. 24 shows the T ₂ timer and PWM waveform output processing processed by the microcomputer of FIG.

23 is basically the same as the flowchart art of FIG. 17 in the absence of power supply voltage correction, and reads the signal input from the power supply voltage fluctuation detecting circuit 18, and is a boolean that is a correction value of the data unit timer T ₂ . The test data is output to the second microcomputer 6 similarly to the T ₂ data.

Here in the micro computer 6 for the second, as shown in claim 24 degrees, by taking first initializes the PWM data read the T ₂ data and Buu host data output at the microcomputer (5) of claim 1, T ₂ Set a timer, wait for the time up, and move on to the next program.

That is, when the T ₂ timer is set from the boost data, which is the correction value of the T ₂ data and the data unit timer T ₂ , if the correction value is 0, the T ₂ data is set as it is, and if there is a correction value, the correction value is set in the T ₂ data. Add. At that time, if T ₂ data is T ₂ data + 1 and the correction value is -1, the change of the data unit timer T ₂ is made for each loop and the correction value is -1 at each time. When the correction value is changed, the correction value = 0 and the data unit timer T ₂ becomes T ₂ data + boost data.

Hereinafter, after the T ₂ timer set, the same processing as that in the flowchart art 18 in the case of no power supply voltage correction is performed to output the PWM waveform.

In this way, the output voltage can be made constant by correcting the data unit timer T ₂ even for the power supply voltage variation.

Claims (12)

In the inverter driving control apparatus using the sinusoidal approximation part width-width PWM method which divides the half period of a sine wave into the carrier frequency (N), and sets it as the carrier period (Tø), and consists of a data area and a HALT area in a carrier period, the carrier drive control apparatus of the inverter The first timer means 10 forming a carrier cycle Tø for determining the rotational speed of the motor corresponding to the number N, and the voltage data comprising a plurality of steps for giving a voltage component in one carrier period Tø. The second timer means 11 for driving data for construction, the power supply voltage fluctuation detecting means 18 for detecting the fluctuation of the power supply voltage, and the data of one cycle of the output waveform in the order of occurrence and the voltage data In the non-existent HALT area, the second timer value T ₂ of the second timer value T ₂ corrected by a signal from the power supply voltage fluctuation detecting means is stored and the output does not apply the voltage to the motor. The first and second timer means 10 and 11 are set to independent digital values, respectively, and the data access star art for each carrier period is set to the first and second means. By the second timer means 10 and 11, the next data access means is performed by the second timer means 11 to the power supply voltage fluctuation detected by the power supply voltage fluctuation detecting means 18. And an inverter drive control device configured to change an output voltage determined by said second timer means (11). The inverter drive control apparatus according to claim 1, wherein the inverter drive control device changes the correction values of the second timer values T ₂ one by one. The inverter drive control apparatus according to claim 1, wherein any one or both of the number of carriers (N), the number of data (K), or the correction value has a plurality of sets of different data areas. 4. The inverter drive control apparatus according to claim 3, wherein the data region and the first and second timer means are synchronously switched at the timing of the data end of one cycle of waveform data, respectively. Inverter drive control device according to the sinusoidal approximation width PWM method which divides the half period of sine wave into carrier number (N) to make carrier period (Tø) and constitutes the data period and HALT area in carrier period (Tø). A first timer means (10) comprising a carrier cycle (T?) For determining the rotational speed of an electric motor corresponding to the carrier number (N), and a plurality of steps for giving a voltage component in one carrier period (T?). Second timer means 11 for driving data for constituting voltage data, power supply voltage fluctuation detecting means 18 for detecting a change in power supply voltage, and data of one output waveform period in order of generation the timer value of the voltage HALT area data is not present memory output does not apply a voltage to the electric motor is corrected by the signal from the power supply voltage fluctuation detection means wherein the ₂ (T 2) The storage means 15 which memorize | amended the correction value is provided, and the said 1st, 2nd timer means 10 and 11 are set to independent digital values, respectively, and the data access star art for every carrier period has the said 1st, 2nd The second timer means 11, the next data access means being configured to change the output voltage by a change in power supply voltage, and the first timer means. An inverter drive control apparatus in which (10) is performed by the first microcomputer and the second timer means (11) and the storage means (15) are performed by the second microcomputer. 6. The inverter drive control apparatus according to claim 5, wherein the inverter drive control device changes the correction values of the second timer values (T ₂ ) one by one. The inverter drive control apparatus according to claim 5, wherein any one or all of the number of carriers (N), the number of data (K), or the correction value has a plurality of sets of different data areas. 8. The inverter drive control apparatus according to claim 7, wherein the data area and the first and second timer means (10) (11) are synchronously switched at the timing of the data end of one cycle of waveform data, respectively. Inverter drive control device according to the sinusoidal approximation width PWM method which divides the half period of sine wave into carrier number (N) to make carrier period (Tø) and constitutes the data period and HALT area in carrier period (Tø). A first microcomputer (5) having a first timer means (10) and a first control means (12) for forming a carrier cycle (Tø) for determining the rotational speed of an electric motor corresponding to the carrier number (N). And power supply voltage fluctuation detecting means 18 for detecting a change in power supply voltage, and second timer means 11 for driving data for constituting voltage data comprising a plurality of steps of giving a voltage component in one carrier period. And an output of applying no voltage to the electric motor in the HALT area storing data of one cycle of the output waveform in the order of occurrence, and having no voltage data, and being supplied to the power supply voltage fluctuation detecting means 18. A second microcomputer 6 having a storage means 15 for storing the correction value of the second timer value T ₂ corrected by the data signal, a second control unit 13, and the first And a system clock (8) (9) for inputting the same reference oscillation frequency to the second microcomputer (5) (6), and the first and second timer means (10) and (11) are independent digital ones. T ₂ for the signal of the first timer 10 and the signal of the second timer 11 produced by the second microcomputer 6 in the first control unit 12. The data is output to the second microcomputer 6, and the second control unit 13 performs the data access star art for each carrier period by the first and second timer means 10 and 11, respectively. The next data access means is constituted by the second timer means 11, and the power supply voltage fluctuation detecting means 18 To according to the power supply voltage variation is detected by a configuration for changing an output voltage that is determined by the timer means 11 of the second inverter drive control apparatus. 10. The inverter drive control apparatus according to claim 9, wherein the inverter has a configuration in which the correction values of the second timer values (T ₂ ) are changed one by one. The inverter type control device according to claim 9, wherein any one or all of the number of carriers (N), the number of data (K), or the correction value has a plurality of sets of different data areas. 12. The inverter drive control apparatus according to claim 11, wherein the data area and the first and second timer means (10) (11) are synchronously switched at the timing of the data end of one cycle of waveform data, respectively.

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