KR900002073Y1 - Noise signal canceling circuit - Google Patents

Noise signal canceling circuit Download PDF

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Publication number
KR900002073Y1
KR900002073Y1 KR2019870015763U KR870015763U KR900002073Y1 KR 900002073 Y1 KR900002073 Y1 KR 900002073Y1 KR 2019870015763 U KR2019870015763 U KR 2019870015763U KR 870015763 U KR870015763 U KR 870015763U KR 900002073 Y1 KR900002073 Y1 KR 900002073Y1
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transistor
signal
noise signal
collector
base
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KR2019870015763U
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Korean (ko)
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KR890007849U (en
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정병노
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주식회사금성사
최근선
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/10Means associated with receiver for limiting or suppressing noise or interference
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/16Circuits
    • H04B1/18Input circuits, e.g. for coupling to an antenna or a transmission line

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Noise Elimination (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)

Abstract

내용 없음.No content.

Description

잡음심호 제거회로Noise Deletion Circuit

제 1도는 본 고안의 잡음신호 제거회로도.1 is a noise signal cancellation circuit of the present invention.

제 2도는 제 1도의 각부의 파형도.2 is a waveform diagram of each part of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : AM 고자파 및 중간주파 검파부 FET1: 전계효과 트랜지스터1: AM high frequency and intermediate frequency detector FET 1 : Field effect transistor

TR1~TR4: 저항 C1~C4: 콘덴서TR 1 to TR 4 : Resistance C 1 to C 4 : Capacitor

본 고안은 휴대용 및 차량등에 설치되는 에이엠(Amplitude Moldulation : AM) 수신기에 있어서, 특히 약전계 지역 및 강한 잡음지역에서 발생되는 잡음신호를 제거할 수 있게한 잡음심호 제거회로에 관한 것이다.The present invention relates to an Amplitude Moldulation (AM) receiver installed in a portable vehicle and a vehicle, and more particularly, to a noise deep circuit removing circuit capable of removing a noise signal generated in a weak electric field region and a strong noise region.

일반적으로 FM(Frequnecy Modulation) 수신기에 있어서는 여러가지의 잡음신호 감소회로가 구성되어 있으나, AM 수신기에 있어서는 유기되는 외부잡음신호를 제거할수 있는 회로의 구성이 없었으므로 특히 약전계 지역 및 강한 잡음지역에서 유기되는 잡음신호의 발생으로 청취자에게 청각적으로 많은 분괘감을 주는등의 결함이 있었다.In general, in FM (Frequnecy Modulation) receivers, various noise signal reduction circuits are constructed. However, in AM receivers, there are no circuits to remove the induced external noise signals. There was a defect such as the generation of a noise signal that gives the listener a sense of hearing.

그리고, 차량용 무선통신기에 있어서는 잡음 리미터 회로가 사용되었으나 이 역시 관변조시 찌그러짐이 발생되는 결함이 있었다.In addition, although a noise limiter circuit is used in a vehicle wireless communication device, this also has a defect in that distortion occurs during tube modulation.

본 고안은 이와같은 종래의 결함을 감안하여 약전계 지역 및 강한 잡음지역에서 발생되는 잡음신호를 제거할 수 있게 안출한 것으로 이를 첨부된 제 1도의 도면에 의하여 상세히 설명하면 다음과 같다.The present invention is designed to remove the noise signal generated in the weak field and the strong noise area in consideration of such a conventional defect as described in detail with reference to the accompanying drawings of FIG.

제 1도는 본 고안의 잡음신호 제거회로도로서 이에 도시한 바와 같이 안테나(ANT)를 통상의 AM 고주파 및 중간주파 검파부(1)의 입력측에 접속함과 아울러 콘덴서(C1)를 통해 전계효과 트랜지스터(FET1)의 게이트에 접속하고, 그의 드레인은 저항(R1) 및 콘덴서(C2)(C3)를 통해 저항(R2) 및 트랜지스터(TR1)의 베이스에 접속하여 그의 콜렉터를 저항(R3) 및 콘덴서(C4)를 통해 저항(R4) 및 트랜지스터(TR2)의 베이스에 접속하며, 그의 콜렉터는 저항(R5) 및 에미터가 전원단자(Vcc)에 접속된 트랜지스터(TR3)의 베이스에 접속하여 그의 콜렉터를 저항(R6)(R7)을 통해 저항(R8) 및 트랜지스터(TR4)의 베이스에 접속하고, 그의 콜렉터는 저항(R9)을 통한 상기 AM 고주파 및 중간 주파 검파부(1)의 출력측과 함께 출력단자(OUT)에 접속하여 구성한 것이다.1 is a noise signal removing circuit diagram of the present invention, as shown therein, an antenna ANT is connected to the input side of a normal AM high frequency and intermediate frequency detector 1 , and a field effect transistor is provided through a capacitor C 1 . Is connected to the gate of (FET 1 ), and the drain thereof is connected to the base of the resistor (R 2 ) and the transistor (TR 1 ) through a resistor (R 1 ) and a capacitor (C 2 ) (C 3 ) to resist its collector. (R 3 ) and a capacitor (C 4 ) are connected to the base of the resistor (R 4 ) and the transistor (TR 2 ), the collector of which is a transistor in which the resistor (R 5 ) and the emitter are connected to the power supply terminal (Vcc). Is connected to the base of (TR 3 ) and its collector is connected to the base of the resistor (R 8 ) and the transistor (TR 4 ) via a resistor (R 6 ) (R 7 ), the collector of which is connected through a resistor (R 9 ) The output terminal OUT is configured together with the output side of the AM high frequency and intermediate frequency detector 1.

이와같이 구성된 본 고안의 작용 효과를 상세히 설명하면 다음과 같다.Referring to the effects of the present invention configured in this way in detail as follows.

전원단자(Vcc)에 전원이 인가되고, 안테나(ANT)를 통해 수신된 신호가 잡음신호가 없는 정상적인 신호일 경우에는 상기 안테나(ANT)를 통해 수신된 신호는 AM 고주파 및 중간주파 검파부(1)에 입력됨과 아울러 콘덴서(C1) 및 버퍼로 동작되는 전계효과 트랜지스터(FET1)를 통해 증폭되고, 그 증폭된 신호는 트랜지스터(TR1)에 의해 다시 증폭된후, 트랜지스터(TR2)의 베이스에 인가된다.When power is applied to the power supply terminal Vcc, and the signal received through the antenna ANT is a normal signal without a noise signal, the signal received through the antenna ANT is an AM high frequency and intermediate frequency detector 1. Amplified through the field effect transistor FET 1 which is input to the capacitor C 1 and the buffer, the amplified signal is amplified again by the transistor TR 1 , and then the base of the transistor TR 2 . Is applied to.

여기서, 상기 증폭된 신호의 최대 진폭레벨보다 트랜지스터(TR2)의 바이어스 전답을 높게 저항(R4) 값을 설정하면, 트랜지스터(TR2)가 오프되어 트랜지스터(TR3)의 베이스전류가 흐르지 못하므로 트랜지스터(TR3)도 오프되고, 이에 따라 트랜지스터(TR4)의 베이스에 저전위가 인가되어 트랜지스터(TR4)도 오프되므로 상기 AM 고주파 및 중간주파 검파부(1)를 통해 검파된 신호는 저항(R9)을 통해 출력단자(OUT)로 출력된다.Here, when the resistor R 4 value is set to have a higher bias response of the transistor TR 2 than the maximum amplitude level of the amplified signal, the transistor TR 2 is turned off so that the base current of the transistor TR 3 does not flow. Therefore, the transistor TR 3 is also turned off. Accordingly, a low potential is applied to the base of the transistor TR 4 , and the transistor TR 4 is also turned off. Thus, the signal detected by the AM high frequency and intermediate frequency detector 1 is It is output to the output terminal OUT through the resistor R 9 .

이와같은 상태에서 안테나(ANT)를 통해 잡음신호가 섞인 신호가 입력될 경우에는 상기와 같이 AM 고주파 및 중간주파 검파부(1)에 입력됨과 아울러 전계효과 트랜지스터(FET1)를 통해 증폭되고, 그 증폭된 신호는 콘덴서(C2)에 의해 고주파 신호가 제거되어 제 2도의 (a)에 도시한 바와 같이 출력되고, 그 출력된 신호는 트랜지스터(TR1)를 통해 다시 증폭되어 트랜지스터(TR2)의 베이스에 인가되고, 이때 상기에서 설정한 바와같이 증폭된 신호의 잡음신호 부분에서는 트랜지스터(TR2)의 베이스에 바이어스 전압으로 인가되어 트랜지스터(TR2)가 온되므로 전원단자(Vcc)의 전원이 저항(R5) 및 트랜지스터(TR2)를 통해 접지되고, 이에따라 그의 콜렉터에는 제 2도의 (b)에 도시한 바와같이 잡음신호 부분에서는 저전위의 펄스 신호가 출력되고, 상기 트랜지스터(TR2)가 온되어있을 경우에는 트랜지스터(TR3)의 베이스 전류가 흐르게 되어 그가 온되므로 그의 콜렉터에는 제 2도의 (c)에 도시한 바와 같이 반전된 펄스신호가 출력되고, 그 출력된 펄스신호는 트랜지스터(TR4)의 베이스에 인가되어 트랜지스터(TR4)가 온, 오프를 반복 즉, 고전위 신호 부분에서 트랜지스터(TR4)가 온되어 상기 AM 고주파 및 중간주파 검파부(1)를 통해 검파된 출력신호중에서 잡음 신호가 섞인 부분에서는 트랜지스터(TR4)를 통해 접지되므로 출력단자(OUT)로 제 2도의 (d)에 도시한 바와같이 잡음신호가 제거된 신호로 출력한다.In this state, when a signal mixed with a noise signal is input through the antenna ANT, the signal is input to the AM high frequency and intermediate frequency detector 1 and amplified by the field effect transistor FET 1 as described above. The amplified signal is removed as shown in (a) of FIG. 2 by the condenser C 2 and the high frequency signal is output, and the output signal is amplified again through the transistor TR 1 and the transistor TR 2 . of being applied to the base, wherein the power of the noise signal portion of the amplified signal is applied as a bias voltage to the base of the transistor (TR 2), so that the transistor (TR 2) on the power supply terminal (Vcc), as set by the is grounded through a resistance (R 5) and a transistor (TR 2), its collector is yiettara the noise signal portion as shown in the second degree (b) and outputs a pulse signal of a low potential, the transistor (TR 2) if there is one, the one inverted pulse signal as shown in, because the base current is flowed he came second degree in his collector (c) of the transistor (TR 3) and the output, that the output pulse signal transistor (TR 4) is applied to the base of the transistor (TR 4) is on, a repeat-off that is, the transistor (TR 4) in the high potential portion of the signal is on the AM radio frequency and intermediate frequency detector (1) The portion of the output signal detected through the mixed noise signal is grounded through the transistor TR 4 , and outputs the signal to the output terminal OUT as a signal from which the noise signal is removed as shown in FIG.

이상에서 설명한 바와같이 안테나에 혼입되는 잡음신호가 있을 경우에 그 잡음신호 부분의 검파 출력신호를 효율적으로 제거하게 되므로 청취자에게 최저의 청취감을 제공함은 물론 제품의 신뢰도를 높일 수 있는 효과가 있다.As described above, when there is a noise signal mixed in the antenna, the detection output signal of the noise signal portion is efficiently removed, thereby providing the listener with the lowest listening feeling and increasing the reliability of the product.

Claims (1)

안테나(ANT)를 통상의 AM 고주파 및 중간주파 검파부(1)의 입력측에 접속함과 아울러 전계효과 트랜지스터(FET1)의 게이트에 접속하고, 그의 드레인측은 트랜지스터(TR1)의 베이스에 접속하여 트랜지스터(TR1)의 콜렉터를 접지저항(R4) 및 트랜지스터(TR2)의 베이스측에 접속하며, 트랜지스터(TR2)의 콜렉터는 에미터가 전원단자(Vcc)에 접속된 트랜지스터(TR3)의 베이스측에 접속하여 트랜지스터(TR3)의 콜렉터를 트랜지스터(TR4)의 베이스측에 접속하고, 트랜지스터(TR4)의 콜렉터는 상기 AM 고주파 및 중간주파 검파부(1)의 출력축과 함께 출력단자(OUT)에 접속하여 구성함을 특징으로 하는 잡음신호 제거회로.The antenna ANT is connected to the input side of the normal AM high frequency and intermediate frequency detector 1, and is connected to the gate of the field effect transistor FET 1 , and the drain side thereof is connected to the base of the transistor TR 1 with and connected to the collector of the transistor (TR 1) to the earth resistance (R 4) and the base side of the transistor (TR 2), the collector of the transistor (TR 2) the emitter is connected to the power supply terminal (Vcc) transistor (TR 3 ) Is connected to the base side of the transistor TR 3 and the collector of the transistor TR 4 is connected to the base side of the transistor TR 4 , and the collector of the transistor TR 4 together with the output shaft of the AM high frequency and intermediate frequency detector 1. Noise signal elimination circuit characterized in that it is configured by connecting to the output terminal (OUT).
KR2019870015763U 1987-09-15 1987-09-15 Noise signal canceling circuit KR900002073Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019870015763U KR900002073Y1 (en) 1987-09-15 1987-09-15 Noise signal canceling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019870015763U KR900002073Y1 (en) 1987-09-15 1987-09-15 Noise signal canceling circuit

Publications (2)

Publication Number Publication Date
KR890007849U KR890007849U (en) 1989-05-17
KR900002073Y1 true KR900002073Y1 (en) 1990-03-13

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KR2019870015763U KR900002073Y1 (en) 1987-09-15 1987-09-15 Noise signal canceling circuit

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