KR960019962A - Tuner High Frequency Input Signal Strength Control Circuit - Google Patents

Tuner High Frequency Input Signal Strength Control Circuit Download PDF

Info

Publication number
KR960019962A
KR960019962A KR1019940028757A KR19940028757A KR960019962A KR 960019962 A KR960019962 A KR 960019962A KR 1019940028757 A KR1019940028757 A KR 1019940028757A KR 19940028757 A KR19940028757 A KR 19940028757A KR 960019962 A KR960019962 A KR 960019962A
Authority
KR
South Korea
Prior art keywords
high frequency
input signal
transistor
frequency input
signal
Prior art date
Application number
KR1019940028757A
Other languages
Korean (ko)
Other versions
KR0130024B1 (en
Inventor
최규환
Original Assignee
이형도
삼성전기 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이형도, 삼성전기 주식회사 filed Critical 이형도
Priority to KR1019940028757A priority Critical patent/KR0130024B1/en
Publication of KR960019962A publication Critical patent/KR960019962A/en
Application granted granted Critical
Publication of KR0130024B1 publication Critical patent/KR0130024B1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/3052—Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0035—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using continuously variable impedance elements
    • H03G1/0052—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using continuously variable impedance elements using diodes
    • H03G1/0058—PIN-diodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/50—Tuning indicators; Automatic tuning control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/52—Automatic gain control

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Circuits Of Receivers In General (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

튜너의 고주파 신호 입력 레벨이 지역별 전계강도의 세기에 무관하게 안정되게 유지시키기위한 튜너의 고주파 입력신호 강도 조절회로는 복조부에서 발생한 AGC전압(VAGC)의 조절에 따라 일정한 레벨의 고주파 신호를 튜너부에 제공하는 신호처리부를 포함하는데, 상기 신호처리부는, 베이스로 입력되는 AGC 전압(VAGC)의 크기에 따라 콜렉터전류와 에미터전류가 상호 반비례하여 변화하게 되는 트랜지스터(TR)와, 상기 트랜지스터(TR)의 콜렉터전류로 바이어스되며 그 바이어스 값에따라 변화하는 저항값을 가지고 고주파입력신호를 그라운드로 바이패스 시키는 제1핀 다이오드(D11)와, 상기 트랜지스터(TR)의 에미터전류로 바이어스되며 그 바이어스값에 따라 변화하는 저항값을 가지고 고주파 입력신호를 저잡음 증폭기(A)로 전달하는 제2핀 다이오드(D12)와, 상기 제9핀 다이오드(D12)를 거친 고주파입력신호를 증폭하여 상기 튜너부(20)로 전달하는 증폭기(A)로 구성되는 것을 특징지워진다.The tuner's high frequency input signal strength control circuit is designed to maintain the tuner's high frequency signal input level independently of the regional electric field strength. And a signal processing unit provided to the transistor, wherein the signal processing unit comprises: a transistor (TR) in which collector current and emitter current change in inverse proportion to each other according to the magnitude of AGC voltage (VAGC) input to a base, and the transistor (TR) The first pin diode D11 biases the collector current of the transistor and bypasses the high frequency input signal to ground with a resistance value that varies according to the bias value, and is biased by the emitter current of the transistor TR. A second pin diode D12 which transmits a high frequency input signal to the low noise amplifier A with a resistance value that changes according to the value; It is characterized in that it consists of an amplifier (A) for amplifying the high frequency input signal passing through the ninth pin diode (D12) to the tuner unit 20.

Description

튜너의 고주파 입력 신호 강도 조절회로Tuner High Frequency Input Signal Strength Control Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따른 블럭 구성도.3 is a block diagram according to the present invention.

Claims (1)

안테나에 입력되는 고주파 신호를 전계강도의 크기에 따라 제어가능한 신호 처리부(50)와, 상기 신호 처리부(50)의 고주파 출력을 받아 중간 주파신호를 발생하는 튜너부(20)와, 상기 튜너부(20)의 중간 주파출력에서 영상 및 음성신호를 검파출력하는 복조부(30)를 포함하는 고주파 신호 처리회로에 있어서, 상기 신호처리부는 베이스로 입력되는 AGC 전압(VAGC)의 크기에 따라 콜렉터전류와 에미터전류가 상호 반비례하여 변화하게되는 트랜지스터(TR)와, 상기 트랜지스터(TR)의 콜렉터전류로 바이어스 되며 그 바이어스 값에 따라 변화하는 저항값을 가지고 고주파입력신호를 그라운드로 바이패스시키는 제1핀 다이오드(D11)와, 상기 스트랜지스터(TR)의 에미터전류로 바이어스되며 그 바이어스값에 따라 변화하는 저항값을 가지고 고주파 입력신호를 저잡음 증폭기(A)로 전달하는 제2핀다이오드(D12)와, 상기 제2핀다이오드(D12)를 거친 고주파 입력신호를 증폭하여 상기 튜너부(20)로 전달하는 저잡음 증폭기(A)로 구성되는 것을 특징으로 하는 튜너의 고주파 입력신호 강도 조절회로.A signal processor 50 capable of controlling the high frequency signal input to the antenna according to the magnitude of the electric field strength, a tuner unit 20 generating an intermediate frequency signal by receiving the high frequency output of the signal processor 50, and the tuner unit ( In the high frequency signal processing circuit including a demodulation unit 30 for detecting and outputting video and audio signals at the intermediate frequency output of 20), the signal processing unit and the collector current according to the magnitude of the AGC voltage (VAGC) input to the base; The first pin for biasing the transistor TR and the collector current of the transistor TR, the emitter current changes in inverse proportion to each other, and bypasses the high frequency input signal to ground with a resistance value that changes according to the bias value. A low noise increase in the high frequency input signal has a bias value of the diode D11 and the emitter current of the transistor TR and the resistance value varies according to the bias value. And a low noise amplifier (A) for amplifying a high frequency input signal passing through the second pin diode (D12) and transmitting it to the tuner unit (20). A high frequency input signal strength control circuit of a tuner. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940028757A 1994-11-03 1994-11-03 High frequency input signal intensity adjustment circuit of tuner KR0130024B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940028757A KR0130024B1 (en) 1994-11-03 1994-11-03 High frequency input signal intensity adjustment circuit of tuner

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940028757A KR0130024B1 (en) 1994-11-03 1994-11-03 High frequency input signal intensity adjustment circuit of tuner

Publications (2)

Publication Number Publication Date
KR960019962A true KR960019962A (en) 1996-06-17
KR0130024B1 KR0130024B1 (en) 1998-10-01

Family

ID=19397014

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940028757A KR0130024B1 (en) 1994-11-03 1994-11-03 High frequency input signal intensity adjustment circuit of tuner

Country Status (1)

Country Link
KR (1) KR0130024B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100360119B1 (en) * 1999-12-17 2002-11-04 삼성전기주식회사 Tuner of pip television

Also Published As

Publication number Publication date
KR0130024B1 (en) 1998-10-01

Similar Documents

Publication Publication Date Title
KR920005527A (en) Wireless receiver
JPS6096008A (en) Photocurrent amplifying wide band amplifier
KR910010897A (en) AM radio receiver
ATE361581T1 (en) SELF-ADAPTABLE BIASING CIRCUIT TO ALLOW DYNAMIC CONTROL OF QUIZ CURRENT IN A LINEAR POWER AMPLIFIER
KR910010899A (en) Receiver unit that can respond quickly to multi-path reflection disturbances
KR920005455A (en) Amplification circuit
KR960019962A (en) Tuner High Frequency Input Signal Strength Control Circuit
KR950024416A (en) High frequency amplifier
KR890013917A (en) FM receiver
US4112371A (en) Muting and tuning indicator system for an FM receiver
CA2098028A1 (en) Low power integrated circuit white noise source
KR910007236A (en) RECEIVER circuit with first and second amplifiers
KR880010560A (en) amplifier
KR900002073Y1 (en) Noise signal canceling circuit
KR970077818A (en) Field-Sensitive Automatic Gain Control Device of RF Amplifier for Glass Antenna
KR960006257A (en) Tuner High Frequency Input Signal Intensity Control Circuit
KR890004490A (en) Output processing circuit
KR910009484Y1 (en) Selection circuit of broad band and narrow band
KR930006291Y1 (en) 2 input switching circuit
KR900001225Y1 (en) Automatic mono / stereo mode selection circuit in fm receiver
KR920005460A (en) Amplification circuit
JPH0641398Y2 (en) FM receiver level shift circuit
KR960003084A (en) Tuner Input Level Control Circuit
KR850002013Y1 (en) Am muting circuit
JPS599261Y2 (en) tremolo effect circuit

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070918

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee