KR890017819A - High speed and high voltage semiconductor device and manufacturing method - Google Patents

Abstract

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Description

High speed and high voltage semiconductor device and manufacturing method

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2 is a cross-sectional view of a silicon gate MOS transistor according to the present invention, and FIG. 3 (A)-(E) is a manufacturing process diagram of the silicon gate MOS transistor according to the present invention.

Claims (3)

A semiconductor substrate of a first conductivity type and a field oxide film formed on the surface of the semiconductor substrate and surrounding an active region; A MOS transistor for sleeping an insulating layer and a gate electrode on a surface of a semiconductor substrate between a region and a drain region, comprising: a low concentration semiconductor region of a second conductivity type over the source region, the drain region, and the lower portion of the insulating layer; A high-concentration and high-voltage semiconductor device having a low-concentration semiconductor region of a first conductivity type under a low-concentration semiconductor region below. A semiconductor substrate of a first conductivity type, a field oxide layer formed in a region other than a region in which an element on the semiconductor substrate is to be formed, and a source and a drain of the second conductivity type and a region between the source and the drain in the region where the element is to be formed. A method of forming a MOS transistor having a gate over a substrate of the method comprises the following steps and comprises a series of steps below. (a) forming a gate insulating film in a region where the device is to be formed; (b) forming a polycrystalline silicon gate electrode on the insulating film, and (c) implanting a first ion at a predetermined concentration into a second conductive type having a high concentration of a second conductivity type opposite to the first conductivity type on the entire surface of the substrate. (D) implanting a second ion of the same conductivity type at a lower concentration than the first ion implantation into the front surface of the substrate at a higher energy than the first ion implantation, and e) at a low concentration onto the front surface of the substrate Performing a third ion implantation of the first conductivity type with higher energy than implantation, and (f) a heat treatment to activate the ion implanted region. 3. The fabrication of high-speed and high-voltage semiconductor devices as recited in claim 2, wherein the second and third ion implantations in steps (d) and (e) have energy sufficient to penetrate the polycrystalline silicon gate electrode. Way. ※ Note: The disclosure is based on the initial application.