KR890015232A - Video recording prevention device - Google Patents

Video recording prevention device Download PDF

Info

Publication number
KR890015232A
KR890015232A KR1019880003668A KR880003668A KR890015232A KR 890015232 A KR890015232 A KR 890015232A KR 1019880003668 A KR1019880003668 A KR 1019880003668A KR 880003668 A KR880003668 A KR 880003668A KR 890015232 A KR890015232 A KR 890015232A
Authority
KR
South Korea
Prior art keywords
circuit
synchronous signal
composite
signal
video
Prior art date
Application number
KR1019880003668A
Other languages
Korean (ko)
Inventor
우세민
이광수
Original Assignee
우세민
이광수
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 우세민, 이광수 filed Critical 우세민
Priority to KR1019880003668A priority Critical patent/KR890015232A/en
Publication of KR890015232A publication Critical patent/KR890015232A/en

Links

Landscapes

  • Television Signal Processing For Recording (AREA)

Abstract

내용 없음No content

Description

비데오 녹화방지장치Video recording prevention device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 본 발명의 블럭다이아그램. 제 2 도는 본 발명의 회로도. 제 3 도는 본 발명의 타이밍차트도.1 is a block diagram of the present invention. 2 is a circuit diagram of the present invention. 3 is a timing chart of the present invention.

Claims (1)

복합영상신호가 입력되는 영상버퍼 AMP 회로(1)를 복합동기신호크램핑회로(2)와 비동기비데오발생회로(10)에 연결하고 복합동기신호크램핑회로(2)를 차례로 연결된 복합동기신호분리회로(3), 수평수식동기신호분리회로(4), 쉬프트레지스터회로(5)에 연결하여 복합동기신호분리회로(3)를 게이트복합동기신호발생회로(9)에 연결하여 복합동기신호분리회로(3)에 인가되어 분리된 복합동기신호(D)를 인가되도록하며 수평, 수직동기신호분리회로(4)를 쉬프트레지스터회로(5)와 임펄스게이팅발생회로(6)에 연결하여 수평동기신호(E2)를 인가시키고 쉬프트레지스터회로(5)에 임펄스게이팅발생회로(6)와 엔코딩동기신호펄스발생회로(7)를 연결시켜 펄스신호를 인가시키며 엔코딩동기신호펄스발생회로(7)는 콤바이너회로(8)와 게이트복합동기신호발생회로(9)와 연결하여 임펄스게이팅발생회로(6)는 혼합회로(11)에 연결된 콤바이너회로(8)에 연결시키고 게이트복합동기신호발생회로(9)와 비동기비디오발생회로(10)를 혼합회로(11)에 연결시켜 비동기비데오신호(L)와 복합동기게이트펄스(H), 콤바인드게이트신호(J)를 혼합시켜 엔코딩복합영상신호를 영상 AMP 회로(12)에 입력시켜 증폭출력되게 한 것을 특징으로 하는 비데오 녹화방지장치.Separating the composite synchronous signal connected with the image buffer AMP circuit (1) to which the composite video signal is inputted to the composite synchronous signal clamping circuit (2) and the asynchronous video generation circuit (10), and then connecting the composite synchronous signal clamping circuit (2). The composite synchronous signal separation circuit (3) to the gate composite synchronous signal generation circuit (9) by connecting the circuit (3), the horizontal formula synchronous signal separation circuit (4), and the shift register circuit (5). (3) to apply the separated composite synchronous signal (D) and to connect the horizontal and vertical synchronous signal separation circuit (4) to the shift register circuit (5) and the impulse gating generation circuit (6) the horizontal synchronous signal ( E 2 ) is applied to the shift register circuit 5 to connect the impulse gating generating circuit 6 and the encoding synchronous signal pulse generating circuit 7 to apply a pulse signal, and the encoding synchronous signal pulse generating circuit 7 is combined. Connection with the negative circuit (8) and the gate composite synchronous signal generator (9) The impulse gating generating circuit 6 is connected to the combiner circuit 8 connected to the mixing circuit 11 and the gate composite synchronous signal generating circuit 9 and the asynchronous video generating circuit 10 are connected to the mixing circuit 11. A video, characterized in that the asynchronous video signal (L), the composite synchronous gate pulse (H), and the combined gate signal (J) are mixed to input an encoded composite video signal to the video AMP circuit (12) for amplification and output. Anti-recording device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019880003668A 1988-03-31 1988-03-31 Video recording prevention device KR890015232A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019880003668A KR890015232A (en) 1988-03-31 1988-03-31 Video recording prevention device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880003668A KR890015232A (en) 1988-03-31 1988-03-31 Video recording prevention device

Publications (1)

Publication Number Publication Date
KR890015232A true KR890015232A (en) 1989-10-28

Family

ID=68241463

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880003668A KR890015232A (en) 1988-03-31 1988-03-31 Video recording prevention device

Country Status (1)

Country Link
KR (1) KR890015232A (en)

Similar Documents

Publication Publication Date Title
KR930005478A (en) Copper detection method and apparatus for television images obtained after film-to-TV conversion
KR920019194A (en) Image display device
KR830005799A (en) Control output synthesis key signal generator for television receiver
KR890015245A (en) Magnetic recording and reproducing apparatus for obtaining a separate clock signal from the luminance and color components of the video signal
KR850006821A (en) Sequentially Used Video Signal Processor
KR890015232A (en) Video recording prevention device
KR880014797A (en) Synchronous signal separation integrated circuit that can output burst gate pulse
KR880002167A (en) Video signal processing system
KR970078657A (en) Video data compression device
KR860002204A (en) Television Synchronous Signal Waveform Processing Equipment
KR910009101A (en) Data selector for color signal digital demodulator
JP2501187B2 (en) Super-impose device
KR920015938A (en) White Balance Inspection Circuit
JPS5755670A (en) Video display device
KR890015606A (en) Video signal transmission device
KR880003519A (en) Double scanning image processing device for TV receiver
KR890016776A (en) Code converters and encoders containing them
KR880005617A (en) Image storage
KR920014287A (en) Control Function Synchronization Method and Device
KR900001222A (en) Image Signal Synthesis Circuit for Stereo Video Camera
KR930005450A (en) Parallel line sensor type image processing tester
KR930003675A (en) Synchronization signal insertion method and circuit
KR930009401A (en) Line Synchronization and Frame Synchronization Detection Circuit of Multiplexed Analogue Components (MAC) Signal
KR960016398A (en) Double Scan Converter Circuit Using Synchronous Generation IC
KR890003217A (en) Image input device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application