KR890011345A - Facsimile System and Control Method Using Single Processor and Parallel Data Load Method - Google Patents

Abstract

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Description

Facsimile System and Control Method Using Single Processor and Parallel Data Load Method

Since this is an open matter, no full text was included.

2 is a circuit diagram according to the present invention.

Claims (2)

In the facsimile system, a ROM (4) containing a program necessary for operating the facsimile data and various tables necessary for coding or decoding, and temporarily storing the data required for the program execution of the ROM (4), A RAM 5 for storing a kind of functions required by the user and storing various types of functions, telephone numbers, names, etc., and waiting for a while until coding data is needed for transmission or decoding, and a direct memory access unit for a predetermined channel; In the case where the timer is mounted, the program of the ROM 4 is processed according to an input command to supply control signals such as addresser, data, and write / read to the system, and to transfer image data to the direct memory access unit. The central processing unit 1 for granting the input / output control right of the control signal, and Since the address and data of the central processing unit 1 are mixed and output through one bus, the address is latched using an address signal indicating that the address is output time or the address of the input / output control or the RAM 5 ROM 4 is designated. The data is entered into the central processing unit 1 during the address latch 2 and the data enable time indicating that the central processing unit 1 is ready to read or write data. Whether the data buffer 3 is buffered so that the data bus can be loaded and the signal of the predetermined signal line, which is an address line indicating the state of the central processing unit 1, and control signals such as read / write, etc. Indicate whether memory is read or not when the "low" byte data buffer of the data buffer 3 is turned on or when the "high" byte data buffer is turned on. A central processing unit signal control unit 6 for outputting various signals and controlling input and output force of the RAM 5 and ROM 4 by using signals and whether they are low / high byte, and the address latch An input / output decoder circuit 7 for multiplexing / demultiplexing a predetermined address signal of (2) to generate data input / output and chip enable control signals for each signal processing and driving unit, and real-time clock signal generation for generating a clock signal set at a predetermined period; A circuit 8, a digital image processing circuit 10 for optimally digitizing the analog data input from the image image sensor, and supplying a serial data and a synchronous clock, and a drive signal of the thermal printer head TPH. Reads the data in one line in series with the direct bus interface thermal printer head controller 9 and generates the direct bus interface thermal printer. The thermal printer unit 14, which receives the drive signal of the controller 9, generates thermal paper, and is connected to the private exchanger and the telephone line to attenuate or amplify the input / output signal of the line according to the standard required by the modem, A line interface device 11 for checking on / off and dialing, a modem 12 for demodulating and demodulating data on a parallel data bus with the line interface device 11, and a document to be recorded and a recording sheet A stem motor control unit 15 for controlling data, an LCD and key array control circuit 16 for directly writing byte data to a display unit or reading data of a key input state, and reading the data of one line in series; A circuit comprising a scanner (13) for supplying an image preprocessing circuit (10). In the facsimile data transmission method, a digital image preprocessing unit processes a line of data in series by driving an image sensing sensor during copying in a first step of checking a transmission / reception mode and a copy mode when performing a facsimile mode. The second process of compensating and digitizing the data, the third process of latching the data digitized in the second process in the thermal printer unit and driving the printer, and the process data digitized in the third process. A fourth step of checking; a fifth step of completing copying according to whether copying is completed in the fourth step; if it is not an ordinary letter; and moving the image data for coding and decoding during transmission in the first step; A sixth process of specifying an access first channel as a digital image preprocessing process and a second channel as a modem; And a seventh process of converting data transferred from digital image preprocessing to serial data and printing the reverse process of the sixth process upon reception in step 1. ※ Note: The disclosure is based on the initial application.