KR890008946A - Semiconductor integrated circuit device with contact hole - Google Patents

Semiconductor integrated circuit device with contact hole

Info

Publication number
KR890008946A
KR890008946A KR1019880014451A KR880014451A KR890008946A KR 890008946 A KR890008946 A KR 890008946A KR 1019880014451 A KR1019880014451 A KR 1019880014451A KR 880014451 A KR880014451 A KR 880014451A KR 890008946 A KR890008946 A KR 890008946A
Authority
KR
South Korea
Prior art keywords
integrated circuit
semiconductor integrated
insulating film
circuit device
contact hole
Prior art date
Application number
KR1019880014451A
Other languages
Korean (ko)
Other versions
KR920007446B1 (en
Inventor
다이지 에마
Original Assignee
야마모도 다꾸마
후지쓰 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 야마모도 다꾸마, 후지쓰 가부시끼가이샤 filed Critical 야마모도 다꾸마
Publication of KR890008946A publication Critical patent/KR890008946A/en
Application granted granted Critical
Publication of KR920007446B1 publication Critical patent/KR920007446B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

내용 없음No content

Description

콘택트 호울을 갖는 반도체 집적회로 장치Semiconductor integrated circuit device with contact hole

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도는 본 발명의 바람직한 실시예의 주요부분의 평면도,1A is a plan view of an essential part of a preferred embodiment of the present invention,

1B도와 1C도는 제1A도에 도시된 선(X-X, Y-Y)을 따라 절단된 단면도.1B and 1C are sectional views taken along the lines X-X and Y-Y shown in FIG. 1A.

Claims (8)

반도체 기판; 산화레지스트 마스크가 사용되는 선택적 산화법에 의하여 반도체 기판 표면상에 형성되는 파일드 절연막; 파일드 절연막상에 형성되는 절연막; 콘택트 호울을 가지며, 콘택트 호울의 에지가 피일드 절연막의 에지에 의하여 정해지는 제1방향으로 연장되고 절연막을 패터닝함으로써 정해지는 제2방향으로 연장되는 절연막 및 기판표면과 접촉하도록 콘택트 호울을 커버하는 도전막으로 구성되는 반도체 집적회로장치.Semiconductor substrates; A pile insulating film formed on the surface of the semiconductor substrate by a selective oxidation method in which an oxide resist mask is used; An insulating film formed on the pile insulating film; A conductive hole having a contact hole and covering the contact hole so that the edge of the contact hole extends in a first direction defined by the edge of the shielded insulating film and in contact with the surface of the insulating film and the substrate extending in a second direction determined by patterning the insulating film; A semiconductor integrated circuit device composed of a film. 제1항에 있어서, 제2방향은 인접한 도전막사이의 피치를 감소하는 것을 요구하는 1방향이며, 제1방향은 제2방향과 수직인 방향인 것을 특징으로 하는 반도체 집적회로장치.2. The semiconductor integrated circuit device according to claim 1, wherein the second direction is one direction that requires to reduce the pitch between adjacent conductive films, and the first direction is a direction perpendicular to the second direction. 제1항에 있어서, 제1방향으로 연장된 피일드 절연막의 에지는 선택적 산화법에 의하여 제조된 버드 버크부인 것을 특징으로 하는 반도체 집적회로장치.The semiconductor integrated circuit device according to claim 1, wherein the edge of the feed insulating film extending in the first direction is a bird buck portion manufactured by a selective oxidation method. 제1항에 있어서, 도전막은 피일드 절연막의 에지상에 연장되는 것을 특징으로 하는 반도체 집적회로장치.The semiconductor integrated circuit device according to claim 1, wherein the conductive film extends on an edge of the shielded insulating film. 제1항에 있어서, 콘택트 호울을 통하여 노출된 기판의 표면부가 절연막에 형성된 콘택트 호울의 크기 보다 더 작은 제2방향에서의 크기를 갖는 것을 특징으로 하는 반도체 집적회로장치.The semiconductor integrated circuit device according to claim 1, wherein the surface portion of the substrate exposed through the contact hole has a size in the second direction smaller than the size of the contact hole formed in the insulating film. 제1항에 있어서, 기판은 불순물로 도핑된 활성영역으로 구성되며, 및 도전막은 기판에 형성된 활성영역과 접촉되어 있는 것을 특징으로 하는 반도체 집적회로장치.The semiconductor integrated circuit device according to claim 1, wherein the substrate is composed of an active region doped with impurities, and the conductive film is in contact with an active region formed on the substrate. 제1항에 있어서, 장치는 적층 콘덴서형 다이나믹 랜덤 억세스 메모리장치이며, 도전막은 장치의 메모리콘덴서의 쌍 전극종 하나인 것을 특징으로 하는 반도체 집적회로장치.The semiconductor integrated circuit device according to claim 1, wherein the device is a multilayer capacitor type dynamic random access memory device, and the conductive film is one of a pair of electrode types of the memory capacitor of the device. 제1항에 있어서, 장치는 적층 콘덴서형 다이나믹 랜덤 억세스 메모리장치이며, 도전막은 비트선인 것을 특징으로 하는 반도체 집적회로장치.The semiconductor integrated circuit device according to claim 1, wherein the device is a multilayer capacitor type dynamic random access memory device, and the conductive film is a bit line. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019880014451A 1987-11-05 1988-11-03 Semiconductor integrated circuit device having contact hole KR920007446B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62-278285 1987-11-05
JP62278285A JPH01120847A (en) 1987-11-05 1987-11-05 Semiconductor device

Publications (2)

Publication Number Publication Date
KR890008946A true KR890008946A (en) 1989-07-13
KR920007446B1 KR920007446B1 (en) 1992-09-01

Family

ID=17595216

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880014451A KR920007446B1 (en) 1987-11-05 1988-11-03 Semiconductor integrated circuit device having contact hole

Country Status (3)

Country Link
EP (1) EP0315421B1 (en)
JP (1) JPH01120847A (en)
KR (1) KR920007446B1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03266437A (en) * 1990-03-16 1991-11-27 Toshiba Corp Manufacture of semiconductor device
US5780323A (en) 1990-04-12 1998-07-14 Actel Corporation Fabrication method for metal-to-metal antifuses incorporating a tungsten via plug
US5057451A (en) * 1990-04-12 1991-10-15 Actel Corporation Method of forming an antifuse element with substantially reduced capacitance using the locos technique
US5614756A (en) 1990-04-12 1997-03-25 Actel Corporation Metal-to-metal antifuse with conductive
KR930006732B1 (en) * 1991-05-08 1993-07-23 재단법인 한국전자통신연구소 Semiconductor substrate having the structure assembly varied and method of the same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8600769A (en) * 1986-03-26 1987-10-16 Philips Nv METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Also Published As

Publication number Publication date
KR920007446B1 (en) 1992-09-01
EP0315421B1 (en) 1994-05-18
EP0315421A1 (en) 1989-05-10
JPH0571182B2 (en) 1993-10-06
JPH01120847A (en) 1989-05-12

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