KR890005611A - How to address memory using a data bus - Google Patents

How to address memory using a data bus Download PDF

Info

Publication number
KR890005611A
KR890005611A KR870010069A KR870010069A KR890005611A KR 890005611 A KR890005611 A KR 890005611A KR 870010069 A KR870010069 A KR 870010069A KR 870010069 A KR870010069 A KR 870010069A KR 890005611 A KR890005611 A KR 890005611A
Authority
KR
South Korea
Prior art keywords
memory
data bus
address memory
data
microprocessor
Prior art date
Application number
KR870010069A
Other languages
Korean (ko)
Inventor
김광석
Original Assignee
안시환
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 안시환, 삼성전자 주식회사 filed Critical 안시환
Priority to KR870010069A priority Critical patent/KR890005611A/en
Publication of KR890005611A publication Critical patent/KR890005611A/en

Links

Landscapes

  • Microcomputers (AREA)

Abstract

내용 없음No content

Description

데이타 버스를 이용하여 메모리를 어드레싱 하는 방법How to address memory using a data bus

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

첨부도면은 본 발명을 적용하기 위한 회로도.The accompanying drawings are circuit diagrams for applying the present invention.

Claims (1)

마이크로프로세서(10)와 메모리(80)를 구비하여 구성되는 시스템에서 메모리(80)의 내의 데이타를 액세스함에 있어서, 메모리(80)의 칩 인에이블 신호 발생용 배치(40)와 하위 어드레스 발생용래치(50)와 상위 어드레스 발생용 래치(60)에 의해 데이타버스를 통하여 메모리(80)의 어드레스를 지정하고, 메모리(80)의 데이타를 단방향 3상태 버퍼(70)를 통해 데이타 버스로 읽어들이며, 상기한 래치(40-60)와 단방향 3상태 버퍼(70)와 메모리(80)의 제어신호로서 마이크로 프로세서(10)로부터의 입출력 제어신호를 사용하는 것을 특징으로 하는 데이타버스를 이용하여 메모리를 어드레싱 하는 방법.In accessing data in the memory 80 in a system including the microprocessor 10 and the memory 80, the chip enable signal generation arrangement 40 and the lower address generation latch of the memory 80 are accessed. The address of the memory 80 is designated by the 50 and the upper address generation latch 60 via the data bus, and the data of the memory 80 is read into the data bus through the one-way tri-state buffer 70, Addressing the memory using the data bus, characterized in that the input and output control signals from the microprocessor 10 are used as the control signals of the latches 40-60, the unidirectional tri-state buffer 70, and the memory 80. How to. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR870010069A 1987-09-11 1987-09-11 How to address memory using a data bus KR890005611A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR870010069A KR890005611A (en) 1987-09-11 1987-09-11 How to address memory using a data bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR870010069A KR890005611A (en) 1987-09-11 1987-09-11 How to address memory using a data bus

Publications (1)

Publication Number Publication Date
KR890005611A true KR890005611A (en) 1989-05-16

Family

ID=68343636

Family Applications (1)

Application Number Title Priority Date Filing Date
KR870010069A KR890005611A (en) 1987-09-11 1987-09-11 How to address memory using a data bus

Country Status (1)

Country Link
KR (1) KR890005611A (en)

Similar Documents

Publication Publication Date Title
KR890008691A (en) Data processor devices
KR910001771A (en) Semiconductor memory device
KR870011537A (en) Data Processing System Using Address Translation
KR890017619A (en) Multi-bus microcomputer system
KR920004946A (en) VGA input / output port access circuit
KR890005611A (en) How to address memory using a data bus
KR950033829A (en) Information utilization circuit of memory chip
KR880000961A (en) Video memory
KR860009339A (en) Auxiliary memory
KR900012453A (en) Interprocessor communication circuit using dual port memory
KR880002072A (en) CRT control circuit
KR910006845A (en) Central memory expansion unit
KR880008157A (en) Memory recording logic unit for computer
KR920014047A (en) Data access circuits
KR920022102A (en) Memory address mapping device
KR920000069A (en) Memory IC with Parallel and Serial Output Conversion
KR920022110A (en) PC Interrupt System
JPH0356983U (en)
KR850004666A (en) Transparent image data control circuit
JPS54123841A (en) Semiconductor integrated memory element
KR890005612A (en) Memory bank select circuit
KR940017592A (en) Light Latch Control Device of Memory Board
KR910012928A (en) Computer memory expansion system
KR900002191A (en) Buffer Memory Duplexing Control Circuit
KR890002761A (en) Dual Port Control Circuit of One Board Memory

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E902 Notification of reason for refusal
SUBM Submission of document of abandonment before or after decision of registration