KR890004416Y1 - Reset pulse generator for synclonising circuit - Google Patents

Abstract

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Description

Reset pulse generator for synchronization

1 is a blur diagram of a circuit according to the present invention.

FIG. 2 is a detailed circuit diagram of a synchronous separator used in FIG.

3 is a horizontal synchronous reset pulse generation circuit diagram.

4 is a vertical synchronous reset pulse generation circuit diagram.

5, 6, 7, and 8 are horizontal synchronous reset pulse timing diagrams.

9, 10, 11, and 12 are vertical synchronous reset pulse timing diagrams.

* Explanation of symbols for main parts of the drawings

1: Synchronous Separator 2: TTL Level Voltage Converter

3, 4: pulse width control unit 5: amplification unit

The present invention relates to a circuit that can easily adjust the timing of each synchronization signal by adjusting the pulse width after converting the vertical and horizontal synchronization signal obtained by synchronizing the composite video signal (COMPOSITHDEO SIGNAL) to the TTL level.

In the synchronous deflection circuit of the TV, the horizontal synchronous signal and the vertical synchronous signal are used. The horizontal synchronous signal and the vertical synchronous signal obtained by synchronizing the composite video signal are not synchronized with the synchronization signals of the original composite video signal, and an error occurs. Done.

Therefore, as a means of matching the timing of the horizontal synchronizing signal and the vertical synchronizing signal, conventionally, a special synchronous separation integrated device is used or a simple separated horizontal and vertical synchronizing signal is also processed by a differential circuit to generate a reset pulse to generate a horizontal and vertical synchronizing signal Matched.

However, even when the horizontal and vertical synchronization signals are a little unstable, the time constant value of the differential circuit changes frequently, which makes it difficult to output an accurate reset pulse.

Accordingly, the present invention provides a circuit for generating stable reset pulses by freely adjusting the timing of the synchronization signal by adjusting the pulse widths of the horizontally synchronized signals and the vertically synchronized signals separated from each other. The purpose is.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a TTL level (input of a level voltage; Vin 2), in which a composite image signal is synchronously separated and a horizontal synchronous signal and a vertical synchronous signal are synchronously separated from the separation separator 1. Vin 5v, input low level voltage; Vil 0 Vil A TTL level voltage converter 2 for converting to 0.8v, a pulse width adjusting unit 3 for adjusting the pulse width of the synchronous signals of which the level is changed, and an amplifier 5 for amplifying the synchronous signals in which the pulse width is adjusted; Is a block diagram of a circuit of the present invention, which is composed of

FIG. 2 is a detailed circuit diagram of the synchronous separation unit 1 used in FIG. 1, which is composed of a synchronous separation integrated device, a plurality of resistors and capacitors, and converts a composite image signal into a horizontal synchronization signal (H-SYNC) and a vertical synchronization signal. This is a circuit diagram separated by (V-SYNC).

FIG. 3 shows a converter 2 for converting the horizontal synchronous signal separated in FIG. 2 into a TTL level, and a pulse width adjuster 3 for connecting to a direct element used to adjust the pulse width, and a horizontal pulse width controlled. It is a horizontal synchronizing reset pulse generation circuit composed of an amplifier 5 for amplifying a synchronization signal.

4 is a vertical synchronous reset pulse generation circuit configured to amplify a vertical synchronous signal into a pulse width conversion, a TTL level voltage conversion, and a vertical synchronous signal as shown in FIG.

5 to 8 are horizontal synchronous reset pulse timing diagrams, and FIGS. 9 to 12 are vertical synchronous reset pulse timing diagrams.

The circuit operation of the present invention having the configuration as described above will be described in detail.

First, before describing the circuit operation of the present invention, an integrated device used as a means for adjusting the pulse width of a synchronization signal, for example, a method of triggering a monostable multivibrator, first, sets the input stages 1A and 2A to "low". And hold the input stages 1B and 2B from "low" to "high", i.e., up edge, and trigger them. Second, keep the input stages 1B and 2B "high." There is a method of triggering 2A) from "high" to "low", that is, down edge.

In addition, converting the voltage of the synchronous signal separated by the synchronous separation unit 1 into the TTL level is a means for matching the voltage of the integrated element controlling the pulse width.

When explaining the operation of the circuit of the subject innovation, and then the composite video signal is separated by a horizontal sync signal and vertical sync signals over the sync separation unit (1) constructed as a second assist the horizontal sync signal is a transistor (Q ₄₎ (Q ₅₎ Is applied to the input of an integrated element, i.e., a monostable multivibrator, which is used as a means for adjusting the pulse width through a TTL level voltage conversion circuit 2A composed of a resistor and R ₂₄ -R ₂₇ . It is applied to the input terminal of the monostable multivibrator via a TTL level voltage conversion circuit 2B composed of a transistor Q ₈ and a resistor R ₃₈ and R ₃₉ .

However, in inputting the horizontal and vertical synchronization signals separated by the synchronization separation unit 1 to the input terminals 1A and 1B of the monostable multivibrator, the synchronization signal is oscillated at the pulse up edge. The synchronization signal such as H-SYNC) and the vertical synchronization signal (V-SYNC) of FIG. 9 is input to the input terminal 1B of the monostable multivibrator while the synchronization signal is oscillated at the fall-down edge. A synchronization signal such as the synchronization signal H-SYNC and the vertical synchronization signal V-SYNC in FIG. 11 may be connected to the input terminal 1A of the monostable multivibrator.

When the synchronous pulse is applied to the input terminal of the monostable multivibrator as described above, in the primary side pulse width control circuit 3A, the horizontal synchronous signal is determined by the variable resistor VR ₃ and the capacitor C ₁₈ . When the pulse up edge is applied to the input terminal 1B of the monostable multivibrator like the horizontal synchronous signal H-SYNC of FIG. 5, the horizontal synchronous output is output from the primary pulse width control circuit 3A. signal is a pulse width is converted to at t ₁ t ₂ are output as degrees of claim 5 1Q into the secondary side pulse width control circuit is input to (3B) pulses of the output horizontal synchronization signal pulse width is t ₂ at t ₃ A pulse, such as 2Q in FIG. 5, is outputted, where the width t ₃ of the output pulse depends on a time constant determined by the variable resistor VR ₁ and the capacitor C ₁₉ .

Then, the horizontal synchronization signal separated by the synchronization separation unit 1 inputs a pulse-down edge such as the horizontal synchronization signal H-SYNC of FIG. 7 to the input terminal 1A of the monostable multivibrator, thereby adjusting the primary pulse width. A pulse equal to 1Q in FIG. 7 outputted from the output terminal 1Q of (3A) is inputted to the input terminal 2A of the secondary side pulp / width control circuit 3B, and is output from the secondary side pulse width control circuit 3B. The pulse is outputted as shown in 2Q of FIG. 7, wherein the width of the pulse is determined by the time constant determined by the variable resistor and the capacitor in the primary and secondary pulse width control circuits 3A and 3B.

As such, the horizontal synchronous signal whose pulse width is determined by the time constant is amplified and output through the amplifier 5A including the transistors Q ₆ , Q ₇ , resistors R ₃₂ -R ₃₇ , and capacitor C ₂₀ . do.

Next, a process in which the vertical synchronization signal V-SYNC separated by the synchronization separator 1 becomes a reset pulse by adjusting the width of the pulse will be described.

The vertical synchronizing signal V-SYNC is input to a sig- nal element used as a means for adjusting the width of the pulse through the TTL level voltage conversion circuit 2B composed of the transistor Q _S and the resistors R ₃₈ and R ₃₉ . Is applied to the terminal.

However, when a pulse such as the vertical synchronous signal V-SYNC of FIG. 11 is applied to the input terminal 1A of the monostable multivibrator, the vertical synchronous signal output from the primary pulse width control circuit 4A has a width of t. _The pulse of the vertical synchronization signal converted from ₁ 'to t ₂ ' and outputted as 1Q in FIG. 11 and input to the secondary side pulse width control circuit 4B is outputted from t ₂ 'to t ₃ '. A pulse equal to 2Q in FIG. 11 is output.

At this time, the pulse width of the vertical synchronization signal output from the primary side and the secondary side depends on the time constant.

The vertical synchronization signal output in this manner is amplified and output through the amplifier 5B including the transistors Q ₉ (Q ₁₀ ), the resistors R ₄₄ -R ₄₉ , and the capacitor C ₃ .

6, 8, 9, and 12 are pulses output by selectively connecting the synchronization signal separated by the synchronization separator 1 to the input terminals 1A and 1B of the monostable multivibrator. And the timing output based on the selection of the input and output terminals of the primary and secondary pulse width control circuits. The pulse widths are determined by the time constants of the pulse control circuits on the primary and secondary sides. It depends on the value determined.

According to the present invention operating as described above, the composite video signal can be freely adjusted timing of the synchronization signal by adjusting the width of the pulse of the horizontal synchronization signal and the vertical synchronization signal, which is separated from the synchronization can provide a stable reset pulse There is this.

Claims (1)

The voltage of the integrated device used as a means for controlling the pulse width of each of the synchronization signal separated by the synchronization separator 1 for separating the composite image signal into a horizontal synchronization signal and a vertical synchronization signal. Receives the output of the TTL level voltage converter 2 and the TTL level voltage converter 2 to convert the level to match the level, and sets the pulse width of each synchronization signal by a value determined by the time constant. In order to amplify the pulses output from the pulse width adjusting section 3 and 4 and the pulse width adjusting section 3 and 4, respectively, the transistors Q ₆ and Q ₇ resistive ( R _32- R ₃₇ ) Synchronous generation, characterized in that it comprises an amplifier (5) consisting of a condenser (C ₂₀ ) to output a stable reset pulse by adjusting the width of the pulses of the horizontal and vertical synchronization signal Reset pulse generator circuit.