KR890002677B1 - Color synchronizing signal oscillator - Google Patents

Abstract

The circuit is for matching the phase of the delayed input primary colour signal with the phase of no-delayed one to provide clear image by inverting the clock pulse corresponding to the horizontal synchronous freq. The circuit includes a synchronous signal generator for applying the inversed clock pulse to the point placed between an image signal input circuit and an image signal amplifier, and a mis-synchronisation detecting circuit for detecting the delayed colour signal and controlling the state signal of the clock pulse provided with the clock inverter.

Description

Primary color synchronization generator

1 is a circuit diagram of the present invention.

2 (a) is a state diagram of output color video signals at the time of primary color signal delay.

2 (b) is a waveform diagram of each part of the circuit diagram of the present invention at the time of the primary color signal delay.

* Explanation of symbols for main parts of the drawings

1: Video signal input unit 2: Video signal amplifier

3: video signal output part CRT: cathode ray tube

5 synchronization generator 6 differential circuit

7: charge and discharge circuit 10: paulownia detector

15: clock inverting portion I ₁ , I ₂ . I ₇ : Inverter

OR ₁ , OR ₂ : Ocatenate C ₁ , C ₂ , C ₃ : Condensate

R ₁ , R ₂ , R ₃ : Resistance A ₁ , A ₂ , A ₃ : Questionnaire

EX ₁ , EX ₂ : Exclusive Oagate FF ₁ , FF ₂ , FF ₃ : RS-Flip-Flop

FF ₅ , FF ₆ : D-flip flop FF ₇ : T-flip flop

The present invention relates to a primary color synchronization generating circuit and inverts a clock pulse to match a phase between a delayed color signal and an undelayed color signal to match the synchronization signal of the color image signal to prevent the delay between the color signals.

When inputting the primary, red, green, blue (R) (G) (B) signal from the personal, computer, video camera, video tape recorder, etc. to the video signal amplifying unit, the external noise or each gate during transmission Due to the difference in the transmission delay time between the color signal delay occurs.

This color signal delay does not affect image quality even when blurring is performed in the case of a monitor whose horizontal resolution is not very high. However, because of the high resolution in a high-resolution monitor, a slight color signal delay in transmission Since the interference shape between color signals is generated, there is a disadvantage in that good image quality cannot be obtained.

An object of the present invention is to synchronize a primary color signal that is applied with a delay by inverting a clock pulse according to a horizontal synchronization frequency so that the phase of the primary color signal that is not delayed matches the phase of the color signal, thereby providing a clear picture quality screen. And a synchronization generator for applying the clock pulse of the clock inverting unit between the image signal input unit and the image signal amplifying unit. The AND gate connected to the inverter by the color signal through the differential circuit and the charge / discharge circuit is misaligned due to the delay of the color signal. The oscillator detector is configured to control the output of the T flip-flop and to control the state signal of the clock pulse of the clock inverter. This will be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram of the present invention, in which a synchronization generator 5 is formed between an image signal input unit 1 and an image signal amplifier 2, and the image signal amplified by the image signal amplifier 2 is a video signal output unit. The synchronization generating unit 5 is configured to be applied to the cathode ray tube CRT through (3), and the primary color signals R ', G', and B 'of the image signal input unit 1 are applied to the set terminal S. At the same time, it is inverted through the inverters I ₁ -I ₃ and then output from the RS-flip flop FF ₁ -FF ₃ and the RS-flip flop FF ₁ -FF ₃ applied to the reset terminal R. It is configured to be applied to the video signal amplifier 2 through the D-flip flops FF ₄ -FF ₅ to stabilize the color signals R, G, and B.

클럭 지연된 상태로 인가되므로 클럭펄스가 반전될때 동작을 안정시키도록 구성한 것이다.At this time, the clock pulse of the clock inverting unit 15 is applied to the clock terminal CK of the RS-flip flop FF ₁ -FF _{3 as it} is, and the clock terminal CK of the D-flop flop FF ₄ -FF ₆ . The clock pulse of the clock inverting unit 15 is configured to be applied after being inverted by the inverter I ₄ and the D-flip flop (FF ₄ -FF ₆ ) connected to the rear end of the RS-flip flop (FF ₁ -FF ₃ ). Is greater than the clock of the RS-Flip-Flop (FF ₁ -FF ₃ )

Since the clock is applied in a delayed state, it is configured to stabilize the operation when the clock pulse is inverted.

The output of the synchronization generating unit 5 is applied to the oscillator detecting unit 10 to detect the delay of the color image signal. Red, green, and blue (R) (G) (B) color video signals are applied to the gates EX ₁ and EX ₂ so that the high level status signal is detected when the OR signal is detected by the OR gate ₂ . After configured to output through the diode (D ₁ ) in the differential circuit (6) consisting of a capacitor (C ₁ ) and a resistor (R ₁ ), after the capacitor (C ₂ ) (C ₃ ), resistor (R ₂ ) (R ₃ It is configured to be applied to the AND gate (A ₃ ) through a charge and discharge circuit (7) consisting of one side through the inverter (I ₇ ) and then clocked to the clock terminal (CK) of the T-flip flop (FF ₇ ) The oscillator detector 10 is configured to be applied as a pulse, and a positive pulse voltage of the differential circuit 6 is applied to the capacitor C ₂ . If a negative pulse voltage is applied during the period when the charged voltage is discharged by the time constant C ₂ × R ₂ , the AND gate A ₃ is configured to detect the positive pulse for a predetermined narrow time.

The T flip-flop FF ₇ outputs a state signal that is inverted each time a clock pulse is applied to the clock terminal CK. The clock inversion unit 15 controlling the inversion state of the clock pulse according to the state signal is provided. flip flop (FF in the inverter (I ₅₎ (I ₆₎ and aND gates (a ₁₎ (a ₂₎ and Iowa gate consists of a (OR ₁₎ Iowa gate (OR ₁₎ output synchronous generation part 5 of the _It is configured to be applied to the clock terminal CK of ₁ -FF ₆ ).

Clock inverted portion (15) in the present invention configured in this way is a clock pulse as soon as applied to one side of the AND Kate (A ₁₎ at the same time be applied to one side of the AND gate (A ₂₎ and then inverted by the inverter (I ₅₎ and ohdonggi detector 10. the output end geyiyi agent (a ₂₎ is applied intact to the other as soon the same time the inverter (I ₆₎ after the reverse in, and be applied to the other side of the aND gates (a ₁₎ aND gates (a ₁₎ (a of The output of ₂ ) is applied to the clock terminal CK of the flip-flops FF _1- FF ₆ of the synchronization generating unit 5 through the oragate OR ₁ so that the T-flip flop of the misalignment detection unit 10 is provided. The clock pulse CP in the forward or reverse direction is output according to the state signal applied at (FF ₇ ).

That is, when the high level status signal is output to the output terminal Q of the T-flip flop FF ₇ , the AND gate A ₁ is cut off by the low level signal inverted by the inverter I ₆ , and the AND gate A ₂ ) maintains the conduction state, so the clock pulse CP inverted in the inverter I ₅ is applied to the synchronization generator 5 through the OR gate OR ₁ , but the output of the T-flip flop FF ₇ is maintained. When the inverted low level state signal is output to the terminal Q, the AND gate A ₂ is interrupted and the high level state signal inverted by the inverter I ₆ is applied to the other side of the AND gate A ₁ , so that the clock pulse is generated. CP performs an operation which is applied to the synchronization generating unit 5 through the AND gate A ₁ and the OR gate OR ₁ as it is, and a clock pulse outputted by the output of the T-flip flop FF ₇ ( The phase of CP) is controlled.

The primary color signals R '(G') (B ') output from the video signal input unit 1 are set at the set terminals S of the RS-flip flops FF ₁ -FF ₃ of the synchronization generating unit 5. When applied, the inverters I ₁ -I ₃ invert the primary color signals R '(G') and B 'and apply them to the reset terminal R so that the clock pulse of the clock inverting unit 15 is clock terminal. Color signals R, G, and B corresponding to the respective primary color signals are generated at the output terminals Q of the RS-flip flops FF _{1 to} FF ₃ applied to the CK. When the primary color signal is applied, the color signal shown above is displayed by the primary color signals R '(G') and B 'when the primary color signal is applied.

At this time, if the primary signal of red (R ¹ ) is delayed and applied like a dotted line, unwanted cyan and magenta color signals are output to the color bar, but RS-flip-flop (FF ₁ -FF ₃ ) is positive of clock pulse (CP). When the clock pulse CP is applied as shown in FIG. 2 (a), the output side of the RS-flip-flop FF _{1 to} FF ₃ is the positive edge as shown in FIG. The color signals R (G) (B) synchronized with F) are output.

; 이는 제2(a)도의 클럭펄스를 반전시킨펄스임)에 동기시시키게 되면 제2(b)도에 표시된 바와 같이 칼라신호(R)는 칼라신호(G)(B)에 비하여 정확히 한 클럭주기만큼 늦어져 출력되게 되므로 원하는 화질의 화면을 얻을 수 없는 것이다.However, when the primary color signal R ³ is delayed and output, the same clock pulse as in FIG.

; This is synchronized with the clock pulse of FIG. 2 (a). As shown in FIG. 2 (b), the color signal R is exactly one clock cycle compared to the color signal G and B. As shown in FIG. As it is delayed as much as the output, the screen of the desired quality cannot be obtained.

Therefore, in the present invention, when the color signal is delayed and outputted, it is detected by the asynchronous detector 10 and inverted and outputted by the clock pulse of the clock inverting unit 15 so that the color signal is not delayed by one clock period.

That is, the oscillator detection unit 10 of the present invention detects a misaligned state signal and inverts the output of the T-flip flop FF ₇ to output the inverted clock pulse CP at the clock inversion unit 15 to generate an RS-flip. By driving the flop (FF ₁ ) (FF ₂ ) (FF ₃ ), the negative edge of the clock pulse (CP) is converted to the positive edge and synchronized so that the color signal is delayed by one clock cycle to prevent a malfunction. will be.

As described above, when the primary color signal R ³ is delayed and applied, the color signal R output from the RS-flip flop FF ₁ is delayed by one clock period as shown in FIG. 2 (b). To this end, the clock pulse CP applied from the clock inverting unit 15 to the synchronization generating unit 5 should be inverted. To this end, the oscillator detecting unit 10 detects a misalignment of the color signal R and thereby causes the clock pulse. It is to reverse (CP).

Looking at the detection process of the paulownia detection unit 10 as described above.

First, when the primary color signal R ¹ is input past the point F, which is the positive edge of the clock pulse CP, as shown in FIG. 2 (a), the color signal R is colored as shown in FIG. 2 (b). When the output signal is delayed by one clock period as compared with the signal G and B, the color signals R and G as shown in FIG. 2 (b) are the exclusive oragate EX ₁ ( EX ₂ ).

로 도시)하게 되어 익스크루시브 오아게이트(EX₁)에서는

+G, 익스크루시브 오아게이트(EX₂)에서는

+신호를 출력시키게 되며 이러한 익스크루시브 오아게이트(EX₁)(EX₂)의 출력

은 오아게이트(OR₂)를 통한후

신호로 출력되게 된다.Exclusive ogate (EX ₁ ) (EX ₂ ), which outputs a high-level status signal only when the input levels are different, combines the color signals (R) (G) (B) (see

Exclusive Oagate (EX ₁ )

+ G, in Exclusive Oagate (EX ₂ )

It will output a + signal and the output of this exclusive oragate (EX ₁ ) (EX ₂ )

Through the Oagate (OR ₂ )

It is output as a signal.

의 상태는 제2(b)도에 도시된 바와 같으며 이러한 신호는 오아게이트(OR₂)를 통한후 제2(b)도에서와 같이

신호를 출력되게 된다.At this time, the exclusive oragate EX ₁ (EX ₂ ) outputs a high level status signal only when the input levels of the color signals R, G, and B applied as shown in FIG. 2 (b) are different. So that

The state of is as shown in Fig. 2 (b) and this signal is passed through the oragate OR ₂ and then as

The signal will be output.

의 펄스를 출력시키며 이때 오동기 현상은

펄스의 P₀(빗금친 부분)으로 나타나게 되며 이같은 빗금친 펄스(P₀)를 이용하여 클럭반전부(15)의 클럭펄스를 반전시키게 된다.The second (b) through the exclusive oragate EX ₁ (EX ₂ ) and the oragate OR ₂ in order to detect a misalignment of the color signals R, G, and B that are mistransmitted and output as described above. As in

Outputs a pulse of

It appears as P ₀ (hatched portion) of the pulse and inverts the clock pulse of the clock inverting unit 15 by using the hatched pulse P ₀ .

의 펄스가 발생되면 이를 콘덴서(C₁)와 저항(R₁)으로 구성된 미분회로(6)에 인가심킴으로써 제2(b)도의 β₁에서와 같은 미분펄스를 얻게된다.That is the gate to the output side of Iowa (OR _2), such as to help claim 2 (b)

When a pulse is generated, it is applied to the differential circuit 6 composed of the capacitor C ₁ and the resistor R ₁ to obtain a differential pulse as in β ₁ of FIG. 2 (b).

Since the positive pulse voltage of the differential pulse is charged to the capacitor C ₂ (C ₃ ) through the resistor R ₃ and the diode D ₁ , one side of the AND gate A ₃ to which the inverter I ₇ is connected. The terminal input is applied at a low level, but the charge charged in the capacitor C ₂ is discharged through the resistor R ₂ , so that the other terminal input of the AND gate A ₃ is high level during the time constant R ₂ × C ₂ . To be applied.

At this time, the time constant (R ₂ × C ₂ ) is determined as shown in the second (b).

When the negative pulse voltage of the gold ear β ₁ is applied, the voltage charged in the capacitor C ₃ is instantaneously discharged, so that the input of one terminal of the AND gate A ₃ to which the inverter I ₇ is connected is applied at a high level. Since the high level state is applied to the other terminal of the AND gate A ₃ by the time constant R ₂ × C ₂ , the output of the AND gate A ₃ is output at a high level, but the capacitor ( When C ₂ ) is discharged and the other terminal input of the AND gate A ₃ passes through the time constant R ₂ × C ₂ , the output of the AND gate A ₃ is output at a low level.

In other words, when a differential pulse as shown in β ₁ of FIG. 2 (b) is generated in the differential circuit 6, it is applied to the AND gate A ₃ through the charge / discharge circuit 7 and the inverter I ₇ . the output side of the a ₃₎ is the output pulse, such as a β ₂ degrees in claim 2 (b), so to be applied to the clock terminal (CK) of T- flip-flop (FF ₇₎ T- flip-flop (the output terminal of the FF ₇₎ In (Q), the clock inverting section 15 is applied with the same pulse as in β ₃ in FIG. 2 (b).

에서 빗금친 펄스(P₀)가 발생하게 되므로 앤드게이트(A₃)의 출력 (제2(b)도의 β₂)이 인가되는 T-플립플롭(FF₇)에서는 제2(b)도의 β₃)에서와 같이 하이레벨의 펄스를 펄스반전회로(15)에 인가시키게 되나 카랄신호의 오동기가 발생하지 않으면 상기와는 반대로

에서 빗금친 펄스(P₀)가 발생되지 않아 결국T-플립플롭(FF₇)에서는 펄스 반전회로(15)에 로우레벨의 펄스를 인가시키게 된다.As described above, when a malfunction occurs in the color signals R, G, and B, the second detection may be performed on the output side of the oragate OR ₂ of the misalignment detector 10.

Since the hatched pulse P ₀ occurs at the T-flip flop FF _{7 to} which the output of the AND gate A ₃ (β _{2 in} FIG. 2 (b)) is applied, β _{3 in} FIG. In this case, if a high level pulse is applied to the pulse inversion circuit 15, but there is no malfunction of the coral signal,

Since the hatched pulse P ₀ is not generated in the T-flip flop FF ₇ , a low level pulse is applied to the pulse inversion circuit 15.

As described above, the β ₃ pulses of FIG. 2 applied to the clock inverting unit 15 are applied at different logic levels depending on whether or not a color signal misalignment exists. The present invention uses the β ₃ pulses to control the clock pulse CP. The reverse oscillator generator is inverted and applied to the synchronization generator 5, and when the malfunctioner does not occur, it is applied to the synchronization generator 5 as it is.

That is ohdonggi in case there is a high level applied from ohdonggi detector 10, AND gates (A ₁₎ is blocked because the AND gate (A ₂₎ and Iowa gate (OR ₁₎ to the inverter (I ₅₎ by 180 ° phase reversal When the clock pulse (CP) is output, and when no malfunction is generated, the low level is applied by the misalignment detector (10), and the AND gate (A ₂ ) is blocked so that the clock pulse (CP) is output as it is.

Therefore, even when the primary color signal R 'is delayed as shown in FIG. 2 (a) by the inverted clock pulse generated by the misalignment, the color signal G ( It is possible to match the phase with B).

That is, the clock pulse of FIG. If the primary color signal R ³ is delayed and output as shown in FIG. 2 (a) when synchronizing the synchronization generating circuit 5 with (), the color signals R (G) and (B) become second (b). Since the color signal R is delayed for one cycle of the clock and outputted as shown in FIG. 5, the clock of the clock inverter 15 is converted into the clock pulse of FIG. By inverting the phase like CP) and applying it to the synchronization generating unit 5, the color signals R, G, and B are output as shown in FIG. 2A and positioned within one cycle of this clock. The phases of (R) (G) (B) are matched.

주기만큼 지연된 클럭펄스가 인가되는 D-플립플롭(FF₄-FF₆)을 접속시켜 준다.At this time, when the phase of the clock pulse is inverted in the synchronization detector 5, the RS-flip flop (FF ₁ -FF ₃ ) is used to stabilize the operation.

The D-flip flop (FF ₄ -FF ₆ ) to which the clock pulse delayed by the period is applied is connected.

In this way, the color image signal outputted with the same phase from the synchronization generator 5 can be displayed on the cathode ray tube (CRT) through the image signal amplifier 2 and the image signal output unit 3, thereby providing clear image quality. It is.

That is, according to the present invention, the clock pulse is developed to match the phase of the delayed color signal and the non-delayed color signal to match the phase of the color image signal. The monitor can improve the picture quality of the television screen by preventing the delay between the color signals due to the transmission delay time and having high resolution.

Claims (1)

The synchronization generator 5 is composed of an inverter I ₁ -I ₄ and a flip-flop FF ₁ -FF ₆ between the image signal input unit 1 and the image signal amplifier 2. after the color signal output is exclusive Iowa output of the gate (EX ₁₎ Iowa gate (OR ₂₎ applied through the (EX ₂₎ is via a differential circuit (6) and the charge-discharge circuit 7, an inverter (I ₇ ) is applied to the aND gate (a ₃₎ connected to configure the flip-flop (ohdonggi detector 10 to control the output of the FF ₇₎ and the output of the flip-flop (FF ₇₎ is an inverter (I ₅₎ (I ₆₎ and Configured to control the state signal of the clock pulse CP applied to the clock inverting unit 15 including the AND gate A ₁ (A ₂ ) and the ora gate OR ₁ and applied to the synchronization generating unit 5. Primary color synchronization generator.

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