KR890002557Y1 - Control circuit of voltage lebel - Google Patents

Control circuit of voltage lebel Download PDF

Info

Publication number
KR890002557Y1
KR890002557Y1 KR2019860011378U KR860011378U KR890002557Y1 KR 890002557 Y1 KR890002557 Y1 KR 890002557Y1 KR 2019860011378 U KR2019860011378 U KR 2019860011378U KR 860011378 U KR860011378 U KR 860011378U KR 890002557 Y1 KR890002557 Y1 KR 890002557Y1
Authority
KR
South Korea
Prior art keywords
voltage
output
operational amplifier
variable resistor
resistor
Prior art date
Application number
KR2019860011378U
Other languages
Korean (ko)
Other versions
KR880003511U (en
Inventor
이민기
Original Assignee
주식회사 금성사
구자학
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 금성사, 구자학 filed Critical 주식회사 금성사
Priority to KR2019860011378U priority Critical patent/KR890002557Y1/en
Publication of KR880003511U publication Critical patent/KR880003511U/en
Application granted granted Critical
Publication of KR890002557Y1 publication Critical patent/KR890002557Y1/en

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/461—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using an operational amplifier as final control device
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Amplifiers (AREA)

Abstract

내용 없음.No content.

Description

출력레벨 조절회로Output level control circuit

제1도는 종래의 회로도.1 is a conventional circuit diagram.

제2도는 본 고안에 따른 회로도.2 is a circuit diagram according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

R1-R9: 저항 C1: 콘덴서R 1 -R 9 : Resistor C 1 : Capacitor

TR1, TR2: 트랜지스터 OP2-OP7: 연산증폭기TR 1 , TR 2 : Transistor OP 2 -OP 7 : Operational Amplifier

VR4-VR6: 가변저항VR 4 -VR 6 : Variable Resistance

본 고안은 회로상의 출력레벨의 최대치와 최소치를 조절하는 출력레벨 조절회로에 관한 것으로, 특히 최대, 최소값을 조정할때 상호영향을 미치지 않고 단독 조정가능하게 한 출력레벨 조절회로에 관한 것이다.The present invention relates to an output level control circuit for adjusting the maximum and minimum values of the output level on the circuit, and more particularly to an output level control circuit that can be independently adjusted without mutual influence when adjusting the maximum and minimum values.

종래의 경우에는 각종 조정회로에 있어서 최대, 최소값을 조정할 때 상호간에 영향을 미치게 되어 최대값 조성시 최소값이 변하고 최소값 조정시 최대값이 변하여 여러차례의 최대, 최소값 조성을 거친 후 어느 정도 원하는 만큼의 레벨조절을 하게 되는 것이었다.In the conventional case, various adjustment circuits affect each other when adjusting the maximum and minimum values, and the minimum value is changed when the maximum value is formed, and the maximum value is changed when the minimum value is adjusted. It was to be.

제1도는 이와 같은 종래의 회로도로서, 이에 도시한 바와 같이 전원단자(Vcc)에 가변저항(VR1-VR3)을 직렬 접속하고, 그의 중간가변저항(VR2)의 가변단자는 연산증폭기(OP1)의 비반전입력단자(+)에 접속한 것으로, 최대, 최소값을 조정할 때 가변저항(VR1)(VR3)을 각기 조정하여 최대, 최소값을 조정하게 되는 바, 최대값을 조정하기 위해 가변저항(VR1)을 조정하여 최대값을 맞추고, 최소값을 조정하기 위해 가변저항(VR3)을 조정하면 이 가변저항(VR3)의 저항값 변화에 따라 최대값(Vmax)이 변하게 되며, 최대값(Vmax)을 재조정해주기 위해 가변저항(VR1)을 변화시키면 이 저항값(VR1)의 변화로 최소값(Vmin)이 변하게 되어 결국 여러차례 가변저항(VR1)(VR3)을 번갈아 조정해야만 어느 일정한 출력레벨을 맞출 수 있게되나, 조정하는데 많은 시간이 소요될 뿐만 아니라 정확한 조정을 할 수 없어 많은 오차를 갖는 출력레벨을 출력시키게 되는 단점이 있었다.FIG. 1 is a circuit diagram of the related art, and as shown therein, the variable resistors VR 1 to VR 3 are connected in series to the power supply terminals Vcc, and the variable terminals of the intermediate variable resistors VR 2 are connected to operational amplifiers. OP 1 ) is connected to the non-inverting input terminal (+), and when adjusting the maximum and minimum values, the variable resistors VR 1 and VR 3 are adjusted to adjust the maximum and minimum values. Adjust the variable resistor VR 1 to adjust the maximum value, and adjust the variable resistor VR 3 to adjust the minimum value. The maximum value Vmax changes according to the resistance value of the variable resistor VR 3 . If the variable resistance VR 1 is changed to readjust the maximum value Vmax, the minimum value Vmin is changed by the change of the resistance value VR 1 , and the variable resistance VR 1 and VR 3 are alternately changed several times. Only a certain output level can be adjusted to adjust, but it takes a lot of time to adjust. As it can not be an exact adjustment had the disadvantage that the output level output thereby has a lot of errors.

본 고안은 이와 같은 종래의 단점을 감안하여, 최대, 최소값의 조정시 상호 영향을 미치게 하는 것 없이 단독 조정가능하게 함은 물론 최대, 최소값의 레벨을 표시하는 전압을 동시에 얻을 수 있도록 안출한 것으로, 첨부한 제2도에 의해 이를 상세히 설명하면 다음과 같다.The present invention has been made in view of the above-mentioned drawbacks, so that it is possible to obtain a voltage indicating the level of the maximum and minimum values as well as to be independently adjustable without affecting each other when adjusting the maximum and minimum values. Referring to this in detail with the accompanying Figure 2 as follows.

첨부한 제2도는 본 고안에 따른 회로도로서, 이에 도시한 바와 같이 비반전 입력단자 (+)(+)가 저항(R1, R2)(R2, R3)의 각 접속점에 각기 접속된 연산증폭기(OP2)(OP3)의 출력측은 콘덴서(C1) 및 가변저항(VR1)을 병렬로 통해 상호 접속되게 하고, 상기 연산증폭기(OP1)의 출력측은 저항(R4)(R5)을 각기 통해 트랜지스터(TR1)(TR2)의 에미터에 접속하며, 상기 가변저항(VR4)의 가변단자는 반전입력단자(-)가 상기 트랜지스터(TR1)의 에미터에 접속된 연산증폭기(OP4)의 비반전입력단자(+)에 접속하여 그의 출력측은 상기 트랜지스터(TR1)(TR2)의 베이스에 공통접속하고, 그의 콜렉터는 연산증폭기(OP6)(OP7)를 통해 출력 전압측 및 전시전압측에 접속하며, 저항(R8)을 통해 전압단자(Vcc)에 접속된 가변저항(VR5) 및 저항(R9)의 접속점에 비반전입력단자(+)가 접속된 연산증폭기(OP5)의 출력측은 저항(R6) 및 가변저항(VR6)을 통해 상기 트랜지스터(TR1)의 콜렉터에 접속한 것으로, 이와 같이 구성한 본 고안의 작용 및 효과를 상세히 설명하면 다음과 같다.2 is a circuit diagram according to the present invention, in which a non-inverting input terminal (+) (+) is connected to each connection point of the resistors R 1 , R 2 , R 2 , and R 3 , respectively. The output side of the operational amplifier OP 2 and OP 3 allows the capacitor C 1 and the variable resistor VR 1 to be interconnected in parallel, and the output side of the operational amplifier OP 1 is connected to the resistor R 4 ( R 5 ) is connected to the emitter of the transistor TR 1 (TR 2 ), respectively, and the variable terminal of the variable resistor VR 4 has an inverting input terminal (−) connected to the emitter of the transistor TR 1 . It is connected to the non-inverting input terminal (+) of the connected operational amplifier OP 4 and its output side is commonly connected to the base of the transistor TR 1 (TR 2 ), and its collector is connected to the operational amplifier OP 6 (OP). 7 ) is connected to the output voltage side and the display voltage side, and the non-inverting input terminal () at the connection point of the variable resistor VR 5 and the resistor R 9 connected to the voltage terminal Vcc through the resistor R 8 . +) The output side of a connected operational amplifier (OP 5) has a resistance (R 6), and that through the variable resistor (VR 6) connected to the collector of said transistor (TR 1), describe the action and effect of the present design is configured as described above in detail Is as follows.

전원단자(Vcc)에 전원을 인가하게 되면, 그에 직렬 접속된 저항(R1-R3)에 의해 분할된 전원(Vref1)(Vref2)이 연산증폭기(OP2)(OP3)의 비반전입력단자(+)(+)에 입력 되어 그의 출력측에는 일정전압(V3)(V4)이 각기 출력된다. 이때 콘덴서(C1)는 상기 전압(V3)(V4)에 의해 충전되어 전압을 안정시키게 된다.When the power is applied to the power supply terminal Vcc, the power supply Vref 1 (Vref 2 ) divided by the resistors R 1 -R 3 connected in series is divided by the ratio of the operational amplifier OP 2 (OP 3 ). It is input to the inverting input terminal (+) (+) and a constant voltage (V 3 ) (V 4 ) is output to the output side thereof, respectively. In this case, the capacitor C 1 is charged by the voltage V 3 and V 4 to stabilize the voltage.

가변저항(VR4)은 사용자가 외부에서 조절함으로써 출력레벨을 조정하는 것이다. 즉, 가변저항(VR4)을 A측으로 조절하여 그의 값을 작게하면 최소출력을 얻을 수 있고, 가변저항(VR4)을 B측으로 조절하여 그의 값을 크게하면 최대출력을 얻을 수 있게 되는바, 최대출력과 최소출력의 범위를 확대하기 위해서는 상기 연산증폭기(OP2)(OP3)의 출력전압(V3)(V4)의 차이를 크게하면 된다.The variable resistor VR 4 adjusts the output level by the user externally adjusting. That is, the minimum output can be obtained by adjusting the variable resistor VR 4 to the A side to reduce the value thereof, and the maximum output can be obtained by adjusting the variable resistor VR 4 to the B side to increase the value thereof. In order to extend the range between the maximum output and the minimum output, the difference between the output voltages V 3 and V 4 of the operational amplifiers OP 2 and OP 3 may be increased.

이와 같이하여 사용자가 가변저항(VR4)의 저항값을 조정함에 따라 그의 가변단자로부터 연상증폭기(OP4)의 비반전입력단자(+)에 인가되는 전압(V5)은 전압(V3)에서부터 전압(V4)까지 선형적 가변이 된다.In this way, as the user adjusts the resistance value of the variable resistor VR 4 , the voltage V 5 applied from the variable terminal to the non-inverting input terminal (+) of the associative amplifier OP 4 is equal to the voltage V 3 . Linearly from to the voltage V 4 .

한편, 트랜지스터(TR1)의 콜렉터전압(V6)은 연산증폭기(OP4)가 전압플로워(Voltage Follower)로 구성되어 있으므로 그 연산증폭기(OP4)의 입력전압(V5)과 거의 같게 된다. [실시로는 V6=V5-VEB(≒0.7V)].On the other hand, the collector voltage (V 6) of the transistor (TR 1) is an operational amplifier (OP 4) a voltage-follower (Voltage Follower) it consists of is almost the same as the op amp input voltage (V 5) of the (OP 4) equal to . [V 6 = V 5 -V EB (≒ 0.7V) in the embodiment].

이에따라 트랜지스터(TR1)(TR2)의 콜렉터전류(I1)(I2)는 각기 다음과 같이 산출될 수 있게 된다.Accordingly, the collector currents I 1 and I 2 of the transistors TR 1 and TR 2 can be respectively calculated as follows.

이때 저항(R4)(R5)의 값을 동일하게 설정하여 상기 전류(I1)(I2)의 값이 동일하게 한다.In this case, the values of the resistors R 4 and R 5 are set to be the same so that the values of the currents I 1 and I 2 are the same.

이때 상기한 바와 같이 가변저항(VR4)의 값을 변화시켜 전압(V3)(V5)이 서로 같게하면 상기 식(1)(2)에서 보는 바와 같이 전류(I1)(I2)는 제로가 된다.At this time, if the voltage (V 3 ) (V 5 ) is equal to each other by changing the value of the variable resistor (VR 4 ) as described above, the current (I 1 ) (I 2 ) as shown in equation (1) ( 2 ) Becomes zero.

이와 같은 상태에서 연산증폭기(OP5)의 비반전입력단자(+)에 접속된 가변저항(VR5)의 값을 조정하여 그 연산증폭기(OP5)의 출력전압(V8)이 최소치가 되게 하면 이 출력 최소전압은 저항(R6), 가변저항(VR6) 및 연산증폭기(OP6)를 통해 출력된다.The output voltage (V 8) of adjusting the value of the variable resistor (VR 5) and the operational amplifier (OP 5) connected in such state to the non-inverting input terminal (+) of the operational amplifier (OP 5) is to be the minimum value This output minimum voltage is then output via resistor R 6 , variable resistor VR 6 , and operational amplifier OP 6 .

또한, 상기 가변저항(VR4)의 값을 변화시켜 전압(V5)이 전압(V4)과 같게 하면 상기 식(1)(2)에 의해 전류(I1)(I2)는 최대값이 되게 된다.In addition, when the value of the variable resistor VR 4 is changed to make the voltage V 5 equal to the voltage V 4 , the current I 1 (I 2 ) is the maximum value according to the above formula (1) (2). Will be

이때, 가변저항(VR6)을 조정하여 출력조절전압이 최대치가 되도록 조정하면 그 최대출력 조절전압은 V8+I1(VR6+R6)=V8 (VR6+R6)가 된다.At this time, if you adjust the variable resistance (VR 6 ) so that the output control voltage is the maximum value, the maximum output control voltage is V 8 + I 1 (VR 6 + R 6 ) = V 8 (VR 6 + R 6 ).

한편, 상기 식(1)(2)에서 보면 전류(I1)(I2)는 전압(V3) 및 저항(R4)(R5)의 값이 각기 고정된 상태이므로 전압(V5)의 값에 의해서만 변화하게 되고, 상기 가변저항(VR5)(VR6) 및 저항(R6)의 값에 대해서는 변화하지 않게 된다.On the other hand, since the formula (1) (2) When the current (I 1) (I 2) is the state value of the voltage (V 3) and a resistor (R 4) (R 5) of each fixed at a voltage (V 5) It is changed only by the value of, and does not change with respect to the values of the variable resistors VR 5 (VR 6 ) and the resistor R 6 .

이와 같이하여 상기 전류(I1)(I2)를 제로로한 상태에서 최소출력전압(V8)을 조정하므로 가변저항(VR6)과는 무관하게 되고, 전류(I1)(I2)는 가변저항(VR6)에 무관하므로 가변저항(VR6)의 값을 변화시켜도 전류(I1)(I2)에는 변화가 없게 되며, 최소출력전압을 결정하는 연산증폭기(OP5)의 비반전입력단자(+)의 전압(V9)은 저항(R8), 가변저항(VR5) 및 저항(R9)에 의한 분배전압이므로 가변저항(VR6)은 출력최소전압에 아무 영향을 미치지 않은 상태에서 최대출력전압을 조절하게 된다.In this way, since the minimum output voltage V 8 is adjusted in the state where the current I 1 (I 2 ) is zero, it is independent of the variable resistor VR 6 and the current I 1 (I 2 ). Since is independent of the variable resistor VR 6 , there is no change in the current I 1 (I 2 ) even if the value of the variable resistor VR 6 is changed, and the ratio of the operational amplifier OP 5 that determines the minimum output voltage is determined. Since the voltage V 9 of the inverting input terminal (+) is divided by the resistor R 8 , the variable resistor VR 5 and the resistor R 9 , the variable resistor VR 6 has no influence on the output minimum voltage. The maximum output voltage is adjusted without reaching.

또한 출력조절전압에 따라 출력레벨을 표시하기 위한 전시전압을 동시에 얻을 수 있는 바 저항(R4)(R5)의 값을 상호 동일한 값으로 하였을 때 전류(I1)(I2)가 상호 같은 값이 되므로 트랜지스터(TR2)의 콜렉터에 접속된 저항(R7)에는 일정전압(V7)이 검출되고, 이 전압을 연산증폭기(OP7)를 통해 출력하면 오차없이 출력조절전압에 상응하는 전시전압을 얻게 된다.In addition, the display voltage for displaying the output level can be obtained simultaneously according to the output control voltage. When the values of the resistors R 4 and R 5 are the same, the currents I 1 and I 2 are the same. As a value, a constant voltage V 7 is detected in the resistor R 7 connected to the collector of the transistor TR 2 , and when this voltage is output through the operational amplifier OP 7 , it corresponds to the output regulation voltage without error. The display voltage is obtained.

이상에서 설명한 바와 같이 본 고안은 출력레벨 조정시 최대출력전압 및 최소출력전압을 결정하는 가변저항(VR5)(VR6)을 상호 독립적으로 조정할 수 있게 함으로써 정확한 출력레벨을 조절할 수 있는 효과가 있게 된다.As described above, the present invention makes it possible to independently adjust the variable resistors VR 5 and VR 6 that determine the maximum output voltage and the minimum output voltage at the time of adjusting the output level. do.

Claims (1)

기준전압(Vref1)(Vref2)이 비반전입력단자에 인가되는 연산증폭기(OP2)(OP3)출력측은 콘덴서(C1) 및 가변저항(VR4)을 병렬로 통해 접속하고, 상기 연산증폭기(OP2)의 출력측은 저항(R4)(R5)을 각기 통해 트랜지스터(TR1)(TR2)의 에미터에 각각 접속하며, 상기 가변저항(VR4)의 가변단자는 반전입력단자가 트랜지스터(TR1)의 에미터에 접속된 연산증폭기(OP4)의 비반전입력단자에 접속하여 그의 출력측은 상기 트랜지스터(TR1)(TR2)의 베이스에 접속하고, 그의 콜렉터는 연산증폭기(OP6)(OP7)를 통해 출력전압측 및 전시전압측에 각기 접속하며 가변저항(VR5)을 통해 일정기준전압(V9)을 비반전입력단자에 인가받는 연산증폭기(OP5)의 출력측은 저항(R6),가변저항(VR6)을 통해 상기 트랜지스터(TR1)의 콜렉터에 접속하여 구성함을 특징으로 하는 출력레벨 조절회로.The operational amplifier OP 2 (OP 3 ) output side to which the reference voltage Vref 1 (Vref 2 ) is applied to the non-inverting input terminal is connected to the capacitor C 1 and the variable resistor VR 4 in parallel, and The output side of the operational amplifier OP 2 is connected to the emitters of the transistors TR 1 and TR 2 through the resistors R 4 and R 5 , respectively, and the variable terminals of the variable resistor VR 4 are inverted. input terminal is connected to the non-inverting input terminal of the operational amplifier (OP 4) connected to the emitter of the transistor (TR 1) its output side is connected to the base of said transistor (TR 1) (TR 2), and its collector is The operational amplifier (OP 6 ), which is connected to the output voltage side and the display voltage side through the operational amplifier OP 6 and OP 7 , and receives a constant reference voltage V 9 to the non-inverting input terminal through the variable resistor VR 5 . The output side of 5 ) is configured to be connected to the collector of the transistor TR 1 via a resistor R 6 and a variable resistor VR 6 . Level control circuit.
KR2019860011378U 1986-07-30 1986-07-30 Control circuit of voltage lebel KR890002557Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019860011378U KR890002557Y1 (en) 1986-07-30 1986-07-30 Control circuit of voltage lebel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019860011378U KR890002557Y1 (en) 1986-07-30 1986-07-30 Control circuit of voltage lebel

Publications (2)

Publication Number Publication Date
KR880003511U KR880003511U (en) 1988-04-13
KR890002557Y1 true KR890002557Y1 (en) 1989-04-29

Family

ID=19254410

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019860011378U KR890002557Y1 (en) 1986-07-30 1986-07-30 Control circuit of voltage lebel

Country Status (1)

Country Link
KR (1) KR890002557Y1 (en)

Also Published As

Publication number Publication date
KR880003511U (en) 1988-04-13

Similar Documents

Publication Publication Date Title
JP2556710B2 (en) Variable current source
JPH0544845B2 (en)
KR890002557Y1 (en) Control circuit of voltage lebel
JP3067010B2 (en) Absolute humidity sensor
US4370608A (en) Integrable conversion circuit for converting input voltage to output current or voltage
US4039980A (en) Voltage-controlled filter
KR100209473B1 (en) Wide band amplifier
KR930001218Y1 (en) Input stabilized circuit of analog and digital converter
SU866550A1 (en) Parallel-type dc voltage stabilizer
JPH0619208Y2 (en) Variable gain circuit
KR900000712Y1 (en) Brightness control circuit for monitor
SU1026124A1 (en) Variable signal stabilizer
SU1723462A1 (en) Converter of non-electric values to electric signal
JPH087465Y2 (en) Highly stable constant current power supply
JPH0321082Y2 (en)
KR200211734Y1 (en) Variable voltage distribution circuit
SU1401559A1 (en) Broad-band current amplifier
SU1374202A1 (en) D.c. voltage stabilizer
SU726511A1 (en) Current source
SU1053085A1 (en) D.c. voltage and direct current stabilizer
SU800973A1 (en) Dc voltage stabilizer
KR940003081Y1 (en) Diff amplifier
KR100355381B1 (en) Current-controlled power amplifier
JP2911977B2 (en) Oscillation circuit
JPS5842941Y2 (en) Amplifier for PH meter

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 19941227

Year of fee payment: 7

LAPS Lapse due to unpaid annual fee