KR890001340Y1 - Double scan device for television set - Google Patents
Double scan device for television set Download PDFInfo
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- KR890001340Y1 KR890001340Y1 KR2019850013375U KR850013375U KR890001340Y1 KR 890001340 Y1 KR890001340 Y1 KR 890001340Y1 KR 2019850013375 U KR2019850013375 U KR 2019850013375U KR 850013375 U KR850013375 U KR 850013375U KR 890001340 Y1 KR890001340 Y1 KR 890001340Y1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
- H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1737—Controllable logic circuits using multiplexers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/38—Starting, stopping or resetting the counter
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/06—Generation of synchronising signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/284—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator monostable
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Abstract
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Description
제1도는 종래의 회로도.1 is a conventional circuit diagram.
제2도는 본 고안의 회로도.2 is a circuit diagram of the present invention.
제3도 (a)는 본 고안의 주파수 체배회로의 상세회로도, (b)는 본 고안의 리세트 회로의 상세회로도, (c)는 본 고안의 단안정 멀티바이브레타의 상세회로도.3 is a detailed circuit diagram of a frequency multiplier circuit of the present invention, (b) is a detailed circuit diagram of a reset circuit of the present invention, and (c) is a detailed circuit diagram of a monostable multivibrator of the present invention.
제4도는 제2도 회로 각 부분의 신호파형도.4 is a signal waveform diagram of each part of the circuit of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 주파수 체배회로 2, 8 : 멀티플렉서1: Frequency multiplication circuit 2, 8: Multiplexer
3 : 리세트 회로 4, 5 : N분할 카운터3: reset circuit 4, 5: N division counter
6, 7 : NAND게이트 9 : 수평동기신호 발생회로6, 7: NAND gate 9: horizontal synchronous signal generating circuit
본 고안은 흑백텔레비젼용 2배주사장치에 관한 것으로서, 특히 2배주사변환기(Double Scan Convertor)내의 메모리 어드레스 지정은 표본화신호(fs)의 N분할 카운터의 클럭입력을 매수평주기마다 서로 바꿔서 2개의 어드레스 신호군을 스위칭토록 하므로서 N분할카운터 출력에 연결되는 멀티플렉서를 삭제할 수 있도록 한 텔레비젼수상기용 2배주사장치의 구성에 관한 것이다.The present invention relates to a double scan device for black and white televisions. In particular, the memory addressing in the double scan convertor is performed by changing the clock inputs of the N division counters of the sampling signal (fs) at every horizontal period. The present invention relates to a configuration of a double-scanning apparatus for a television receiver which allows the multiplexer connected to the N-division counter output to be switched by causing the address signal group to be switched.
종래의 흑백텔레비젼 수상기용 2배주사장치의 2배주사변환기는 제1도에 도시된 바와 같이 멀티플렉서(마) 및 멀티플렉서(바)의 출력단자(Q)에 각각 나타난 어드레스신호(Ad1)와 어드레스신호(Ad2)는 각각 두개의 라인메모리에 입력되며 이 두 어드레스신호는 입력영상신호의 수평주기가 바뀔때마다 서로 바뀌어지도록 되어 있다.The double scan converter of the conventional double scan device for monochrome television receivers has an address signal (Ad1) and an address signal shown on the output terminal (Q) of the multiplexer (e) and the multiplexer (bar), respectively, as shown in FIG. (Ad2) is input to two line memories, respectively, and these two address signals are interchanged each time the horizontal period of the input video signal changes.
즉, 임의의 수평주기동안 어드레스신호(Ad1)가 표본화신호(fs)의 주파수로 카운트하는 N분할카운터(다)의 출력으로 표현된다면 어드레스신호(Ad2)는 주파수 체배회로 (가)에서 체배된 표본화신호(zfs)로 카운트하는 N분할카운터(라)의 출력으로 표현되는 것이다.That is, if the address signal Ad1 is represented by the output of the N division counter C that counts at the frequency of the sampling signal fs during any horizontal period, the address signal Ad2 is multiplied by the frequency multiplying circuit a. It is represented by the output of the N division counter d which counts with the sampling signal zfs.
한편 수평동기신호 발생회로 (사)에서는 체배된 수평동기신호를 출력하여 2배주사시의 모든 회로동작에 통일을 기하고 있다.On the other hand, the horizontal synchronizing signal generating circuit (G) outputs a multiplying horizontal synchronizing signal to uniformize all the circuit operations during double scanning.
또한 리세트회로(나)는 N분할카운터(다, 라)의 초기 리세트와 멀티플렉서(마, 바)의 제어단자(S)에 멀티플렉서(마, 바)의 선택신호를 공급한다.In addition, the reset circuit b supplies an initial reset of the N division counters d and d and a selection signal of the multiplexer e to the control terminal S of the multiplexer e and bar.
멀티플렉서(마, 바)의 선택신호는 입력영상신호의 수평주기(≒63.5μsec)마다 0과 1이 반복되는 신호로서 제4도의 (b)와 같은 형태이다. 그러나 이러한 종래의 어드레스신호(Ad1)와 어드레스신호(Ad2)를 매 수평주기마다 바꿔주기 위해 N분할카운터(다, 라)의 출력을 멀티플렉서(마, 바)로서 스위칭해주고 있으므로 만약 N분할카운터의 N값이 910일 경우 어드렛선은 10개선이 되며 이는 곧 많은 양의 멀티플렉서를 N분한카운터의 출력에 연결하여 사용해야 됨을 의미한다.The selection signal of the multiplexer (e.g., bar) is a signal in which 0 and 1 are repeated every horizontal period (주기 63.5 μsec) of the input video signal, as shown in FIG. However, in order to change the conventional address signal Ad1 and the address signal Ad2 every horizontal period, the output of the N division counter (C) is switched as a multiplexer (MA, bar). If the value is 910, then there are 10 address lines, which means that a large number of multiplexers should be connected to the output of N divided counters.
또한 N분할카운터의 N값은 입력영상신호의 표본화신호(fs) 주파수가 높아질수록 증가하며 따라서 카운터출력의 멀티플렉서도 더욱 많이 필요해지게 되는 것이다.In addition, the N value of the N-division counter increases as the sampling signal (fs) frequency of the input video signal increases, thus requiring more counter multiplexers.
그러므로 종래의 장치는 부품수의 증가로 인한 제조원가의 상승과 조립의 어려움 및 소형 경량화할 수 없게 되는 단점이 있는 것이다.Therefore, the conventional apparatus has a disadvantage in that the manufacturing cost is increased due to the increase in the number of parts, the difficulty of assembly, and the size and weight can not be reduced.
본 고안은 이와 같은 단점을 없이하도록 N분할카운터 출력측의 멀티플렉서를 삭제하므로서 소요부품수를 줄여서 구성을 간단히 하고 제조원가를 절감하며 조립작업능률을 높일 수 있도록 한 것이다.The present invention eliminates the multiplexer on the N-segment counter output side to eliminate such drawbacks, thereby reducing the number of parts required, simplifying configuration, reducing manufacturing costs, and increasing assembly efficiency.
본 고안 장치의 구성은 제2도에 도시된 바와 같이, 멀티플렉서(2)의 입력단자(Io)에는 표본화신호(fs)를 입력하고 입력단자(I1)에는 주파수 체배회로(1)를 통해 체배된 표본화 신호(2fs)를 입력하며, 출력단자(Co)는 N분할카운터(4)의 클럭단자(cko)에, 출력단자(C1)는 N분할카운터(5)의 클럭단자(CK1)에 각각 연결하되 N분할카운터(4, 5)의 출력단자(Q1, Q2)는 각각 NAND게이트(6, 7)를 통해 멀티플렉서(8)의 입력단자(F0, F1)에 각각 연결하며, 멀티플렉서(8)의 출력단자(G0)는 수평동기신호 발생회로(9)의 입력단자(H0)에 연결하여 그 출력단자(L0)에서는 2배 주사변환된 영상신호에 맞는 수평동기신호(H/S)를 출력토록 하고, 리세트회로(3)의 출력단자(E0)는 N분할카운터(4, 5)의 리세트 단자()에, 출력단자(E1)는 멀티플렉서(2, 8)의 제어단자(S1, S2)에 각각 연결하여서 된 것이다.As shown in FIG. 2, the device of the present invention is configured to input a sampling signal fs to an input terminal Io of the multiplexer 2 and a frequency multiplication circuit 1 to the input terminal I 1 . The multiplied sampling signal 2fs is input, the output terminal Co is connected to the clock terminal cko of the N division counter 4, and the output terminal C 1 is the clock terminal CK 1 of the N division counter 5. ), But output terminals (Q 1 , Q 2 ) of N division counters (4, 5) are respectively connected to input terminals (F 0 , F 1 ) of multiplexer (8) through NAND gates (6, 7), respectively. The output terminal (G 0 ) of the multiplexer 8 is connected to the input terminal (H 0 ) of the horizontal synchronous signal generation circuit (9), and at the output terminal (L 0 ), the output signal (L 0 ) is matched to the video signal converted twice. The horizontal synchronization signal (H / S) is output, and the output terminal (E 0 ) of the reset circuit (3) is connected to the reset terminal ( ), The output terminal E 1 is connected to the control terminals S 1 and S 2 of the multiplexers 2 and 8, respectively.
또한 제3도에는 본 고안에 의한 주파수 체배회로(1)와 리세트 회로(3) 및 수평동기신호 발생회로(9)의 상세회로가 도시되어 있다. 즉, 주파수 체배회로(1)는 제3도 (a)에 도시된 바와 같이, 표본화신호(fs)를 인버터(101)를 통해 시정수회로 (102)에 입력시킴과 동시에 OR게이트(103)와 NAND게이트(104)의 일측에 각각 입력시켜서 시정수회로(102)와 OR게이트(103) 및 NAND게이트(104, 105)의 공지된 논리작용에 의해 출력단자(B0)에서는 2배로 체배된 표본화신호(2fs)를 출력한다.3 shows a detailed circuit of the frequency multiplication circuit 1, the reset circuit 3, and the horizontal synchronous signal generating circuit 9 according to the present invention. That is, the frequency multiplication circuit 1 inputs the sampling signal fs to the time constant circuit 102 via the inverter 101 as shown in FIG. And multiplied by two times at the output terminal B 0 by a known logic action of the time constant circuit 102, the OR gate 103, and the NAND gates 104, 105 by inputting to one side of the NAND gate 104, respectively. Output a sampling signal (2fs).
그리고 리세트회로(3)는 제3도 (b)에 도시된 바와 같이 수평동기신호(H/S)를 단안정 멀티바이브레타(301)의 입력단자(M0)에 입력시키고, 수직동기신호(V/S)를 OR게이트(303)를 통해 단안정 멀티바이브레타(302)의 입력단자(M1)에 입력시킴과 동시에 D플립플롭(306)의 클럭단자(CLK)에 입력시켜서 단안정 멀티바이브레타(301, 302, 304)와 OR게이트(305)의 공지된 논리작용에 의해 출력단자(E0)에서 N분할카운터(4, 5)의 리세트신호를 출력하고, 단자(E1)에서 멀티플렉서(2, 8)의 제어신호를 출력하게 된다.The reset circuit 3 inputs the horizontal synchronous signal H / S to the input terminal M 0 of the monostable multivibrator 301 as shown in FIG. (V / S) is inputted to the input terminal M 1 of the monostable multivibrator 302 through the OR gate 303, and is also input to the clock terminal CLK of the D flip-flop 306 to be monostable. By the known logic of the multivibrators 301, 302, 304 and the OR gate 305, the reset signal of the N division counters 4, 5 is output from the output terminal E 0 , and the terminal E 1 is output. ) Outputs the control signals of the multiplexers 2 and 8.
또한 수평동기신호 발생회로(9)는 제3도 (c)에 도시된 바와 같이 2개의 단안정 멀티바이브레타(901, 902)와 OR게이트(903)의 공지된 논리작용에 의해 2배 주사변환된 영상신호에 맞는 새로운 수평동기신호(H/S)'를 단자(L0)에서 출력한다.In addition, the horizontal synchronizing signal generation circuit 9 performs double scan conversion by the known logic of the two monostable multivibrators 901 and 902 and the OR gate 903 as shown in FIG. A new horizontal synchronization signal (H / S) 'corresponding to the received video signal is output from the terminal (L 0 ).
상기와 같은 장치를 포함하여 본 고안의 작용효과를 상세히 설명하면 다음과 같다.Referring to the effect of the present invention including the device as described above in detail.
제2도의 주파수 체배회로(1)에 가해지는 클럭신호는 제4도의 (a)에 나타낸 영상신호의 표본화신호와 같은 것이며, 이 신호의 주파수를 fs라고 할때, fs=N·fM의 관계식이 만족되는 정수N이 존재하는 것으로 가정한다.(여기서 fn는 수평동기 주파수로서 약 15.75KHZ이다) 즉, 위 관계식이 만족될때 두배주사 변환기에 사용되는 메모리의 용량은 한 주사선당 N byte가 되어야 하며 어드레스 라인의 수는 log2N보다 같거나 큰 정수만큼 된다.The clock signal applied to the frequency multiplying circuit 1 of FIG. 2 is the same as the sampling signal of the video signal shown in FIG. 4A, and when the frequency of this signal is fs, fs = N · f M. Assume that there is an integer N where the relation is satisfied (where fn is the horizontal synchronous frequency of about 15.75 KHZ). That is, the capacity of the memory used for the double scan transducer when the relation is satisfied must be N bytes per scan line. The number of address lines is an integer greater than or equal to log 2 N.
한편, 주파수 체배회로(1) 출력단자(B0)에는 2fs의 주파수 신호가 나타나며 표본화신호인 클럭입력신호(fs)와 함께 멀티플렉서(2)의 입력단자(I0, I1)에 각각 가해진다. 멀티플렉서(2)의 제어단자(S1) 입력신호는 리세트회로(3)에서 발생되며 제4도의 (b)와 같은 형태의 신호이다. 따라서 멀티플렉서(2)의 출력단자(C0, C1)에는 이 제어단자(S1) 입력신호에 따라 클럭주파수가 fs인 것과 2fs인 것이 번갈아가며 출력되며 제4도의 (c)와 (d)는 이것을 나타내고 있는 것이다.On the other hand, a frequency signal of 2 fs appears at the output terminal B 0 of the frequency multiplier circuit 1 and is applied to the input terminals I 0 , I 1 of the multiplexer 2 together with the clock input signal fs, which is a sampling signal. All. The input signal of the control terminal S 1 of the multiplexer 2 is generated by the reset circuit 3 and is a signal of the type shown in FIG. Therefore, the output terminals C 0 and C 1 of the multiplexer 2 are alternately outputted with a clock frequency of fs and 2fs according to the input signal of this control terminal S 1 , and (c) and (d) of FIG. Indicates this.
이와 같은 클럭신호를 받는 N분할카운터(4, 5)는 각각 제4도의 (f)와 (f)에 나타낸 것과 같이 카운트하며 따라서 각각의 출력단자(Q1, Q2)에 수평주기(약 63,5μs)마다 카운트 속도가 번갈아가며 바뀌어지는 신호를 출력시키는 것이다.N-split counters 4 and 5 that receive this clock signal count as shown in (f) and (f) of FIG. 4, respectively, and thus have horizontal periods (approximately 63) at the respective output terminals Q 1 and Q 2 . , 5μs) outputs a signal that alternates between count rates.
한편, 두배로 주파수가 증가한 수평동기신호(H/S)'는 약 주파수가 31.5 KHZ가 되며 두개의 N분할카운터(4, 5)의 출력이 어드레스신호(Ad1) 및 어드레스신호 (Ad2)를 디코딩하여 사용하고 있다. 즉, 어드레스신호(Ad1)나 어드레스신호(Ad2)의 비트중, 적당한 몇 개의 신호로 NAND게이트(6) 및 NAND게이트(7)를 통과시켜 제4도의 (g)와 (h)의 파형을 갖는 신호를 만들 수 있는 것이다.On the other hand, the horizontal synchronization signal (H / S) having twice the frequency is approximately 31.5 KHZ, and the outputs of the two N division counters 4 and 5 decode the address signal Ad1 and the address signal Ad2. I use it. In other words, among the bits of the address signal Ad1 or the address signal Ad2, the NAND gate 6 and the NAND gate 7 are passed through the NAND gate 6 and the NAND gate 7 with some suitable signals to have the waveforms of (g) and (h) in FIG. You can make a signal.
이 두 신호는 멀티플렉서(8)에 가해지며 그 출력단자(G0)에서는 제어단자 (S2) 입력신호에 따라 제4도의 (i)와 같은 신호가 출력될 수 있도록 한다. 이 출력신호는 수평동기신호 발생회로(9)의 단안정 멀티바이브레타(901, 902) 트리거 입력 (M3, M4)에 인가되며 여기서 가변저항(VR901, VR902)과 콘덴서(C901, C902)에 의해 적당한 펄스폭을 조정되어 본 회로가 사용되는 두배 주사변환기에 연결된 모니터의 수평동기 입력조건에 맞는 신호조건으로 조정되어 두배주사 변환된 영상신호에 맞는 수평동기신호(H/S)로서 가해지는 것이다.These two signals are applied to the multiplexer 8, and the output terminal G 0 allows a signal such as (i) of FIG. 4 to be output according to the control terminal S 2 input signal. This output signal is applied to the monostable multivibrators 901 and 902 trigger inputs M 3 and M 4 of the horizontal synchronous signal generation circuit 9 where the variable resistors VR 901 and VR 902 and the capacitor C 901 , C 902 ), to adjust the appropriate pulse width and to adjust the signal condition to the horizontal synchronization input condition of the monitor connected to the double scan converter using this circuit. ) Is applied.
한편, 리세트회로(3)는 멀티플렉서(2, 8)의 제어단자(S1, S2)에 가해지는 선택신호 위에 N분할카운터(4, 5)의 리세트단자()에 가해지는 리세트 펄스를 발생시켜 제4도에 나타낸 것처럼 영상입력신호(제4도의(a))의 수평동기펄스의 상승단(rising edge)에서 모든 상태가 바뀌어지도록 맞추어주는 기능을 수행한다.On the other hand, the reset circuit 3 has a reset terminal (N) of the N division counters 4 and 5 on the selection signal applied to the control terminals S 1 and S 2 of the multiplexers 2 and 8. It generates a reset pulse applied to the circuit and performs the function of adjusting all the states to be changed at the rising edge of the horizontal synchronization pulse of the image input signal (a of FIG. 4) as shown in FIG. .
이와 같이 본 고안에 의하면 분할카운터 출력측의 멀티플렉서가 불필요하게 되어 구성이 극히 간단해지므로 장치를 소형 경량화할 수 있고 제조원가를 절감할 수 있게 된다.As such, according to the present invention, since the multiplexer on the split counter output side is unnecessary, the configuration becomes extremely simple, so that the device can be reduced in size and weight, and the manufacturing cost can be reduced.
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019850013375U KR890001340Y1 (en) | 1985-10-15 | 1985-10-15 | Double scan device for television set |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019850013375U KR890001340Y1 (en) | 1985-10-15 | 1985-10-15 | Double scan device for television set |
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| Publication Number | Publication Date |
|---|---|
| KR870007535U KR870007535U (en) | 1987-05-13 |
| KR890001340Y1 true KR890001340Y1 (en) | 1989-03-31 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019850013375U KR890001340Y1 (en) | 1985-10-15 | 1985-10-15 | Double scan device for television set |
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| Country | Link |
|---|---|
| KR (1) | KR890001340Y1 (en) |
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1985
- 1985-10-15 KR KR2019850013375U patent/KR890001340Y1/en not_active IP Right Cessation
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| KR870007535U (en) | 1987-05-13 |
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