KR880001287U - Digital data reproduction clock generation circuit - Google Patents
Digital data reproduction clock generation circuitInfo
- Publication number
- KR880001287U KR880001287U KR2019860008907U KR860008907U KR880001287U KR 880001287 U KR880001287 U KR 880001287U KR 2019860008907 U KR2019860008907 U KR 2019860008907U KR 860008907 U KR860008907 U KR 860008907U KR 880001287 U KR880001287 U KR 880001287U
- Authority
- KR
- South Korea
- Prior art keywords
- generation circuit
- digital data
- clock generation
- data reproduction
- reproduction clock
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
- G11B27/10—Indexing; Addressing; Timing or synchronising; Measuring tape travel
- G11B27/19—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019860008907U KR900005132Y1 (en) | 1986-06-24 | 1986-06-24 | Reproducing clock generating circuit of digital data |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019860008907U KR900005132Y1 (en) | 1986-06-24 | 1986-06-24 | Reproducing clock generating circuit of digital data |
Publications (2)
Publication Number | Publication Date |
---|---|
KR880001287U true KR880001287U (en) | 1988-03-15 |
KR900005132Y1 KR900005132Y1 (en) | 1990-06-09 |
Family
ID=19252950
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR2019860008907U KR900005132Y1 (en) | 1986-06-24 | 1986-06-24 | Reproducing clock generating circuit of digital data |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR900005132Y1 (en) |
-
1986
- 1986-06-24 KR KR2019860008907U patent/KR900005132Y1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR900005132Y1 (en) | 1990-06-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE3789291D1 (en) | Video signal generation circuit. | |
DE69033309T2 (en) | Clock generation circuit | |
DE3888220D1 (en) | Data output circuit. | |
DE3485782D1 (en) | CLOCK SYNCHRONIZATION CIRCUIT. | |
NO881209L (en) | DIGITAL LOCKED DATA ENTRY CIRCUIT. | |
KR880016923U (en) | Clock signal generation circuit device | |
FR2544944B1 (en) | DIGITAL DATA RECOVERY CIRCUIT | |
KR880001287U (en) | Digital data reproduction clock generation circuit | |
DE68920464T2 (en) | Clock-controlled data sampling circuit. | |
DE3787385D1 (en) | Generator circuit for clock signal generation. | |
KR860013812U (en) | Clock generation circuit for digital signal reproduction | |
KR880013928U (en) | M F M Lead data signal generation circuit | |
FI840102A0 (en) | EN MED DIGITAL DATA STYRD PULSADDERING OCH -SUBSTRAHERINGS KRETS | |
KR860006672U (en) | Synchronization signal generation circuit when reading the cassette interface | |
KR870014013U (en) | Digital voice data transmission circuit | |
KR900013873U (en) | Digital Signal Synchronization Generation Circuit | |
KR870019326U (en) | Clock generation circuit for image memory | |
KR890003290U (en) | Time clock generation circuit | |
KR860013737U (en) | Digital data signal regeneration circuit | |
KR860001945U (en) | Rotatable advertising digital clock | |
KR880010306U (en) | Synchronized position data lead circuit | |
KR870011461U (en) | Clock signal generation circuit | |
KR880013875U (en) | Surround sound generation circuit | |
KR860003211U (en) | MFM digital modulation circuit | |
KR900005598U (en) | Digital audio data overflow detection circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
REGI | Registration of establishment | ||
FPAY | Annual fee payment |
Payment date: 19970829 Year of fee payment: 10 |
|
LAPS | Lapse due to unpaid annual fee |