KR880000904Y1 - Small signal detecting circuit in high with noise - Google Patents

Small signal detecting circuit in high with noise Download PDF

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Publication number
KR880000904Y1
KR880000904Y1 KR2019840014031U KR840014031U KR880000904Y1 KR 880000904 Y1 KR880000904 Y1 KR 880000904Y1 KR 2019840014031 U KR2019840014031 U KR 2019840014031U KR 840014031 U KR840014031 U KR 840014031U KR 880000904 Y1 KR880000904 Y1 KR 880000904Y1
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South Korea
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noise
fet
circuit
detecting circuit
signal detecting
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KR2019840014031U
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Korean (ko)
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KR860008931U (en
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류광렬
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삼성전자 주식회사
정재은
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H03H11/12—Frequency selective two-port networks using amplifiers with feedback
    • H03H11/1204—Distributed RC filters

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  • Amplifiers (AREA)

Abstract

내용 없음.No content.

Description

고백색 잡음 내에서의 미세신호 검출회로Micro Signal Detection Circuit in High White Noise

본 고안의 회로도.Circuit diagram of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

Q1, Q2: FET T : 트랩Q 1 , Q 2 : FET T: Trap

C1, C5: 콘덴서 R1, R2 … : 저항C 1 , C 5 : condensers R1, R2. : resistance

D1, D2, D3, D4 : 다이오드 10 : 동조회로D1, D2, D3, D4: Diode 10: Tuning Circuit

20, 30 : 과입력 억제부20, 30: over input suppression unit

본 고안은 수신기에 있어서 고백색 잡음 내에서의 미세신호 검출회로에 관한 것으로, RF잡음 자연현상의 잡음등 높은 레벨의 임펄스(impulse)를 포함하고 있는 고백색 잡음(High White Noise)에서 특정한 수신 주파수만을 증폭할 수 있는 회로를 제공하고자 하는 것이다.The present invention relates to a micro-signal detection circuit within high white noise in a receiver, and has a specific reception frequency in high white noise including a high level of impulse such as noise of RF noise natural phenomenon. It is to provide a circuit that can only amplify.

일반적인 수신기에 있어서는 송신된 신호를 모든 고주파 잡음속에서 선별하기 위하여 가능한 높은 증폭도를 갖은 회로를 2-3단 연결시켜 증폭되도록 하였으나 이때에는 불필요한 잡음이 계속 증폭되어 포화현상이 일어나게 되어 수신 회로가 불안정하게 발진되는 요인이 되는 것으로 실제 증폭하여야 할 원신호를 증폭할 수 없는 문제점이 발생되는 것이었다.In the general receiver, in order to select the transmitted signal in all the high frequency noises, the circuit having the highest amplification degree is connected to 2-3 stages to be amplified. In this case, unnecessary noise is continuously amplified and saturation occurs. As a cause of oscillation, there was a problem in that the original signal to be amplified cannot be amplified.

본 고안은 이와같은 점을 감안하여 프리앰프에서 초단증폭한 모든 상태신호를 입력신호로서 사용하며, FET로서 2단 증폭하여 고출력을 얻도록 하되 잡음이 증폭되어 포화현상이 발생되는 것을 억제시키고 원하는 수신 주파수만을 동조시켜 증폭하도록 함으로써 양호한 S/N비를 개선시킬수 있게 한것으로, FET 2단 증폭회로사이에 동조회로 및 과입력 억제부를 구성시켜 된것이다.In consideration of this, the present invention uses all the state signals that are amplified in the preamplifier as input signals, and amplifies the two stages as FETs to obtain a high output, but suppresses the saturation phenomenon caused by noise amplification and desired reception. By tuning only the frequency to amplify, it is possible to improve a good S / N ratio. A tuning circuit and an over-input suppressing unit are formed between the FET two stage amplifying circuits.

따라서, 본 고안의 미세신호 검출회로를 일반적인 녹음기의 앰프사이에 삽입시키면 양질의 녹음특성을 갖게 할 수 있는 것으로 이를 첨부도면에 의하여 상세히 설명하면 다음과 같다.Therefore, when the micro-signal detection circuit of the present invention is inserted between the amplifiers of the general recorder, it is possible to have a high quality recording characteristic, which will be described in detail with reference to the accompanying drawings.

본 고안의 입력단자(1)와 출력단자(2)사이에 구성된 FET(Q1)(Q2)의 2단 증폭회로는 입력 임피던스가 높아 전단에 어떤 증폭기와도 연결하기 편리한 통상의 회로로서 각 저항으로 인가시키는 분배 저항 및 카플링 콘덴서와 직류성분을 차단하는 콘덴서로서 구성시켜 된 것이다.A two-stage amplifier circuit of the input terminal 1 and the output terminal (2), FET (Q 1) (Q 2) is configured between the present design is a conventional circuit convenient due to high input impedance to connect with any amplifier in the front end of each It is constructed as a distribution resistor for applying a resistor, a coupling capacitor, and a capacitor for blocking the DC component.

그리고, FET(Q1)드레인측에 콘덴서(C2)(C3) 및 트랩(T)으로 동조회로 (10)를 구성시키고 FET(Q1)(Q2)의 게이트와소오스측 사이에 다이오드(D1)(D2)(D3)(D4)로 구성된 과입력 제어부(20)(30)를 구성시켜 된것이다.And, between the FET (Q 1), the capacitor (C 2) on the drain side (C 3) and a trap (T) by constituting the tuning (10) and FET (Q 1) (Q 2) of the gate and the source-side The over-input control section 20, 30 composed of the diodes D 1 , D 2 , D 3 , and D 4 is constructed.

미설명 부호 C5는 직류 차단용 콘덴서이고 R6은 분배 저항이다. 이와같이 구성된 본 고안은 전단에 프리앰프를 통하여 증폭된 상태신호가 입력단자(1)로 인가되게 되면 직류 차단용 콘덴서(C1)를 통하여 저항(R1)(R2)으로 분배된 전압이 FET(Q1)의 게이트측에 인가될때에 과입력 억제부(20)를 통하여 인가되므로 다이오드(D1)(D2)에서 고전압이 유기되는잡음레벨 신호는 접지로 흐르게 되고, 수nv에서 수mv로 유기되는 상태신호는 다이오드를 통과하지 못하고, FET(Q1)에 인가하게 된다.Reference numeral C 5 is a DC blocking capacitor and R 6 is a distribution resistor. According to the present invention configured as described above, when the state signal amplified by the preamplifier at the front end is applied to the input terminal 1, the voltage distributed to the resistor R 1 (R 2 ) through the DC blocking capacitor C 1 is FET. When applied to the gate side of (Q 1 ) is applied through the over-input suppression section 20, the noise level signal induced high voltage in the diode (D 1 ) (D 2 ) flows to the ground, and from several nv to several mv The state signal induced by is not passed through the diode and is applied to the FET Q 1 .

그리고, 드레인측에 콘덴서(C2)(C3) 및 트랩(T)으로 동조회로(10)가 구성되어 트랩(T)을 가변시켜 원하는 수신 주파를 선택하면, FET(Q1)(Q2)에 의하여 잡음이 적으며 대역폭이 좁고 신호 이득이 큰 출력신호를 출력단자(2)에서 얻을 수가 있는 것이며, 여기서 과입력 억제부(30)은 FET(Q2)의 게이트에 인가되는 잡음성분을 제거하는 것으로 과입력 억제부(20)와 동일한 동작을 행하게 되는 것이다.Then, when to be a capacitor (C 2) by tuning to the (C 3) and a trap (T) (10) configured on the drain side varies the trap (T) to select the desired reception frequency, FET (Q 1) (Q 2 ) an output signal having a low noise, a narrow bandwidth, and a large signal gain can be obtained from the output terminal 2, wherein the over-input suppression unit 30 is a noise component applied to the gate of the FET Q 2 . The same operation as that of the over-input suppression section 20 is performed by eliminating.

즉, 일반적으로 수신기의 초단 및 각단의 잡음지수를 F1, F2라 하면 전체의 잡음지수는That is, in general, if the noise index of F 1 and F 2 of the receiver's first stage and each stage is F 1 , the overall noise index is

이며 (A1: Q1의 증폭도) FET(Q1)의 잡음지수가 전체 증폭기의 성능을 좌우하게 되는 것으로And (A 1: amplification of Q 1 also) to be the noise figure of the FET (Q 1), influence the performance of the overall amplifier

본 고안은 과입력 억제부(20)(30)의 다이오드에 의하여 잡음이 증폭되어 포화현상이 발생되는 것을 방지할 수 가 있으며, 이때, 실리콘 다이오드를 사용하는 경우0.6-0.7V의 동작전압이 필요하게 되고 게르마늄 다이오드를 사용하는 경우에는 0.2-0.3V의 동작개시 전압이 필요하게 되므로 이 동작개시 전압의 선택으로 과입력 레벨을 조정할 수 있는 효과가 있는 것이다.The present invention can prevent the noise is amplified by the diode of the over-input suppression unit 20, 30 to prevent saturation from occurring. In this case, an operating voltage of 0.6-0.7V is required when using a silicon diode. In case of using germanium diode, 0.2-0.3V starting voltage is required, so the over-input level can be adjusted by selecting the starting voltage.

이상에서와 같이 본 고안은 FET의 게이트와 소오스측사이에 입력 억제부를 구성시켜 잡음 성분이 증폭되는 것을 억제하며 동조회로(10)및 FET(Q1)(Q2)로 부터 대역폭이 좁고 신호이득이 큰 출력전압을 얻을 수가 있는 것으로, 고백색 잡음내에서 미세신호를 검출할 수 있는 회로를 제공할 수 가 있는 것이다.As described above, the present invention configures an input suppression portion between the gate and the source side of the FET to suppress the amplification of noise components, and has a narrow bandwidth and signal from the tuning circuit 10 and the FET Q 1 Q 2 . It is possible to obtain a large gain output voltage, and to provide a circuit capable of detecting a fine signal within high white noise.

Claims (1)

FET(Q1)(Q2)및 분배 저항으로 2단 증폭시키는 통상의회로에 있어서, FET(Q1)의 드레인측에 콘덴서(C2)(C3)및 트랩(T)으로 동조회로(10)를 구성시키고 FET(Q1)(Q2)의 게이트와 소오스측 사이에 다이오드(D1)(D2)(D3)(D4)로 구성된 과입력 억제부(20)(30)를 구성시켜 된 고백색 잡음 내에서의 미세신호 검출회로.In a conventional circuit for two-stage amplification by FETs Q 1 (Q 2 ) and distribution resistors, a tuning circuit with a capacitor C 2 (C 3 ) and a trap T on the drain side of FET Q 1 . An over-input suppression section 20 (30) consisting of a diode (D 1 ), (D 2 ), (D 3 ), (D 4 ), which constitutes (10) and is disposed between the gate and source side of the FET (Q 1 ) (Q 2 ). Micro-signal detection circuit in high white noise composed of
KR2019840014031U 1984-12-24 1984-12-24 Small signal detecting circuit in high with noise KR880000904Y1 (en)

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Application Number Priority Date Filing Date Title
KR2019840014031U KR880000904Y1 (en) 1984-12-24 1984-12-24 Small signal detecting circuit in high with noise

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Application Number Priority Date Filing Date Title
KR2019840014031U KR880000904Y1 (en) 1984-12-24 1984-12-24 Small signal detecting circuit in high with noise

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KR860008931U KR860008931U (en) 1986-07-31
KR880000904Y1 true KR880000904Y1 (en) 1988-03-16

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KR2019840014031U KR880000904Y1 (en) 1984-12-24 1984-12-24 Small signal detecting circuit in high with noise

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KR860008931U (en) 1986-07-31

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