KR860009592A - How to generate synchronous clock of dynamic ram - Google Patents

How to generate synchronous clock of dynamic ram Download PDF

Info

Publication number
KR860009592A
KR860009592A KR1019850003536A KR850003536A KR860009592A KR 860009592 A KR860009592 A KR 860009592A KR 1019850003536 A KR1019850003536 A KR 1019850003536A KR 850003536 A KR850003536 A KR 850003536A KR 860009592 A KR860009592 A KR 860009592A
Authority
KR
South Korea
Prior art keywords
pulse
dynamic ram
synchronous clock
generate synchronous
clock
Prior art date
Application number
KR1019850003536A
Other languages
Korean (ko)
Other versions
KR880001228B1 (en
Inventor
진조철
Original Assignee
정재은
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정재은, 삼성전자 주식회사 filed Critical 정재은
Priority to KR1019850003536A priority Critical patent/KR880001228B1/en
Publication of KR860009592A publication Critical patent/KR860009592A/en
Application granted granted Critical
Publication of KR880001228B1 publication Critical patent/KR880001228B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Facsimiles In General (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

내용 없음No content

Description

다이나믹램의 동기클럭 발생방법How to generate synchronous clock of dynamic ram

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 일반적인 영상정보처리 시스템의 구동펄스 관계도.1 is a driving pulse relationship diagram of a general image information processing system.

제 2 도는 본 발명의 구동펄스 관계도.2 is a driving pulse relationship diagram of the present invention.

제 3 도는 본 발명의 회로도.3 is a circuit diagram of the present invention.

CS : 복합신호 ES : 조기수평펄스CS: Mixed Signal ES: Early Horizontal Pulse

CK : 클럭펄스 CLK : 시스템 클럭펄스CK: Clock Pulse CLK: System Clock Pulse

PS : 감시용 펄스 N1: 낸드 게이트PS: Monitoring pulse N 1 : NAND gate

A1: 앤드 게이트 I1, I2: 인버터A 1 : end gate I 1 , I 2 : inverter

10 : 시스템 클럭발생부 20 : 감시용 펄스발생부10: system clock generator 20: monitoring pulse generator

30 : 콘트롤러30: controller

Claims (1)

복합신호(CS)의 수평펄스 및 클럭펄스(CK)에 의하여 콘트롤러(30)의 시스템 클럭펄스(CLK)를 발생시키며 클럭펄스(CK) 및 조기수평펄스(ES)를 분주시켜 감시용 펄스(PS)가 발생되도록 함으로써 항상 콘트롤러(30)에 시스템 클럭펄스(CLK)를 인가시킬 수 있게한 다이나믹 램의 동기클럭 발생방법.The system clock pulse CLK of the controller 30 is generated by the horizontal pulse and the clock pulse CK of the composite signal CS, and the clock pulse CK and the early horizontal pulse ES are divided to monitor the pulse PS. A method of generating a synchronous clock of a dynamic RAM that always applies a system clock pulse (CLK) to the controller (30). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019850003536A 1985-05-20 1985-05-20 Synchronizing clock generating method of dynamic ram KR880001228B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019850003536A KR880001228B1 (en) 1985-05-20 1985-05-20 Synchronizing clock generating method of dynamic ram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019850003536A KR880001228B1 (en) 1985-05-20 1985-05-20 Synchronizing clock generating method of dynamic ram

Publications (2)

Publication Number Publication Date
KR860009592A true KR860009592A (en) 1986-12-23
KR880001228B1 KR880001228B1 (en) 1988-07-11

Family

ID=19241037

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019850003536A KR880001228B1 (en) 1985-05-20 1985-05-20 Synchronizing clock generating method of dynamic ram

Country Status (1)

Country Link
KR (1) KR880001228B1 (en)

Also Published As

Publication number Publication date
KR880001228B1 (en) 1988-07-11

Similar Documents

Publication Publication Date Title
KR890017972A (en) Plasma display controller system
KR900011144A (en) Duty control circuit
KR880000880A (en) Comparator
KR860009592A (en) How to generate synchronous clock of dynamic ram
KR870010690A (en) Frequency abnormality detection circuit
KR870010528A (en) Sound signal synchronous drive device
KR920017354A (en) Pulse generator with edge detection
KR880000961A (en) Video memory
KR880001147A (en) Vertical drive pulse generator
KR860002048A (en) Time Division ACCESS Control Method for Shared RAM in Multiple Central Control System
KR870006453A (en) Random section reverse display method
KR890001281A (en) Step motor driving pulse generator
KR880005713A (en) Scan address generator of laser printer
KR890010641A (en) Analog clock circuit
KR930014509A (en) High resolution video signal processing device using low frequency oscillator
KR910001641A (en) Stonestone Rhythm of Rhythm Box
KR880008135A (en) Mixed display control device
KR860003549A (en) CRT display control device
KR900010440A (en) Phase conversion method of LCD driving voltage
KR920015717A (en) Synchronous circuit
KR870010734A (en) Synchronous signal generator
KR890004223A (en) Switch-Driven Clock Switching Circuit
KR890005695A (en) Capstan motor speed control circuit
KR910008723A (en) Word line driving signal generation method and circuit
KR880008316A (en) V Seed's Editor

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 19970829

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee