KR860002048A - Time Division ACCESS Control Method for Shared RAM in Multiple Central Control System - Google Patents

Time Division ACCESS Control Method for Shared RAM in Multiple Central Control System Download PDF

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Publication number
KR860002048A
KR860002048A KR1019840004657A KR840004657A KR860002048A KR 860002048 A KR860002048 A KR 860002048A KR 1019840004657 A KR1019840004657 A KR 1019840004657A KR 840004657 A KR840004657 A KR 840004657A KR 860002048 A KR860002048 A KR 860002048A
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KR
South Korea
Prior art keywords
shared ram
time division
control method
control system
access control
Prior art date
Application number
KR1019840004657A
Other languages
Korean (ko)
Other versions
KR860001069B1 (en
Inventor
이광무
Original Assignee
윤영석
대우중공업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 윤영석, 대우중공업 주식회사 filed Critical 윤영석
Priority to KR1019840004657A priority Critical patent/KR860001069B1/en
Publication of KR860002048A publication Critical patent/KR860002048A/en
Application granted granted Critical
Publication of KR860001069B1 publication Critical patent/KR860001069B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

내용 없음No content

Description

다중 중앙제어장치 시스템의 공유 RAM의 시분할 ACCESS 제어방법Time Division ACCESS Control Method for Shared RAM in Multiple Central Control System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도 (가),(나)는 본 발명에 의한 공유 RAM 제어원리를 도시한 도면.1 (a) and (b) illustrate the principle of shared RAM control according to the present invention.

제2도는 본 발명을 적용한 일실시예의 개략구판도.2 is a schematic view of an embodiment to which the present invention is applied.

제3도는 제2도의 상세회로도.3 is a detailed circuit diagram of FIG.

Claims (1)

다수의 CPU부를 포함하며 공유 RAM을 갖는 다중 CPU 시스템에 있어서, 시분할 타이밍제어회로(55)와 3상버퍼 및 랫치(30,38,47,48,49)로서 각 CPU부의 공유 RAM ACCESS가 시분할 펄스로 순차 ACCESS되도록 한 것을 특지응로 하는 공유 RAM ACCESS제어방법.In a multi-CPU system including a plurality of CPU units and having a shared RAM, the time-sharing timing control circuit 55, the three-phase buffers and the latches 30, 38, 47, 48, and 49 are shared RAM ACCESS time-division pulses. Shared RAM ACCESS control method specially adapted to allow ACCESS. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019840004657A 1984-08-03 1984-08-03 Time sharing access control method of common ram in multiprocessor system KR860001069B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019840004657A KR860001069B1 (en) 1984-08-03 1984-08-03 Time sharing access control method of common ram in multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019840004657A KR860001069B1 (en) 1984-08-03 1984-08-03 Time sharing access control method of common ram in multiprocessor system

Publications (2)

Publication Number Publication Date
KR860002048A true KR860002048A (en) 1986-03-26
KR860001069B1 KR860001069B1 (en) 1986-08-04

Family

ID=19234859

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019840004657A KR860001069B1 (en) 1984-08-03 1984-08-03 Time sharing access control method of common ram in multiprocessor system

Country Status (1)

Country Link
KR (1) KR860001069B1 (en)

Also Published As

Publication number Publication date
KR860001069B1 (en) 1986-08-04

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