KR860002147B1 - Mixing circuit of monitor - Google Patents

Abstract

A mixing circuit of monitor system displays the attribute signal like a video character, underline, blank, flash, or inverse signal precisely on the monitor screen by placing the mixing circuit infront of the character generating ROM. It comprises a D flip-frop(1) receiving the attribute signals(w - z), a controller (2), exclusive logic circuits (Ex1, Ex2), a D flip-flop (3), a register(4) receiving the attribute signals(y,z), a character generating ROM(5) receiving row address signal(RA) from a CRT controller, a shift register(6) converting a parallel character signal to the serial video signal, an OR gate(OR2), and an exclusive ligic circuit(EX3).

Description

Mixed circuit of monitor

1 is a circuit diagram of the present invention.

2 is a timing chart according to the real name.

* Explanation of symbols for main parts of the drawings

1,3: D flip-flop 2: Control circuit

4: Register 5: Character Generation ROM

6: Shift register W to Z: Various attribute signals

V: Character serial video signal DT: Character data

RA: Open dress signal CR ₁ , CK ₂ : Control signal

OR, OR: Oagate AD _{1 to} AD ₅ : Endgate

IV ₁ and IV ₂ : Inverter EX _{1 to} EX ₃ : Exclusive logic circuit

DK: Dot Clock Signal CCK: Character Clock Signal

The present invention relates to a mixing circuit of a monitor so that a character video signal and an underscore, blank, flicker, and inverted signal can be matched and displayed on a monitor screen which is a storage device of a computer device.

In general, in order to display a variety of character displays used in computer equipment, when displaying a character video signal and an underscore space, flickering, and inverted signal at the monitor screen and displaying the characters on the monitor screen, Text reading, flickering text and background screen are changed and displayed as inverted text.If the text video signal and attribute signal are not synchronized correctly, the front and back letters overlap or abnormal phenomenon occurs at the edge of the text. The text was difficult to read.

However, conventionally, since the number of gates through which the character video signal and the attribute signal pass is different from each other, an unnecessary D-type flip-flop is installed to register the two signals so that the character video signal is registered. Due to the access time of, the attribute signal is also delayed by that time, which acts to match the character video signal with the attribute signal.

The present invention precisely matches a character video signal with an underscore, space, flickering and inversion signal to display a variety of character displays used in computer equipment. Some control signals are mixed so that the character generating ROM is not specified (blank attribute signal) or specified only at regular intervals (blinking attribute signal). The control circuit is installed in front of the character generating ROM to minimize the difference in time delay. An object of the present invention is to provide a mixed circuit of a monitor so that an attribute signal can be used to the maximum as much as an access time of a character generating ROM consumed without using.

Hereinafter, the configuration, operation, and effects of the present invention will be described in detail with reference to the drawings.

In the present invention, the parallel gate AND gates AD _{1 to} AD ₅ and inverter IV ₁ are inputted to a D-type flip-flop 1 to which underline, inverted signals, blank and flickering attribute signals W to Z are input. IV _2), Iowa gate (OR _1), and an exclusive logic circuit (EX _{1) (EX. 2)} D is a property signal (W), (X) of the parameter the control circuit (2) lines and the inverted signal supplied consisting of Connect the input terminal D ₁ (D ₂ ) of the flip-flop 3 and the reset terminal RT of the register 4 to which the blank and blinking attribute signals Y and Z are supplied, respectively. To the register 4 to which the data DT is supplied, a character generation ROM 5 to which the open-dress signal RA is supplied from the CRT controller is connected, and to the character generation ROM 5 to which character data of ASCII code is generated. A shift register 6 for converting parallel character data into a serial video signal V of characters is connected, and an output terminal Q ₁ (Q ₂ ) and an output terminal of the shift register 6 of the D-type flip-flop 3 are connected. Oh no Byte is a (OR ₂₎ with a structure connected to the Exclusive logic circuit (EX _3).

Reference numerals CK ₁ , CK ₂ are control signals a _{1 to a 3} are signals for determining the underline scan, SL is the shift-lower stage of the shift register 6, DK is the dot clock signal, b ₁ is the console signal, b ₂ denotes an inverted video signal D _{1 to} D ₄ , Q _{1 to} Q ₄ represent an input / output terminal of a D flip-flop, CCK represents a character clock signal, and C ₁ represents a blink rate signal.

1 shows the circuit diagram of the present invention, each of which represents a circuit diagram of the present invention. A serial video (V) signal of an accurately registered character, an underline, a space, The flickering and inverting signal, the attribution signals W to Z, had to be mixed. However, in order to make the transfer delay times of the attribute signals W to Z and the serial video signal V of the characters equal, the attribute signals W to Z are formed by the D-type flip-flop 1 to generate a video signal. The address of the character generating ROM 5 is latched once to the register 4, that is, the same data as the control signal CK ₁ which is the latch signal of the D flip-flop 1 and the register 4, and the latched data While specifying the address of the character generation ROM 5, the attribute signals W to Z are transmitted by the control circuit 2, which is an attribute signal combination, to form a stable signal. These attribute signals W to Z are the character generation ROM ( 5) Wait for valid character data after addressing (property signal (W) (X)) or valid combination of flickering or blank attribute signal (Y) (Z) By resetting the addressing register (4) of (5), the address for generating a valid character is disconnected. As parenting, it will perform the property of flickering or blanking.

In this way, the video signal (V) flashes again, the blank property signal (Y) (Z) and the attribute signal (W) (X) which have been waiting for the character readout time are the same as the D-type flip by the same control signal (CK). It is latched to the flop 3, the shift, and the register 6, and mixed again through the oragate OR ₂ and the exclusive logic circuit ZX ₃ . The circuit waiting for the mixed signal of the attribute signal (W) (X) and the serial video signal (V) of the underline and inverted signals will be described first.In order to underline the underline, the underline attribute signal (W) is a D-type flip-flop. The control signal (1) is supplied to the register 4 in which the character data DT is latched to the input terminal D ₁ of (1), which is a clock signal generated by a central processing unit or a timing circuit suitably composed of hardware. CK ₁ is sent to the output terminals Q _{1 to} Q ₄ of the type flip-flop 1 (1,000), and the output signal of the register 2 is a character generation ROM ( 5) and the dress signal RA is applied from the CRT controller at the same time, the ASCII code character data of the character generating ROM 5 selected by the character key of the keyboard is supplied to the shift register 6.

Since the (1,000) state signal outputs the output terminals Q _{1 to} Q ₄ of the D flip-flop 1, the underline attribute signal W is applied to the AND gate AD ₃ of the control circuit 2, and the CRT since open from the controller to dress the same as each of the input signals (a ₁ ~a ₃₎ a control aND gate (AD ₂₎ (AD ₂₎ of the circuit (2) for determining the underlined scan of the aND gate (AD ₃₎ The output signal is input to the input terminal D ₁ of the D-type flip-flop 3, and accordingly, the control circuit CK ₂ , which is a clock signal, is a clock of the D-type flip-flop 3 in a timing circuit properly configured in hardware. Since the input signal is input to the shift low end SL of the shift register b, the (10) signal is output to the output terminal Q ₁ (Q ₂ ) of the D flip-flop 3, and the shift register 6 is a dot clock signal ( DK) converts the character data of the parallel ASCII load into a serial video (V) signal of characters and inputs them to the OR gate OP ₂ and the exclusive logic circuit EX ₃ , respectively.

Then, the output signal of the OR gate OR ₂ is input to the exclusive logic circuit EX ₂ in a high state while the output terminal Q ₂ of the D-type flip-flop 3 is low in the exclusive logic circuit EX _3. ), The output signal of the exclusive logic circuit EX ₃ is displayed on the monitor screen as underlined characters. In other words, this signal becomes an underline attribute signal determined by the constant opening dresses a _{1 to a 3} .

On the other hand, in order to represent the reversed character by changing the background image, the attribute signal X, which is a switching signal, is inputted to the register 4 in which the character data DT is latched at the input terminal D ₂ of the D flip-flop 1. In this case, the control signal CK ₁ , which is a clock signal, is supplied to the clock stages of the D-type flip-flop 1 and the register 4 in the central processing unit or a timing circuit configured appropriately. A signal in the state (0100) is sent to the output terminals Q _{1 to} Q ₄ of the flop 1, and the output signal of the register 4 is applied to the character generating ROM 5 and simultaneously opened from the CRT controller. Since RA) is applied, the character data of the ASCII load of the character generation ROM 5 selected by the character key of the keyboard is supplied to the shift register 6.

Since the signal in the (0100) state is sent to the output terminals Q _{1 to} Q ₄ of the D flip-flop 1, the attribute signal X, which is a switching signal, is the exclusive logic circuit EX ₁ of the control circuit 2. ) in is input to the keoseul signal (b ₁₎ an exclusive non-logic circuit (EX ₁₎ exclusive logic circuit (EX ₂₎ as the low level output signal of the exclusive logic circuit (EX ₂₎ so applied respectively to, the then low state input to the output signal and the inverted video signal (b ₂₎ a pressure stage (D ₂₎ of the output signal is supplied to the exclusive logic circuit (EX ₂₎ D-type flip-flop (D ₂₎ of the exclusive logic circuit (EX ₁₎ From this, the control signal CK ₂ , which is a clock signal, is input from the timing circuit, which is appropriately composed of hardware, to the clock end of the D-type flip-flop 3 and the shift-lower end SL of the shift register 6. the output terminal (Q ₁₎ (Q ₂₎ of the flip-flop (3), (01) the signal, the shift register 6 is the ASCII code of the character data in parallel by a dot clock signal (DK) is Is changed to the character serial video signal (V) is input to each gate Iowa (OR ₁₎ with exclusion logic circuit (EX _3).

Then, the output signal of the OR gate OR ₂ is inputted into the exclusive video circuit EX _{2 as it} is, and the output terminal Q ₂ of the D-type flip-flop 3 is in the high logic state. It is input to a circuit (EX ₃₎ is the output signal of the exclusive logic circuit (EX ₃₎ changes the background screen is displayed on the display as an inverted letter.

However, a circuit for resetting the address register 4 of the character generator in advance among the transmission and mixed signals of the blank and flickering attribute signal Y (Z) and the serial video signal V of the character will be described first. In order to read out, the empty attribute signal Y is supplied to the register ₄ in which the character data DT is latched to the input terminal D ₄ of the D-type flip-flop 1, respectively. The control signal CK ₁ , which is a clock signal generated by the timing circuit constituted by the hard air, is supplied to the clock stages of the D flip-flop 1 and the register 4, so that the output terminals Q ₁ to D of the flip-flop 1 are provided. Q ₄ ) is sent to the (0001) state signal, and then the (0001) state signal is sent to the output terminals (Q _{1 to} Q ₄ ) of the D-type flip-flop (1), so that the attribute signal (Y) is blank. The inverter IV ₁ of the control circuit 2 is inverted and supplied to the AND gate AD ₅ . From this, the output signal of the AND gate AD _{5 which} is in the low state is input to the OR gate OR ₁ , and the character clock signal CCK such as (2-1) of FIG. 2 is input to the OR gate OR ₁ . The output signal of is applied to the reset terminal RT of the register 4 in the high and low state, and resets the register 4 which directly designates the address of the character generation ROM 5 during that time. (5) serves to prevent the address from coming out of the register 4 during the access time. (That is, it gives 00000000). If the blank signal (Y) is not supplied (the blank signal (Y) is low), the character clock signal (CCK) as shown in (2-1) of FIG. 2 does not cause the oragate (OR ₁ ) to be output. The output signal of the OR gate (OR ₁ ) is always high and the output signal (ASSCII code) of the micro register 4 is applied to the character generating ROM 5 and the dress signal RA is opened from the CRT controller. Since address access is sufficiently made in the generation ROM 5 (as in (2-2) in FIG. 2), valid character data is output after a certain access time (as in (2-3) in FIG. 2), and the shift register 6 is output in parallel. Is supplied.

Thus the character clock signal (CCK) is a space properties are controlled by the signal (Y) of Iowa gate (OR ₁₎ is supplied to the register 4 via the output signal of a space signal properties, such as a second-degree (2-1) When (Y) and the character video signal are mixed and come out as character data, the register 4 is reset at the hatched portion as shown in (2-2) in FIG. ) Character data such as (2-3) is prevented from accessing valid character data, and the character data (character generation ROM (5)) mixed with a blank attribute signal (Y) and a character video signal The control signal CK ₂ , which is a clock signal, is input to the shift signal stage SL, and the dot clock signal DK is input to the clock stage, respectively. data of the character series (V) is changed in Iowa gate (OR ₂₎ Class is.

The resulting mixed serial video data has all of the beads zeroed out. This is because the character generation ROM 5 is made inaccessible. Then, the output signal of the OR gate OR ₂ is input to the low state exclusive logic circuit EX ₃ , where a signal transmitted to the output terminal Q ₁ (Q ₂ ) of the D flip-flop 3 is (00). As the state is input to the oragate (OR ₂ ) and exclusive logic circuit (EX ₃ ), it controls whether or not to export the exclusion through the oragate (OR ₁ ). That is, in the inverted blink rate signal D ₁ , the character clock signal CCK is transmitted through the oragate OR ₁ (the blinking here, and as described above, the character clock signal CCK). Is sent to the oragate (OR ₁ ) to create a space), while the inverted blink rate signal (C ₁ ) is high, the output signal of the oragate (OR ₁ ) is always high (i.e., a character). It does not transmit the clock signal CCK, and makes the normal character generation ROM 5 accessible (not reset the register 4).

This process is repeated by the blink rate, so it is blank / normal / blank / normal…. … This flashes repeatedly. At this time, the output signal of the OR gate OR ₁ is set to a high state by generating the character clock signal CCK at a predetermined interval, and when the character clock signal CCK is generated, the character clock signal CCK is registered as in the above-described blank state. The register 4, which is applied to the reset terminal RT of (4) and directly specifies the address of the character generation ROM 5, is reset during that time, and the address is registered during the access time of the character generation 5; 4) to prevent it from coming out.

When the blinking attribute is set, the blinking is repeated in a constant ratio (blinking ratio (C ₁ )) in a steady state and a blank state, and thus the character clock signal when the blinking rate signal (C ₁ ) is high. Since (CCK) is transmitted through the oragate (OR ₁ ) to reset the register (4), the same operation as when the blank attribute, and when the blink rate signal (C ₁ ) is low, the oragate (OR ₁ ) It keeps the output high and makes it operate normally.

The operation of the other blink rate signal C ₁ in the high state is the same as the operation state described in the blank attribute.

As described above, the present invention accurately displays and displays various characters on the monitor screen, which is an output device of a computer device, by accurately matching and displaying character video signals and attribute signals such as underline, blank, flicker, and inverted signals. have.

Claims (1)

Serially parallel AND gates (AD _{1 to} AD ₅ ) and inverters (IV ₁ ) (IV ₂ ) to the D-type flip flop (1) to which underline, inverted signals, blank and flickering attribute signals (W to Z) are input. Type flip-flop supplied with the underscore and inverted signal (W) (X) via a control circuit (2) consisting of an OR gate (OR ₁ ) and an exclusive logic circuit (EX ₁ ) (EX ₂ ) Input terminal (D ₁ ) (D ₂ ) of (3) and reset terminal (RT) of register (4) to which the blank and flickering attribute signals (Y) (Z) are supplied are respectively connected, and the character data (DT) Is connected to the character generation ROM 5 to which the open-dress signal RA is supplied from the CRT controller, and parallel to the character generation ROM 5 where the character data of the ASCII code is generated. A shift register 6 for converting the character data of the character into a serial video signal V of the character is connected, and the output terminals Q ₁ and Q _{2 of the} D flip-flop 3 are connected to the output terminals of the shift register 6. Oagate (OR ₂ ) And the exclusive logic circuit (EX ₃ ) are connected to the monitor circuit to display on the monitor screen, which is the output device of the computer equipment.

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