KR850008026A - Block division semiconductor memory device having divided bit lines - Google Patents

Abstract

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Description

Block division semiconductor memory device having divided bit lines

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9 is a circuit diagram of a first embodiment of a dynamic RAM having a half bit line according to the present invention, FIG. 10 is a circuit diagram of a sense amplifier of FIG. 9, and FIG. 11 is a second embodiment of a dynamic ram having half bit lines according to the present invention. Schematic diagram

Claims (11)

A memory cell array (1, 2, ..., 1-1, 1-2, 2-1, 2-2 ...) divided into a plurality of blocks, and a plurality of blocks provided for one of the plurality of blocks A plurality of bus bit line means BL ₀ and BL ₀ which are provided in common to the partial bit line means BL ₁ , BL ₁ , BL ₂ , BL _2. A plurality of data transfer means (Q ₁ , Q ₁ '/, Q ₂ , Q ₂ ', ...) connected between one of the plurality of burst line means and one of the plurality of partial bit line means, respectively; and The plurality of data transfer means for selecting and conducting at least one of the plurality of data transfer means to transfer data of the memory cell array from each partial bit line means to each bus bit line means. And a selection means connected to the semiconductor memory device. 2. The apparatus of claim ₁ , further comprising a plurality of sense amplifiers SA ₁ , SA ₂ ..., each connected to one of said plurality of bit line means for amplifying the potential of said plurality of bit line means. A semiconductor memory device characterized in that the. 3. The apparatus of claim 2, wherein the plurality of partial bit line means comprises a pair of partial bit lines BL ₁ , BL ₁ , BL ₂ , BL ₂ , ..., which are multiples of one of the plurality of sense amplifiers. The semiconductor memory device characterized in that. 3. The apparatus of claim 2, wherein the plurality of partial bit line means comprises a pair of open partial bit lines BL ₁ , BL ₁ , BL ₂ , B ₂ , ..., which are connected to one of the plurality of sense amplifiers. The semiconductor memory device characterized in that. 2. The apparatus of claim 1, further comprising: common data bus means (DB, DB) and said plurality of bus bit line means and said common to select one of said plurality of bus bit line means and to connect it to said common data bus means. And a selection means L (D) connected between the data bus means. 3. The semiconductor memory device of claim 2, wherein each of said plurality of sense amplifiers has an active recovery circuit. 7. The apparatus of claim 6, further comprising purifying means connected to said memory cell array for transferring data of each block of said memory cell array to each partial bitline means without conducting said plurality of data transfer means. Semiconductor memory device. 7. The purifying apparatus according to claim 6, wherein the memo-lock cell and the plurality of data transfer means are connected to each other so as to conduct only one of the plurality of data transfer means to transfer data of each bled of the memory cell array to each partial bit line means. A semiconductor memory device, characterized in that it further comprises means. 2. The semiconductor memory device according to claim 1, comprising active recovery circuits (AR) each connected to one of said plurality of bus bit line means to pull down the higher potentials of said plurality of partial bit means. 10. The apparatus of claim 9, further comprising: purging means connected to the memory cell array to transfer data of each block of the demory cell array to each partial bitline means without conducting the plurality of data transfer means. Semiconductor memory device 10. The memory cell array of claim 9, wherein only one of the plurality of data transfer means is connected to the memory cell array and the plurality of data transfer means to transfer data of each block of the memory cell array to each partial bit line means. A semiconductor memory device, characterized in that it further comprises purifying means. ※ Reference window: This is to be disclosed based on the initial application.