KR850002722Y1 - Circuit for detecting the operational state of a television receiver - Google Patents

Abstract

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Description

Operation status detection and processing circuit

1 is a circuit diagram showing an embodiment of the present invention.

2 (a)-(i) are operating waveform diagrams for explaining the operation of the circuit of FIG.

3 and 4 show filter characteristics of the noise detection circuit unit.

5 is a diagram showing channel frequency bands in voice multicasting.

* Explanation of symbols for main parts of the drawings

A: tuning detection circuit B: registration detection circuit

C: Voice Noise Detection Circuit D: Noise Detection Rectifier Circuit

E: Logic Circuit F: Indicator

G: switching circuit H: audio signal muting part

The present invention relates to an operation state detection and control circuit used in a color television receiver.

In a color television receiver, there are cases in which various operation conditions of the receiver are judged and appropriate responses are made accordingly. For example, voice muting is as follows.

As a muting means for the audio signal, a means for FM detecting an intermediate frequency signal and shorting or opening the voice signal line according to the detection output level is common. However, when such a muting means is used in a television receiver, harmonic components generated when FM detection of an intermediate frequency signal are sometimes mixed on the screen as beat interference. Therefore, although a means for suppressing such harmonic components may be provided, the circuit configuration is complicated and the cost is high.

The object of the present invention is to provide an operation condition detection and processing circuit suitable for detecting the various operation conditions of the television receiver described above and for balancing the detection results thereof, and particularly for appealing the reception condition to the time.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 shows a configuration used for a color television receiver capable of receiving voice multiple broadcasts. A is a detection circuit in a tuned state to which a detection output from an automatic frequency tuning circuit (commonly referred to as an AFT circuit) is input. This is referred to as a tuning detection circuit hereinafter. This tuning detection circuit A obtains an output indicative of the non-tuning state when the tuning state, the tuning frequency is shifted toward the high side or the low side.

B is a synchronization detection circuit to which so-called flyback pulses and a horizontal synchronization signal from a flyback transformer are input. This synchronous detection circuit B can take the logical AND of both inputs.

C is a voice noise detection circuit, has a unique pass frequency band, and detects noise in a frequency band that should be an original signal. Therefore, the voice intermediate frequency signal is input to the input terminal. Next, D is a noise detection rectification circuit, which detects and rectifies the output of the voice detection circuit C and changes to DC.

E is a logic circuit. This logic circuit E is a circuit which performs information processing on the outputs of the tuning detection circuit A, the synchronization detection circuit B, and the noise detection circuit C.

This logic circuit E controls the indicator E in accordance with the processing result, and makes it possible to display the tuned state, the tuned state, and the complete non-tuned state. The logic circuit E can also control the muting switching circuit G in accordance with the processing result.

The muting switching circuit G can mute voice according to the control input from the logic circuit E and the control input from the noise detection circuit D. In addition, in response to the output of the synchronization signal detection circuit B, the sensing operation is performed.

Next, the internal structure and connection structure of each circuit are demonstrated concretely.

The tuning detection circuit A has input terminals 1 and 2, to which the first and second detection outputs AFT-1 and AFT-2 (see also second (a)) are input. A condenser 3 is connected between the input terminals 1-2. The input terminals 1 and 2 are connected to the bases of the transistors Q ₁ and Q ₂ via the resistors 4 and 5, respectively. The anodes of the diodes 6 and 7 are connected to the bases of the transistors Q ₁ and Q ₂ , respectively, and the cathodes of the diodes 6 and 7 have a common transistor Q _1. ) And (Q ₂ ) are common emitters. Transistor (Q _1), the collector of the (Q ₂₎ is connected to the base of the transistor (Q ₃₎ (Q ₄₎ via a respective resistor (8), (9), a transistor (Q ₃₎ (Q ₄ ) the emitter is grounded and each collector is connected to the power supply line 12 via resistors 10 and 11, respectively, and each collector is formed of a NAND circuit 55 which forms a logic circuit E. It is connected to the 1st, 2nd input terminal.

In the first and second detection outputs (FIG. 2 (a)) input to the tuning detection circuit A, an output of the center point (frequency position of f ₀ ) of the S-curve is obtained when in the tuning state. Thus, transistors Q ₁ , Q ₂ , and transistors Q ₃ , Q ₄ are turned off. Therefore, the first and second input terminals of the NAND circuit 55 are at a high level, and the output of the circuit 55 is at a low level. Fig. 2 (d) Fig. 3 (b) and Fig. 3 (c) show the outputs of the transistors Q ₃ and Q ₄ , that is, the input waveforms of the NAND circuit 55.

The synchronization signal detection circuit B has a flyback pulse input terminal 15 and a horizontal synchronization signal input terminal 16. The horizontal synchronous signal input terminal 16 is connected to the base of the transistor Q ₅ via a capacitor 17 and a resistor 18 in series. The base of the transistor Q ₅ is grounded through the parallel circuit of the resistor 19 and the capacitor 20, and the emitter is also grounded. The flyback pulse input terminal 15 is connected to the base of the transistor Q ₆ via a resistor 21. The base of the transistor Q ₆ is grounded through the resistor 22, the emitter is connected to the collector of the previous transistor Q ₅ , and the collector is connected to the power supply line via the resistor 23. The collector of this transistor Q ₆ is connected to the base of the transistor Q ₇ via a resistor 24. The base of this transistor Q ₇ . A capacitor 25 is connected between the emitters, and the emitters are connected to the power supply line. The collector of this transistor Q ₇ is grounded via a resistor 26 and connected to the first input terminal of the NAND circuit 56.

The synchronization signal detecting circuit B takes the logic of the flyback pulses of the input terminals 15 and 16 and the horizontal synchronization signal. When both input signals are present, the transistors Q ₅ , Q ₆ , and ( Q ₇ ) is turned on, and the collector potential of the transistor Q ₇ becomes high level. If either the flyback pulse or the synchronous signal is missing, the on operation of the transistor Q ₇ cannot be obtained, and the collector potential becomes an earth potential (low level). The output (collector potential of transistor Q ₇ ) of this synchronization signal detection circuit B is as shown in FIG. 2 (e).

The voice noise detection circuit C has a voice intermediate frequency signal input terminal 30. The input terminal 30 is connected to the base of the transistor Q ₇ via a resistor 31 and a capacitor 32. The connection point of the resistor 31 and the capacitor 32 is grounded through the capacitor 33. The base of the transistor Q ₈ is grounded via a resistor 34 and connected to the power supply line 12 via a resistor 35.

In the peripheral circuit of the transistor Q ₈ , unique filter characteristics are set.

The emitter of the transistor Q ₈ is connected to one end of the coil 38 and the capacitor 39 after passing through the parallel circuit of the resistor 36 and the capacitor 37. The other end of the coil 38 and the condenser 37 is grounded. The collector of the transistor Q ₈ is grounded to the power supply line 12 via the resistor 40 and connected to the base of the transistor Q ₉ via the capacitor 41. The base of this transistor Q ₉ is grounded through a resistor 42 and an opposite diode 43.

The transistor Q ₉ forms a caught detection rectifier, the emitter is grounded, and the collector is connected to the power supply line 12 via a parallel circuit of the resistor 44 and the capacitor 45. The collector of this transistor Q ₉ is connected to the second input terminal of the NAND circuit 56 via a resistor 46.

The voice noise detection circuit (C) and the noise detection rectification circuit (D) are circuits for discriminating when noise is mixed in a place that should be originally a no signal.

In the absence of noise, transistor Q ₈ is " off ". At this time there base bias of the transistor (Q ₉₎ is set to the "off" the transistor (Q _9). Here, when the transistor Q ₁₃ described later is turned "on", even if the transistor Q ₈ is turned "on" and the direct current component is added to the base bias of the transistor Q ₉ , the transistor Q ₉ ) remains "off" state.

Next, when noise is determined, the transistor Q ₈ is turned "on". This is because of the addition output of the DC power supply to the base of the transistor (Q ₉₎ transistors (Q ₈₎ minutes, the transistor (Q ₉₎ is "On". However, and it conditions the transistor (Q _13), which reviews in this case, and off, for example, a transistor (Q ₁₃₎ is the noise, the output is in the "on" state the transistor (Q ₈₎ is be "on" the transistor (Q ₉ ) does not "on".

When the transistor Q ₉ is "on" and its collector potential is at the low level, the second input terminal input level of the NAND circuit 56 is as shown in FIG. 2 (f).

The collector of transistor Q ₉ is connected to the cathode of diode 48 via resistor 47. The connection contact between the diode 48 and the resistor 47 is connected to the power supply line by separating the capacitor 49. The anode of the diode 48 is connected to the base of the transistor Q ₁₀ and simultaneously connected to the first input terminal of the NAND circuit 56 via the diode 50 in the forward direction.

The transistor Q ₁₀ is " on "-" off " at muting time, the collector is grounded, and the emitter is a slider 53 provided in the variable resistor 52 for voice control via the switch unit 51. One end of can be connected. In addition, the collector of this transistor Q ₁₀ can also be connected to the power supply line 12 via the switch part 51. When transistor Q ₁₀ is " on, " the slider is grounded and the audio signal is muted.

Next, in the logic circuit E, the output terminals of the NAND circuits 55 and 56 are connected to the first and second input terminals of the NOR circuit 57. The output terminal of the NAND circuit 56 is connected to the first input terminal of the NAND circuit 58. The output terminal of the NAND circuit 58 is connected to the first and second input terminals of the NAND circuit 66 and to the first and second input terminals of the NOR circuit 59. The output terminal of the NOR circuit 59 is connected to the first and second input terminals of the NOR circuit 60, and the output terminal of the NOR circuit 60 is connected to the NAND circuit (63) via resistors 61 and 62. And the second input terminal of 58). The loops of the NAND circuit 58, the NOR circuit 59, and 60 have a time constant, and a capacitor 63 is connected between the input terminals of the NOR circuit 60.

The output terminal of the NAND circuit 66 is connected to the second input terminal of the NOR circuit 67. The first input terminal of the NOR circuit 67 is also connected. The output terminal of the NOR circuit 57 is connected to the first input terminal of the NOR circuit 67.

The output terminals of the NOR circuits 57 and 67 are connected to the bases of the transistors Q ₁₁ and Q ₁₂ via the resistors 68 and 69, respectively. Transistor (Q _11), connected to the emitter and the emitter grounded, the collector power supply line 12 via the resistor 70 and the light emitting element 71 of the greenish in series with the transistor (Q ₁₁₎ of the (Q ₁₂₎ transistors The collector of Q ₁₂ is connected to the power supply line 12 via a resistor 72 and red light emitting elements 73 and 74.

The output terminal of the NOR circuit 57 is connected to the base of the transistor Q ₁₂ via a resistor 75. The emitter of this transistor Q ₁₃ is grounded and the collector is connected to the base of the preceding transistor Q ₉ .

The present invention is implemented as described above, and the signal waveform of the operation description of this circuit is as shown in FIG.

The circuit according to the present invention includes various features.

First, when the tuning of this circuit is explained from the characteristics, this circuit collects and processes various muting information, thereby obtaining the display of the tuning status and the actual muting operation.

For example, assuming that the reception state is the frequency section F _{1 in} FIG. 2, the tuning point of the S-shaped curve corresponds to that in the AFT detection unit as shown in FIG. Thus, transistors Q ₁ -Q ₄ are off. In the synchronization signal detecting circuit B, the transistor Q ₇ is turned "on" if a normal synchronization signal is obtained. In addition, the transistor Q ₉ is " off " assuming that there is no noise in the noise detection and detection unit.

As a result, the first and second input terminals of the NAND circuit 55 are high level as shown in Figs. 2 (b) and 2 (c), and their outputs are shown in Fig. 2 (d). As is 0. The first and second input terminals of the NAND circuit 56 are high level, and their output is " 0 " as shown in the second (g) diagram. This causes the output of NOR circuit 57 is "1", the transistor (Q ₁₁₎ is "on", the light emission element 71 emits light of green.

In addition, since the output of the NOR circuit 57 is "1", the transistor Q ₁₃ is turned on. This means forcing the transistor Q ₉ to remain "off".

The forcible " off " of transistor Q ₉ must suspend the muting operation attributable to this noise even when noise is detected when it is in the reception state of this frequency section F ₁ . In other words, if the tuning detection output of the settlement is obtained and the normal synchronization signal is obtained, the screen is normal, and it is not preferable to mute the voice completely even if noise is detected at this time. In this case, therefore, the muting caused by noise is forcibly stopped. 2 (e) is an output of the synchronization signal detection circuit. 2 (f) is an output of the noise detection circuit.

However, even in the above state, for example, when one side of the synchronization signal is condensed, the transistor Q ₇ is turned on. As a result, a current path of the base of the transistor Q ₁₀ , the diode 50, and the resistor 26 is formed to perform a muting operation.

When the reception state is in the frequency section F ₁ as described above, the operation in the logic circuit E will be described again. Now, it is assumed that the output of the NAND circuits 55 and 56 is "0" and the output of the NOR circuit 57 is "1" as described above.

Here, the loops of the NAND circuit 58, the NOR circuits 59, and 60 will be described.

In this case, the first input terminal of the NAND circuit 58 is fixed at " 0 ". This means that the output is "1" even if "0" or "1" is input to the second input terminal of this NAND circuit 58. Therefore, the output of the NOR circuit 59 is "0". , The output of the NOR circuit 60 is " 1 ".

The output of the NAND circuit 66 is " 0 ". Here, since the first input terminal of the NOR circuit 67 is "1", the output thereof is "0", and the transistor Q ₁₂ is "off".

Next, the case where the first input terminal of the NAND circuit 58 is fixed to "1" is described. In this case, the output of the NAND circuit 58 changes to "1" or "0" corresponding to input of "0" or "1" to the second input terminal. Therefore, the loops of the NAND circuit 58, the NOR circuit 59, and 60 obtain an oscillation operation. When such an oscillation operation is performed, the output of the NAND circuit 66 also obtains an oscillation output of "0" "1." Even if the oscillation output is obtained here, the first input terminal of the NOR circuit 67 (a nore circuit ( The output of this NOR circuit 67 is "0" as long as the output of 57) indicates "1".

As a result of the above, if the reception state is in the frequency section F ₁ shown in FIG. 2 and a normal tuning detection output is obtained, green light is emitted in the display system. FIG. 2 (h) shows a green lit mode. In the muting system, the muting operation for noise is stopped emotionally. However, if there is a missing registration signal, a muting operation is obtained.

In particular, forcibly suppressing the muting operation due to noise in the reception state is a characteristic part of the above embodiment.

Next, a description will be given of the case where the reception state becomes the frequency section F ₂ or F ₂ ′ shown in the drawing. In this case, since the state of the detection output to the input terminals 1 and 2 changes, the logic level of the first and second input terminals of the NAND circuit 55 is set to "0, 1" or "1,". 0 ". As a result, the output of the NAND circuit 55 becomes "1". Therefore, the output of the NOR circuit 57 becomes "0".

Therefore, in the frequency section F ₂ or F ₂ ′, the transistor Q ₁₃ is turned “off” so that the muting operation can be performed at any time. That is, when the noise is present in the transistor (Q ₈₎ is "On", the output direct-current level of delivery, the base potential of the transistor (Q ₉₎ rises, the transistor (Q ₉₎ is "On". This causes transistor Q ₁₀ to be " on " and muting.

In addition, when noise is not detected and one side of the synchronization signal (fly back pulse or horizontal synchronization signal) is missing, transistor Q ₇ is "off" and the collector potential decreases. In this case, transistor Q ₁₀ The base diode 50 and the bullfight of the resistor 26 are formed and the transistor Q ₁₀ is turned “on.” Therefore, muting is applied even when the synchronization signal is lost.

On the other hand, the display system will be described as follows. Assuming that there is no noise and the synchronization signal is normally obtained, the first and second input terminals of the NAND circuit 56 are both at the high level, and the output thereof is " 0 ". Therefore, since the first input terminal of the NAND circuit 58 is fixed at " 0 ", its output is " 1 ". As a result, the output of the NAND circuit 66 is "0", the output of the NOR circuit 67 is "1", and the transistor Q ₁₂ is turned "on".

Therefore, if the period of the frequency section F ₂ or F ₂ 'is in the reception state and no noise is detected, and the synchronization signal is normal, the red light emitting elements 73 and 74 are turned on and muting is not performed. . 2 (i) shows a light emitting element and a lighting mode.

Next, a description will be given of the case where either the first input terminal or the second input terminal of the NAND circuit 56 becomes "0" in the frequency section described above, and when both input terminals become "0". . In this case, the output of the NAND circuit 56 becomes "1". In this case, oscillation outputs of the NAND circuit 58, the NOR circuit 59, and 60 appear at the output of the NOR circuit 67 to repeat " 0 " " 1 ". In this case, of course, muting is at stake. And the enemy's light emitting element will blink.

In the above fact, first, when the reception state is in the frequency section F ₂ or F ₂ ′ shown in Fig. ₂ , there is no synchronization signal, no noise, no muting, and the red light-emitting element is turned on. In this state, if there is noise or missing synchronization signal, the enemy light emitting device blinks and muting is applied.

Next, the case where the reception state is in the frequency section F ₃ or F ₃ ′ shown in FIG. 2 will be described. In this case, since there is no noise and no synchronization signal, the transistor Q ₁₀ changes to the " on " state and muting is applied. Also in the display system, the output of the NAND circuit 55 is "1", and the output of the NAND circuit 656 is also "1". Therefore, the oscillation output is obtained by the NOR circuit 67, whereby the red flash is interrupted.

Embodiments of the present invention include the following features in that unnecessary muting operations can be performed at any time.

A detection output having a so-called S-curve characteristic, which is an output of an automatic frequency tuning circuit, is applied to the first and third input terminals, and according to the detection output, the first frequency section F ₁ and quasi-equalization in the tuning range are applied. a second frequency area of in the range of F _2, 'takes the output which identifies, respectively, the third frequency interval F ₃ or F ₃ a of the detuning range' F ₂ when for identifying the frequency intervals of the first to A synchronization detection circuit which obtains an output equal to and a synchronization detection circuit which obtains an output of identifying the presence or absence of both of these synchronization signals by taking the logical synchronism of the horizontal synchronization signal and the flyback pulse. And a noise detecting and rectifying means for inputting an audio intermediate frequency signal, having a function of detecting and rectifying out-of-band noise with the audio intermediate frequency, and obtaining an output for determining the presence or absence of noise, and the tuning detection circuit and the synchronous detection circuit. , Noise detection and When the output of the rectifying means is input and the output of the tuning detection circuit is an output corresponding to the first tuning frequency section, the driving circuit for the light emitting element of the first color is driven and corresponding to the third frequency section. In the case of the output, the logic circuit is provided together with the output of the synchronous detection circuit and the noise detection circuit to intermittently drive the drive circuit for the light emitting element of the second color. Therefore, it is possible to easily determine the reception status of the television receiver.

Embodiments of the present invention can easily determine the reception situation has the following features.

A detection output having a so-called S-curve characteristic, which is an output of the automatic frequency tuning circuit, is applied to the first and second input terminals, and according to the detection output, the first frequency section F ₁ , quasi-tuning in the tuning range, is applied. The second frequency section F ₂ , F ₂ ′ in the range was obtained, and the third frequency section F ₃ , F ₃ ′ in the second range was identified. A synchronization detection circuit that obtains the same output as in time, a synchronization signal that obtains the output of identifying the presence or absence of both of these synchronization signals by taking the logic of a horizontal synchronization signal and a flyback pulse, and an intermediate frequency signal Noise detecting and rectifying means having a function of detecting and rectifying the noise outside the band of the voice intermediate frequency to obtain an output for determining the presence of noise, and the tuning detecting circuit, the synchronous detecting circuit, the noise detecting and rectifying means. Is inputted, and these are determined logically, and only when the output of the tuning detection circuit A outputs corresponding to the first tuning frequency section, when it is determined that the output of the noise detecting and rectifying means is free of noise. And muting forced stop means forcibly setting to obtain the same judgment output as the output obtained. Therefore, no unnecessary muting operation is performed.

In the embodiment according to the present invention, the noise detection circuit C and the noise detection circuit D have the following characteristics as a good detection function for muting.

That is, parallel resonant circuits are provided between the input and output terminals of these circuits by the capacitors 37, 39, coils 38, and the like. The impedance Z of this parallel resonance circuit is

Becomes

However, C ₁ : capacity of the condenser 37

C ₂ : capacity of the capacitor 39

L: Inductance of the coil 38

therefore,

to be. Here, if L and C ₁ and C ₂ are selected so that f ₁ is twice the horizontal equalization frequency (approximately 31.5 kHZ) and f ₂ is lower than that, then a series-parallel resonance circuit (from base to collector of transistor Q ₁₎ ), The frequency characteristic is shown as the solid line in the drawing. In this figure, the broken line indicates the frequency characteristic when C ₁ is deleted (trap trap only).

4 shows the total frequency characteristics up to the collector output of transistor Q _{9 in} which the high pass filter and the low pass filter by the capacitors 33 and 32 are combined.

As can be seen from this characteristic diagram, the input to the transistor Q ₉ is mainly composed of frequency components of about 10 kHz to 22 kHz and 40 kHz or more. Therefore, this circuit detects the noise component in the frequency bands above 10kHz-22kHz, 40kHz. Therefore, it is possible to suppress the generation of harmonic components that are likely to occur during detection without increasing the cutoff frequency more than necessary. In addition, in order to detect the noise component near the actual voice band, a squelch circuit capable of realizing a voice muting substantially corresponding to the noise that is a high-definition problem is provided.

It is effective in having a muting function in voice multi-broadcasting with the characteristic filter characteristics as described above. The frequency spectrum of the audio intermediate frequency signal in audio multiplexing is standardized as shown in FIG. That is, the frequency band of the main channel is 0kHz-15kHz, and the frequency band of the subchannel is 16kHz-47kHz. Therefore, the above filter characteristics are responsive to noise components located between the main channel and the sub channel, and noise components located near the upper limit of the band of the sub channel.

In this way, the noise detection and rectification means has a characteristic filter characteristic that responds to noise between the two voice signal frequency bands and near the upper limit of the higher band. As a result, it is not necessary to increase the cutoff frequency of the voice signal detector more than necessary, and it is possible to prevent the screen bite interference caused by the generation of harmonic components at the time of detection, and to make noise in the vicinity of the voice signal band to be outstanding. It is an excellent noise detection means capable of muting operation corresponding to the noise level in question. As a response to such a circuit, the frequency characteristics are changed by controlling the trap circuit "on" and "off" using a mode identification signal during voice and non-voice multiple broadcasts (normal broadcast), and the frequency characteristics are optimized for each broadcast. The frequency band may be set.

The embodiment of the present invention has the following features in the operation of noise detection and its setting as described above, and can perform an extremely effective operation when receiving voice multiple broadcast.

A noise detection circuit to which the first and second channel signals having the first and second frequency bands of the lower side and the upper side are input, and is provided in the noise detection circuit, and a frequency band between the first and second frequency bands. And a filter for setting the pass band as the upper band near the upper limit of the second frequency band, and a detection rectifying circuit for "on" and "off" controlling the switching transistor in accordance with the level of rectifying the detection output of the noise detection circuit. It is a good muting means which is provided, which reduces and does not give unnecessary harmonics to other signals.

As described above, the present invention can provide an operation condition detection and processing circuit suitable for detecting various types of operation up and down of a television receiver and coping with the detection results, and particularly suitable for appealing the received items to time.

Claims (1)

A tuning detection circuit (A) for detecting a tuning state of an automatic frequency tuning circuit of a tuner which automatically tunes to a carrier frequency of a receiving channel, and determining whether the tuning state of the tuner is in the tuning frequency range or the tuning frequency range, and a horizontal equalizer An operation state detection and processing circuit having a synchronous detection circuit (B) for discriminating the presence or absence of a signal, and muting the audio signal when the horizontal synchronization signal is not detected by the registration detection circuit. Is input, and the voice noise detection circuit C which detects the presence or absence of noise in the voice intermediate frequency signal and the noise detection circuit detect that there is no noise in the voice frequency signal. By this, it is detected that the tuned state of the tuner is in the tuned frequency range, and at the same time a sync signal was detected by the sync detection circuit. When the muting operation is forcibly stopped, the muting operation in the tuning frequency range is prevented by providing means (D, 48, 50, Q ₁₀ ) forcibly stopping the muting operation. .