JPS6057266B2 - Operating status detection and processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an operating status detection and processing circuit used in color television receivers and the like.

In a color television receiver, there are cases in which various operating conditions of the receiver are determined and appropriate measures are taken accordingly. For example, regarding audio muting, it is as follows. As audio signal muting means, it is common to perform FM detection on an intermediate frequency signal and short-circuit or open the audio signal line depending on the detected output level.

However, when such a muting means is used in a television receiver, harmonic components generated during FM detection of an intermediate frequency signal may be mixed onto the screen as heat and snow protection. Therefore, means to suppress such harmonic components may be provided, but
The circuit configuration becomes complicated and expensive. It is an object of the present invention to provide an operating situation detection and processing circuit suitable for detecting various operating situations of the above-mentioned television receiver and dealing with the detection results, and particularly suitable for obtaining muting operations. purpose. Embodiments of the present invention will be described below with reference to the drawings.

Figure 1 shows a configuration using a color television receiver capable of receiving audio multiplex broadcasting, and A is a tuning state detection circuit into which the detection output from an automatic frequency tuning circuit (usually referred to as an AFT circuit) is input. This is hereinafter referred to as a tuning detection circuit.

This tuning detection circuit A obtains an output indicating a tuning state and an out-of-tuning state when the tuning frequency is detuned to a higher or lower side. B is a synchronization detection circuit to which a so-called flyback pulse from a flyback transformer and a horizontal synchronization signal are input.

This synchronization detection circuit B can take the logical product of both human forces. C is a voice noise detection circuit which has a unique pass frequency band and detects noise in a frequency band where there should be no signal.

Therefore, the audio intermediate frequency signal is input to the input terminal. Next, D is a noise detection rectification circuit which detects and rectifies the output of the audio noise detection circuit C and converts it into direct current. E is a logic circuit. This logic circuit E is a circuit that processes the outputs of the above-mentioned synchronization detection circuit A, synchronization detection circuit B, and noise detection circuit C. This logic circuit E controls the display F in accordance with the processing result to display an in-tuned state, an out-of-tune state, and a completely out-of-tune state. In addition, the logic circuit E includes a switching circuit G for mutating according to the processing result.
can also be controlled. The switching circuit G for muting can control the audio signal muting section H according to the control input from the logic circuit E and the control input from the noise tuning circuit D.

It also operates in response to the output of the synchronization signal detection circuit B. Next, the internal configuration and connection configuration of each circuit will be specifically explained.

The tuning detection circuit A has input terminals 1 and 2, and a first
, second detection outputs AET-1 and AFT-2 (see FIG. 2a) are input.

A capacitor 3 is connected between input terminals 1 and 2. Input terminals 1 and 2 are connected to the bases of transistors Ql and Q2 via resistors 4 and 5, respectively. transistor Q
The anodes of diodes 6 and 7 are connected to the bases of transistors Q1 and Q2, respectively, and the cathodes of these diodes 6 and 7 are common and connected to the common emitter of transistors Q1 and Q2. The collectors of transistors Ql and Q2 are connected to the bases of transistors Q3 and Q4 via resistors 8 and 9, respectively, the emitters of these transistors Q3 and Q4 are grounded, and the collectors of each transistor are connected to the power supply line via resistors 10 and 11, respectively. 12, and each collector is further connected to the first and second input terminals of a NAND circuit 55 forming the logic circuit E. In the first and second detection outputs (Fig. 2a) input to the above-mentioned tuning detection circuit A, when in the tuning state, an output at the center point of the S-curve (FO frequency position) is obtained, so the transistor Ql, Q2 and j transistors Q3, Q4 are off.

Therefore, the first and second input terminals of the NAND circuit 55 are at high level, and the output of this circuit 55 is at low level. (Figure 2 d) Figure 2 B and c are transistors Q3 and Q.
4 shows the output waveform of the NAND circuit 55, that is, the input waveform of the NAND circuit 55.

Synchronous signal detection circuit B has flyback pulse input terminal 1
5. It has a horizontal synchronization signal terminal 16.

The horizontal synchronization signal input terminal 16 has a capacitor 17 and a resistor 1.
8 in series to the base of transistor q. The base of this transistor Q5 is grounded through a parallel circuit of a resistor 19 and a capacitor 20, and its emitter is also grounded. Flyback pulse input terminal 15 is connected to the base of transistor Q6 via resistor 21. The base of this transistor Q6 is grounded via a resistor 22, the emitter is connected to the collector of the previous transistor q, and the collector is connected to the power supply line 12 via a resistor 23.
connected to. Furthermore, the collector of this transistor Q6 is connected via a resistor 24 to the base of a transistor Q7. A capacitor 25 is connected between the base and emitter of this transistor Q, and the emitter is connected to a power supply line. Further, the collector of this transistor Q is grounded via a resistor 26 and connected to a first input terminal of a NAND circuit 56. The synchronization signal detection circuit B takes the logical product of the flyback pulses at the input terminals 15 and 16 and the horizontal synchronization signal, and when both input signals are present, the transistors Q, Q6, and Q7 are turned on.
The collector potential of transistor Q7 becomes high level.
Furthermore, if either the flyback pulse or the synchronization signal is missing, the transistor Q cannot turn on, and the collector potential becomes the ground potential (low level).
The output of this synchronizing signal detection circuit B (collector potential of transistor Q7) becomes as shown in FIG. 2e when both input signals are present. The audio noise detection circuit C detects a signal sent by audio multiplex broadcasting using FM detection.
F that is FM modulated with low frequency signals and subcarriers
Input terminal 30 for multiple modulation signals that can include M signals
has. This input terminal 30 is connected to the base of a transistor Q8 via a resistor 31 and a capacitor 32.
The connection point between the resistor 31 and the capacitor 32 is the capacitor 33
grounded via. The base of transistor Q8 is grounded via resistor 34 and connected to power supply line 12 via resistor 35. Specific filter characteristics are set for the peripheral circuit of transistor Q8.

The emitter of the transistor Q8 is connected to one end of a coil 38 and a capacitor 39 via a parallel circuit of a resistor 36 and a capacitor 37.

The other ends of this coil 38 and capacitor 39 are grounded.
The collector of transistor q is connected to the power supply line 12 via a resistor 40 and to the base of a transistor Q9 via a capacitor 41. The base of this transistor Q9 is connected to a resistor 42 and a reverse diode 43.
grounded via. Transistor Q forms a noise detection rectifier, has an emitter that is grounded, and a collector that is connected to the power supply line 12 via a parallel circuit of a resistor 44 and a capacitor 45.

Furthermore, the collector of this transistor Q9 is connected to the second input terminal of a NAND circuit 56 via a resistor 46. The above-mentioned voice noise detection circuit C and noise detection rectification circuit D are as follows:
This is a circuit that determines when noise has entered an area where there should be no signal. When there is no noise, transistor Q8 is off.

At this time, the base bias of the transistor Q9 is set so that the transistor Q is turned off. Here, if the transistor Ql3, which will be described later, is on, then
Even if transistor Q8 is turned on and its DC component is added to the base bias of transistor Q, transistor q remains off. Next, when noise is determined, transistor 9 is turned on.

Therefore, the output DC component of the transistor Q8 is added to the base potential of the transistor Q9, and the transistor Q is turned on. However, in this case, the transistor Ql3 described later
The condition is that Q is off, and if transistors Q and 3 are on, even if noise is input and transistor Q8 is turned on, transistor q will not be turned on. When the transistor Q9 is turned on and its collector potential becomes a low level, the input level of the second input terminal of the NAND circuit 56 becomes a low level, and when the transistor Q9 is turned off and its collector potential becomes a high level, the NAND circuit 5
The input level of the second input terminal of No. 6 becomes high level. (Fig. 2 f). The collector of transistor Q9 is connected to the cathode of diode 48 via resistor 47. A connection point between the diode 48 and the resistor 47 is connected to a power supply line via a capacitor 49. The anode of the diode 48 is connected to the base of the transistor QlO, and is also connected to the first input terminal of the AND circuit 56 via the diode 50 in the forward direction. The transistor QlO is turned on during muting, has a collector grounded, and an emitter that can be connected via a switch section 51 to one end of a slider 53 provided on a variable resistor 52 for audio control.

Further, the emitter of this transistor QlO can also be connected to the power supply line 12 via the switch section 51. When transistor QlO is turned on, the slider is grounded and the audio signal is muted. Next, in the logic circuit E, the output terminals of the NAND circuits 55 and 56 are connected to the first and second input terminals of the NOR circuit 57.

Further, the output terminal of the NAND circuit 56 is connected to the first input terminal of the NAND circuit 58. The output terminal of the NAND circuit 58 is connected to the first and second input terminals of the NAND circuit 66 and also to the first and second input terminals of the NOR circuit 59. The output terminal of this NOR circuit 59 is connected to the NOR circuit 6
This NOR circuit 60 is connected to the first and second input terminals of
The output terminal of is connected to the second input terminal of the NAND circuit 58 via resistors 61 and 62. NAND circuit 58,
The loops of the NOR circuits 59 and 60 have a time constant,
A capacitor 63 is connected between the input terminals of the NOR circuit 60.

The output terminal of the NAND circuit 66 is connected to the second output terminal of the NAND circuit 67.
Connected to the input terminal. Also, the first
The output terminal of the NOR circuit 57 is connected to the input terminal. The output terminals of the NOR circuits 57 and 67 are each connected to a resistor 6.
8 and 69 to the bases of transistors Qll and Ql2.

The emitters of transistors Qll and Ql2 are grounded, the collector of transistor Qll is connected to the power supply line 12 via a resistor 70 and a green light emitting element 71 in series, and the collector of transistor Ql2 is connected to a resistor 72 and a red light emitting element 73. , 74 to the power supply line 12.
Furthermore, the output terminal of the NOR circuit 57 is connected to the base of the transistor Ql3 via a resistor 75. The emitter of this transistor Ql3 is grounded, and the collector is connected to the base of the previous transistor q. The present invention is implemented as described above, and a signal waveform diagram illustrating the operation of this circuit is shown in FIG.

The circuit according to the present invention has various features.

First, to explain the characteristics of this circuit during tuning,
This circuit collects and processes various types of muting information, thereby obtaining an indication of the tuning state and an actual muting operation.

For example, assume that the reception state is in frequency section F in FIG. At this time, in the AFT detection section, the tuning points of the S-curve correspond as shown in FIG. 2a. Therefore, transition. Stars Q1-Q4 are off. Furthermore, in the synchronization signal detection circuit B, if a normal synchronization signal is obtained, the transistor Q7 is on. Furthermore, in the noise detection and detection section, assuming that there is no noise, transistor Q9 is off.
Ru. As a result, the first and second input terminals of the NAND circuit 55 are at a high level as shown in FIG.

The first and second input terminals of the NAND circuit 56 are at high level, and the output thereof is "60°" as shown in FIG. , the transistor Qll is turned on, and the green light emitting element 71 emits light.

Furthermore, since the output of the NOR circuit 57 is "1",
Transistor Ql3 turns on.

This means that transistor Q is forced to remain off. The fact that the transistor Q9 is forcibly turned off means that even if noise is detected in the receiving state of the frequency section F1, the muting operation caused by this noise is stopped. It is.

In other words, if a normal synchronization detection output and a normal synchronization signal are obtained, the screen is normal, and in such a case, even if noise is detected, the audio is completely muted. I don't like that. Therefore, in this case, muting caused by noise is forcibly stopped. FIG. 2e shows the output of the synchronization signal detection circuit. Further, FIG. 2f shows the output of the noise detection circuit. However, even in the above state, if either the synchronization signal or the signal is lost, the transistor Q7 is turned off.

Therefore, the base of the transistor QlO, the diode 50
, a current path for resistor 26 is formed, and a muting operation is performed. The operation of the logic circuit E when the reception state is in the frequency section F1 as described above will be further explained.

Now, as before, the outputs of the NAND circuits 55 and 56 are “0-
Assume that the output of the NOR circuit 57 is ゜“1゛.Here,
The loops of the NAND circuit 58 and the NOR circuits 59 and 60 will be explained.

In this case, the first input terminal of the NAND circuit 58 is fixed at "0".

This means that the second input terminal of this NAND circuit 58 is “0”.
Even if ゛ is inputted, ゛ means that even if ``1'' is inputted, the output is ``1''. Therefore, the output of the NOR circuit 59 is "0" and the output of the NOR circuit 60 is "1". Also, the output of the NAND circuit 66 is "0". Here, since the first input terminal of the NOR circuit 67 is "1", its output is "0", and the transistor Ql2 is off. Next, a case where the first input terminal of the NAND circuit 58 is fixed to ゜"1゛1 will be described.

In this case, the output of the NAND circuit 58 changes from "1" to "0" 3 in response to "0" 1 or 44F3 being input to its second input terminal. The loop of the circuit 58 and the NOR circuits 59 and 60 obtains an oscillating operation. When such an oscillating operation occurs, the output of the NAND circuit 66 also obtains an oscillating output of "0゛゜" 1゛.Here,
Even if an oscillation output is obtained, as long as the first input terminal of the NOR circuit 67 (output of the NOR circuit 57) is "1", the output of the NOR circuit 67 is "0". From the above, first, if the receiving state is in the frequency range F1 shown in FIG. 2 and a normal tuning detection output is obtained, green light is emitted in the display system.

Figure 2h shows the green lighting mode. In the muting system, the muting operation regarding noise is forcibly stopped. However, if the synchronization signal is missing,
Muting motion is obtained. Particularly, in the above transmission state, forcibly suppressing the muting operation due to noise is a characteristic part of the above embodiment.

Next, the reception state is in the frequency range F2 or F shown in Figure 2.
The case where the value becomes 2'' will be explained.

In this case, since the state of the detection output input to the input terminals 1 and 2 changes, the logic level of the first and second input terminals of the NAND circuit 55 changes to RO, lJ or Rl, O. As a result, the output of the NAND circuit 55 becomes "°1"3. Therefore, the output of the NOR circuit 57 is at "4"01. Therefore, in the frequency range F2 or F2'', the transistor Ql3 is turned off so that the muting operation can be performed at any time.

In other words, if noise is present and transistor Q8 is turned on, the base potential of transistor 9 increases by the output DC level, and transistor α is turned on. As a result, the transistor QlO turns on and muting is applied. Further, if noise is not detected and one of the synchronization signals (flyback pulse or horizontal synchronization signal) is missing, transistor Q7 is turned off and the collector potential decreases. In this case, the transistor QlO, in which a loop of the base of the transistor QlO, the diode 50, and the resistor 26 is formed, is turned on. Therefore, muting is applied even when the synchronization signal is lost. On the other hand, the display system operates as follows.

Assuming that there is no noise and the synchronization signal is normally obtained, the first and second input terminals of the NAND circuit 56 are both at high level, so the output is '60'1.
Therefore, since the first input terminal of the NAND circuit 58 is fixed at 0, its output becomes 1. For this reason,
The output of the NAND circuit 66 becomes "°0", the output of the NOR circuit 67 becomes "°1", and the transistor Ql2 is turned on. Therefore, if the receiving state is in the frequency section F2 or F2'', no noise is detected, and the synchronization signal is normal, the red light emitting elements 73 and 74 light up and no muting is performed. 21 shows the lighting mode of the light emitting element.Next, in the above frequency range, if either the first input terminal or the second input terminal of the NAND circuit 56 becomes ゜゜0゛, then both The case where the human power terminal becomes ゜“0゛” will be explained.

In this case, the output of the NAND circuit 56 becomes ゜“1゛.
In this case, the oscillation outputs of the NAND circuit 58 and the NOR circuits 59 and 60 are applied to the output of the NOR circuit 67, and "0" and "1" are repeated. Of course, in this case, mutating is involved. The red light emitting element will then blink. From the above, first of all, if the reception state is in the frequency section F2 or F2'' shown in Fig. 2,
If a synchronization signal exists and there is no noise, muting will not occur and the red light emitting element will light up.

In this state, if there is noise or a synchronization signal is missing, the red light emitting element will blink and muting will occur. Next, the reception state is in the frequency section F shown in Figure 2.
3 or F3'' will be explained.

In this case, since there is noise and there is no synchronizing signal, the transistor QlO is turned on and muting is applied.
Also, in the display system, the output voltage of the NAND circuit 55 is
゛, the output of the NAND circuit 56 also becomes ゜゜1゛. Then,
An oscillation output is obtained from the NOR circuit 67, and the red flashing continues. The embodiment according to the present invention includes the following features in terms of suppressing unnecessary muting.

A detection output having a so-called S-curve characteristic, which is an output of the automatic frequency tuning circuit, is applied to the eleventh second input terminal, and depending on the detection output, the first frequency section F1 in the tuning range and the first frequency section F1 in the quasi-tuning range are applied. Second frequency interval, F2
and a horizontal synchronizing signal. , a synchronization detection circuit that performs the logical product of the flyback pulses and outputs an output that identifies the presence of both synchronization signals or the absence of either one, and a synchronization detection circuit that receives multiple modulation signals and detects noise outside the band of the multiple modulation frequency. a noise detection and rectification means which has a function of detecting and rectifying the noise to determine the presence or absence of noise; and the outputs of the tuning detection circuit, the synchronization detection circuit, the noise detection and rectification means are input, driving a drive circuit for a light emitting element of a first color when the output of the circuit is an output corresponding to the first tuning frequency section;
When the output corresponds to the second tuning frequency section, continuously driving a drive circuit for a light emitting element of a second color;
a logic circuit that makes a logical determination together with the outputs of the synchronization detection circuit and the noise detection circuit when the output corresponds to the third frequency section, and continuously drives the drive circuit for the light emitting element of the second color; Equipped with

Therefore, the reception status of the television receiver can be easily determined. The embodiment according to the present invention includes the following features in order to make the reception situation easier to understand.

A detection output having a so-called S-curve characteristic, which is an output of an automatic frequency tuning circuit, is applied to the first and second input terminals, and the first frequency section F1 and the quasi-tuning range in the tuning range are adjusted according to the detection output. The second frequency section Ii8F'
2, F2'' is obtained, and for the third frequency section F3, F3'' in the detuning range, the first frequency section is identified. a synchronization detection circuit that obtains the same output as the synchronization signal, and a synchronization detection circuit that performs the logical product of the horizontal synchronization signal and the flyback pulse and obtains an output that identifies the presence of both or the absence of either of these synchronization signals; a noise detection and rectification means that receives a multiplex modulation signal and has a function of detecting and rectifying noise outside the band of the multiplex modulation frequency to obtain an output that determines the presence or absence of noise; and the tuning detection circuit and the synchronous detection circuit. , the outputs of the noise detection and rectification means are inputted, a logical judgment is made on these, and the output of the tuning detection circuit A is determined as the output of the first tuning detection circuit A.
forced stop of mutating, which is set so as to obtain the same judgment output as the output obtained when it is judged that the output of the noise detection and rectification means is free of noise only when the output corresponds to the tuning frequency interval of the noise detection and rectification means; It is equipped with the means.

Therefore, unnecessary muting operations are not performed.
In the embodiment according to the present invention, the noise detection circuit C and the noise detection circuit D have the following characteristic functions as good detection functions regarding mutating.

That is, a parallel resonant circuit including capacitors 37, 39, a coil 38, etc. is provided between the input and output terminals of these circuits.

The impedance Z of this parallel resonant circuit is as follows.

However, C1: Capacity of capacitor 37 C2: Capacity of capacitor 39 L: Inductance of coil 38 Then, Parallel resonance frequency F,=? 2πj= Series resonant frequency F2=? 2πA and Kayapa? It is.

Here, f1 is twice the horizontal synchronization frequency (approximately 31.5kHz
z), if L, Cl, and C2 are selected so that F2 has a lower frequency, a series-parallel resonant circuit (transistor 9
The frequency characteristics (from the base to the collector) are shown by the solid line in FIG. In this figure, the broken line shows the frequency characteristics when C1 is deleted (in the case of only traps). Figure 4 shows a transistor Q that combines a high-pass filter and a low-pass filter using capacitors 33, 32, etc.
9 shows the overall frequency characteristics up to the collector output. As can be seen from this characteristic diagram, the input to transistor q mainly consists of frequency components of approximately 10 kHz to 22 kHz, and 40 kHz or more.

Therefore, this circuit has a frequency of 10kHz to 22kHz like this
, 40kHz or higher frequency band is detected. Therefore, the generation of high frequency components that are likely to occur during detection can be suppressed without increasing the cutoff frequency more than necessary. In addition, since noise components near the actual voice band are detected, the squelch circuit can realize voice muting that almost corresponds to the noise that causes audible problems. By having the above-mentioned unique filter characteristics,
This is effective in providing a muting function in audio multiplex broadcasting.

The frequency spectrum of a multiplex modulated signal in audio multiplex broadcasting is standardized as shown in FIG. That is, the frequency band of the main channel is 0 kHz to 15 kHz, and the frequency band of one sub channel is 16 kHz to 47 kHz. Therefore, the above-mentioned filter characteristics respond to noise components located between the main channel and the sub-channel and to noise components located near the upper limit of the band of the sub-channel. Thus, the noise detection and rectification means described above has specific filter characteristics that respond to noise between the two audio signal frequency bands and near the upper limit of the higher band.

Therefore, it is not necessary to make the cutoff frequency of the audio signal detector unnecessarily large, and it is possible to prevent screen heat interference due to the generation of harmonic components during detection. This provides an excellent noise detection means that can perform a muting operation corresponding to the noise level that causes the above problem. As an application of such a circuit, the frequency characteristics can be changed by controlling the trap circuit on and off using a mode identification signal, etc. during audio multiplex broadcasting and non-audio multiplexing broadcasting (normal broadcasting), thereby changing the frequency characteristics according to each broadcast. An optimum frequency band may also be set. The embodiment according to the present invention has the following features in the operation of noise detection and its settings as described above, and can perform extremely effective operation when receiving audio multiplex broadcasts. a noise detection circuit to which first and second channel signals having lower and higher frequency bands are input; a filter whose passband is a frequency band between and a frequency band near the upper limit of the second frequency band, and a detection rectifier circuit that controls on/off of a switching transistor according to a level obtained by rectifying the detection output of the noise detection circuit. This is a simple and good muting means that does not give unnecessary high frequencies to other signals.

As described above, the present invention can provide an operating situation detection and processing circuit suitable for detecting various operating conditions of a television receiver and dealing with the detection results, and particularly suitable for obtaining muting operations. .

``Brief Description of the Drawings Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 a-
1 is an operation waveform diagram shown to explain the operation of the circuit in FIG. 1, FIGS. 3 and 4 are diagrams showing filter characteristics of the noise detection circuit section, and FIG. FIG. 3 is a diagram showing channel frequency bands in broadcasting.

A: Tuning detection circuit, B: Synchronization detection circuit, C: Voice noise detection circuit, D: Noise detection rectification circuit, E: Logic Circuit, F...
Display, G... Switching circuit, H...
...Audio signal muting section.

Claims (1)

[Claims] 1 Detection outputs having a so-called S-curve characteristic and having different polarities, which are the outputs of the automatic frequency tuning circuit, are applied to the first and second input terminals, and the first frequency section in the tuning range is adjusted according to the detection outputs. , a tuning detection circuit that obtains an output for identifying each of the second frequency sections in the quasi-tuning range, and obtains an output for the third frequency section in the separated range that is the same as when identifying the first frequency section; , the horizontal synchronization signal, and the flyback pulse, and obtains an output that identifies the presence of both or the absence of either of these synchronization signals, and the multiplex modulation signal is input, and the multiplex modulation frequency is detected. noise detection and rectification means that has a function of detecting and rectifying out-of-band noise and obtains an output that determines the presence or absence of noise; and a muting setting when the noise detection and rectification means obtains an output that determines that there is noise. a mutating switching means for setting a muting release state when a noise-free judgment output is obtained; outputs from the tuning detection circuit, the synchronization detection circuit, and the noise detection and rectification means are supplied; In response to the output corresponding to the first frequency section, the output of the noise detection and rectification means is forcibly set to a noise-free judgment output, and the second
, means for supplying the output of the noise detection and rectification means to the muting switching means in response to the output corresponding to the third frequency section; and an operating state detection and processing circuit.