KR850000955B1 - Noise conceallating circuit - Google Patents

Abstract

The apparatus which comprises a tuning detecting circuit are a synchronization detecting circuit and an audio noise detecting circuit. The tuning detecting circuit detects the tuning state (i.e. proper tuning, mistuning and slight mistuning) of the local oscillator. The tuning detecting circuit receives a pair of oppositely phased signals from an automatic fine tuning circuit, and generates an output signal indicative of the tuning state of the local oscillator. A synchronization detecting circuit, receiving synchronizing signals and flyback pulses, determines whether the synchronization is maintained.

Description

Operation status detection and processing circuit

1 is a circuit diagram showing one embodiment of the present invention.

2 (a) to 2 (i) are operational waveform diagrams for explaining the operation of the circuit of FIG.

3 and 4 show filter characteristics of the noise detection circuit unit.

5 is a diagram showing channel frequency bands in voice multiple broadcasting.

* Explanation of symbols for main parts of the drawings

A: Sync detection circuit B: Sync detection circuit

C: voice noise detection circuit D: noise detection rectification circuit

E: Logic Circuit F: Indicator

G: switching circuit H: audio signal muting section

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to operation state detection and processing circuits used in color television receivers and the like.

In a color television receiver, there are cases in which various operation conditions of the receiver are judged and appropriate responses are made accordingly. For example, voice muting is as follows.

As the muting means for the audio signal, a means for FM detecting the intermediate frequency signal and shorting or opening the audio signal line in accordance with the detection output level is common. However, in a television receiver, when such a muting means is used, there are times when harmonic components generated during FM detection of an intermediate frequency signal are mixed on the screen as beat interference. Therefore, there are cases where a means for suppressing such high frequency components is taken, but the circuit configuration becomes complicated and expensive.

SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to detect a noise component of a frequency band that should be essentially no signal, and to provide and detect an operation state in which a detection output for muting is obtained by somewhat of this noise component.

Embodiments of the present invention will be described below with reference to the drawings.

1 shows a configuration used for a color television receiver capable of receiving voice multiple broadcasts, in which (A) detects a tuning condition in which a detection output from an automatic frequency tuning circuit (commonly referred to as an AFT circuit) is input. This circuit is referred to as a tuning detection circuit hereinafter. This tuning detection circuit A obtains an output indicating the tuning condition, the unillumination status when the tuning frequency is shifted to the higher or lower level.

(B) is a registration detection circuit in which so-called flyback pulses from the flyback transformer and a horizontal registration signal are input. The registration detection circuit B can take the logic of both inputs.

(C) is a voice noise detection circuit, has a unique pass frequency band, and detects noise in a frequency band which should be originally a no signal. Therefore, the voice intermediate frequency signal is input to the input terminal.

Next, (D) is a noise detection rectification circuit, and the output of the audio noise detection circuit C is detected and rectified and converted into direct current.

(E) is a logic circuit. The logic circuit E is a circuit which performs information processing on the outputs of the tuning detection circuit A, the registration detection circuit B, and the noise detection circuit C.

This logic circuit E controls the indicator F in accordance with the processing result, and makes it possible to display the tuned state, the tuned state, and the complete unilluminated state. The logic circuit E can also control the muting switching circuit G in accordance with the processing result.

The muting switch circuit G can mute the audio signal according to the control input from the logic circuit E and the control input from the noise detection circuit D. FIG. In addition, it operates in response to the output of the registered signal detection circuit B. FIG.

Next, the internal structure and connection structure of each circuit are demonstrated concretely.

The tuning detection circuit A has input terminals 1 and 2, and the first and second detection outputs AFT-1 and AFT-2 (second a (reference) are input.) Input terminals 1 to ( The capacitor 3 is connected between 2. The input terminals 1 and 2 are connected to the bases of the transistors Q ₁ and Q ₂ via the resistors 4 and 5, respectively. The anodes of the diodes 6 and 7 are connected to the bases of the transistors Q ₁ and Q ₂ , respectively, and the diodes of the diodes 6 and 7 are commonly used in this transistor Q. _1), via a (h) the transistor (Q _1), the collector of the (Q ₂₎ are each resistor (8) and (9) connected to the meter to a common (Q ₂₎ transistors (Q ₃₎ (Q ₄ ) for being connected to the base, and the emitter ground of the transistor (Q ₃₎ (Q _4), each collector are respectively via a resistor 10, 11 connected to the power supply line 12, again each The collector is connected to the first and second input terminals of the NAND circuit 55 forming the logic circuit E.

In the first and second detection outputs (FIG. A) input to the registration detection circuit A, an output of the center point (frequency position of f) of the S-curve is obtained when in the tuned state, so that the transistor (Q ₁ ), (Q ₂ ) and transistors Q ₃ , (Q ₄ ) are off ”. Therefore, the first and second input terminals of the NAND circuit 55 are at a high level, and the output of the circuit 55 is at a low level. 2 (a), 3 (b) and 3 (c) show the outputs of the transistors Q ₁ and Q ₂ , that is, the input waveform of the NAND circuit 55.

The registration signal detection circuit B has a flyback pulse input terminal 15 and a horizontal registration signal input terminal 16. The horizontal registration signal input terminal 16 is connected to the base of the transistor Q ₅ via a capacitor 17 and a resistor 18 in series. The base of the transistor Q ₅ is grounded through the parallel circuit of the resistor 19 and the capacitor 20, and the emitter is also grounded. The flyback pulse input terminal 15 is connected to the base of the transistor Q ₆ via a resistor 21. The base of this transistor Q ₆ is grounded via a resistor 22, the emitter is connected to the collector of the transistor Q ₅ of voltage, and the collector is connected to the power supply line 12 via a resistor 23. do. Again, the collector of transistor Q ₆ is connected to the base of transistor Q ₇ via a resistor 24. Again, the collector of transistor Q ₆ is connected to the base of transistor Q ₇ via a resistor 24. The capacitor 25 is connected between the base and the emitter of the transistor Q ₇ , and the emitter is connected to the power supply line. The collector of this transistor Q ₇ is grounded via a resistor 26 and connected to the first input terminal of the NAND circuit 56.

The registered signal detecting circuit B takes the logic of the flyback pulses of the input terminals 15 and 16 and the horizontal registered signal. When both input signals are present, the registers Q ₅ and Q _6. Q ₇ becomes “ON” and the collector authenticity of transistor Q ₇ becomes high level. When either the flyback pulse or the registration signal is dropped, the " on " operation of the transistor Q ₇ cannot be obtained, and the collector potential becomes the earth potential (low level). The output (collector potential of transistor Q ₇ ) of the registered signal detection circuit B is the same as that shown in FIG.

The voice noise detection circuit C has a voice intermediate frequency signal input terminal 30. The input terminal 30 is connected to the base of the transistor Q ₈ via a resistor 31 and a capacitor 32. The connection point of the resistor 31 and the capacitor 32 is grounded through the capacitor 33. The base of the transistor Q ₈ is grounded through the resistor 34 and connected to the power supply line 12 via the resistor 35.

In the peripheral circuit of the transistor Q ₈ , unique filter characteristics are set.

The emitter of the transistor Q ₈ is connected to one end of the coil 38 and the capacitor 39 after interposing a parallel circuit of the resistor 36 and the capacitor 37. The other end of the coil 38 and the condenser 39 is grounded. The collector of the transistor Q ₈ is connected to the power supply line 12 via the resistor 40 and at the same time to the base of the transistor Q ₉ via the capacitor 41. The base of this transistor Q ₉ is grounded through a resistor 42 and a reverse diode 43.

The transistor Q ₉ forms a noise detection rectifier, the emitter is grounded, and the collector is connected to the power supply line 12 via the parallel circuit of the resistor 44 and the capacitor 45. Again, the collector of this transistor Q ₉ is connected to the second input terminal of the NAND circuit 56 via a resistor 46.

The voice noise detection circuit (C) and the noise detection rectification circuit (D) are circuits for discriminating when the noise is mixed into a place where the signal should be essentially no signal.

In the absence of noise, transistor Q ₈ is “off”. The transistor has a base bias of the (Q ₉₎ is set such that the transistor (Q ₉₎ is "off". If the transistor Q ₁₃ described later is "on", the transistor Q ₉ is "on" and even if the DC component is added to the base bias of the transistor Q ₉ , the transistor Q ₉ remains ""Off" state.

Next, when noise is determined, the transistor Q ₈ is turned on. This output is a DC-minute addition of a base potential of the transistor (Q ₉₎ transistors (Q ₈₎ and the transistor (Q ₉₎ is "On". However, in this case, it is a condition that the transistor Q _{13 to be} described later is "off", for example, when the transistor Q ₁₃ is in the "on" state, noise is inputted, and the transistor Q ₈ is "on", which causes a transition. Q ₉ is not "on".

When transistor Q ₉ is "on" and its collector potential is at low level, the second input terminal input level of NAND circuit 56 is as shown in FIG. 2 (f).

The collector of transistor Q ₉ is connected to the diode of diode 48 via resistor 47. The connection point between the diode 48 and the resistor 47 is connected to the power supply line via the capacitor 49. The anode of the diode 48 is connected to the base of the transistor Q ₁₀ and simultaneously connected to the first input terminal of the AND circuit 50 via the diode 50 in the forward direction.

The transistor Q ₁₀ is " on "" off " at the time of muting, the collector is grounded, and the emitter is connected to the slider 53 provided in the variable resistor 52 for voice control via the switch 51. You can connect to one end. The collector of the transistor Q ₁₀ can also be connected to the power supply line 12 via the switch unit 51. When transistor Q ₁₀ is "on" the slider is grounded and the audio signal is muted.

Next to the logic circuit E, the output terminals of the NAND circuits 55 and 56 are connected to the first and second input terminals of the NOR circuit 57. The output terminal of the NAND circuit 56 is connected to the first input terminal of the NAND circuit 58. The output terminal of the NAND circuit 58 is connected to the first and second input terminals of the NAND circuit 66 and simultaneously to the first and second input terminals of the NOR circuit 59. The output terminal of the NOR circuit 59 is connected to the first and second input terminals of the NOR circuit 60, and the output terminal of the NOR circuit 60 is connected to the NAND circuit (63) through the resistors 61 and 62. And the second input terminal of 58).

The loops of the NAND circuit 58, the NOR circuit 59, and 60 have a time constant, and a capacitor 63 is connected between the extruded force terminals of the NOR circuit 60.

The output terminal of the NAND circuit 66 is connected to the second input terminal of the NOR circuit 67. The output terminal of the NOR circuit 57 is connected to the first input terminal of the NOR circuit 67.

The output terminals of the NOR circuits 57 and 67 are connected to the bases of the transistors Q ₁₁ and Q ₁₂ via the resistors 68 and 69, respectively. The collector of the transistor (Q _11), (Q ₁₂₎ the emitter and the emitter grounded, the transistor (Q ₁₁₎ of the is connected to the power line 12 via a resistor 70 and light emission of the green element 71 in series, The collector of the transistor Q ₁₂ is connected to the power supply line 12 via the resistor 72 and the red light emitting elements 73 and 74.

The output terminal of the NOR circuit 57 is connected to the base of the transistor Q ₁₃ via a resistor 75. The transistor Q ₁₃ and the emitter are grounded, and the collector is connected to the base of the previous transistor Q ₉ .

The present invention has been carried out as described above, and the signal waveform diagram of the operation description of this circuit can be expressed as the second diagram.

The circuit according to the present invention includes various features.

First, from the characteristics of this circuit tuning, the circuit collects and processes various muting information, whereby the display of the tuning status or the actual muting operation can be obtained.

Now, suppose, for example, that the reception state was the frequency section F _{1 in} FIG. At this time, in the AFT detection unit, as shown in FIG. 2 (a), the tuning point of the S-curve corresponds. Thus, transistors Q ₁ -Q ₄ are “off”. In the synchronization signal detecting circuit B, the transistor Q ₇ is turned "on" if a normal synchronization signal is obtained. In addition, assuming that there is no noise in the noise detection and detection unit, the transistor Q ₉ is in an "off" state.

As a result, the first and second input terminals of the NAND circuit 55 are at the high level as shown in the second (b) and the second (c), and the output thereof is the same as that shown in the second (d) diagram. Likewise, it becomes "0". The first and second input terminals of the NAND circuit 56 are high level, and their output becomes "0" as in the second (g).

As a result, the output of the NOR circuit 57 is "1" and the transformer Q ₁₁ is turned "on" so that the light emitting element 71 of the vegetation emits light.

In addition, since the output of the NOR circuit 57 is "1", the transistor Q ₁₃ is turned "on". This means forcing the transistor Q ₉ to remain in the "off" state.

Forcing transistor Q ₉ to “off” must stop the muting operation due to this noise even when noise is detected, for example, when it is in the reception state of this frequency wave section F ₁ . In other words, if a normal tuning detection output is obtained and a normal tuning signal is obtained, the screen is normal, and even if noise is detected at this time, it is not good to mute the audio completely. In this case, therefore, the muting caused by noise is forcibly stopped. 2 (e) is an output of the synchronization signal detection circuit. 2 (f) is an output of the noise detection circuit.

However, even in the above state, for example, when one of the synchronization signals is missing, the transistor Q ₇ is turned "on". As a result, a wire path of the base of the transistor Q ₁₀ , the diode 50, and the resistor 6 is formed, and muting is performed.

When the reception state is in the frequency section F ₁ as described above, the operation in the logic circuit E will be described again. Now, it is assumed that the output of the NAND circuits 55 and 56 is "0" and the output of the NOR circuit 57 is "1" as described above.

Here, the loops of the NAND circuit 58 and the NOR circuit 60 will be described. In this case, the first input terminal of the NAND circuit 58 is fixed at "0". This means that even if "9" inputs or "1" inputs to the second input terminal of the NAND circuit 58, the output is "1". Therefore, the output of the NOR circuit 59 is "0" and the output of the NOR circuit 60 is "1".

In addition, the output of the NOR circuit 60 is "1". Here, the first input terminal of the NOR circuit 67 is "1", the output thereof is "0", and the transistor Q ₁₂ is "off".

Next, the case where the first input terminal of the NAND circuit 58 is fixed to "1" is described. In this case, the output of the NAND circuit 58 changes to "1" or "0" corresponding to input of "0" or "1" to the second input terminal. Thus, the loops of the NAND circuit 58, the NOR circuits 59, 60 obtain an oscillation operation. When the oscillation operation is performed in this manner, the output of the NAND circuit 66 also obtains an oscillation output of "0" or "1". Even if the oscillation output is obtained here, the output of the NOR circuit 67 is "0" as long as the first input terminal (output of the NOA circuit 57) of the NOR circuit 67 is "1".

In the above fact, first, if the reception state is in the wave section shown in Fig. 2 and a normal tuning detection output is obtained, the display system. The vegetation glows. In FIG. 2 (h), the vegetation shows a lighting mode. In the muting system, the muting operation for noise is forcibly stopped. However, if there is a missing registration signal, a muting operation is obtained.

In particular, forcibly suppressing muting operation due to noise in the reception state is a characteristic part of the embodiment.

Next, the case where the reception state becomes the frequency section F ₁ or F ₂ shown in FIG. In this case, in order to change the state of the detection output to the input terminals 1 and 2, the logic level of the first and second input terminals of the NAND circuit 55 is "0,1" or "1,0. To change. As a result, the output of the AND circuit 55 becomes "1". Therefore, the output of the NOR circuit 57 becomes "0".

Therefore, in the frequency section F ₂ or F ₂ ′, the transistor Q ₁₃ is turned “off” so that the muting operation is always possible. That is, when the transistor (Q ₈₎ "on" with noise is present, the output direct current rebeol minutes and as long as the base potential of the transistor (Q ₉₎ rises, the transistor (Q ₉₎ is "On". This causes transistor Q ₁₀ to be " on " and muting.

In addition, when noise is not detected and one of the synchronization signals (a flyback pulse is a light receiver signal) is missing, the transistor Q ₇ is "off" and the collector potential is lowered. In this case, the loop base of the transistor diode 950, a resistor 26 (Q ₁₀₎₎ is formed in the transistor (Q ₁₀₎ is "On".

Therefore, muting is applied even when the synchronization signal is lost.

On the other hand, the display system will be described as follows. Now, it is assumed that there is no noise and the synchronization signal is obtained normally. Since the first and second input terminals of the NAND circuit 56 are all at the high level, their output is "0". Therefore, since the first input terminal of the NAND circuit 58 is fixed to "0", the output becomes "1". As a result, the output of the NAND circuit 66 becomes "0", the output of the NOR circuit 67 becomes "1", and the transistor Q ₁₂ is turned "on". Accordingly, if the reception state of the frequency section F ₂ or F ₂ ′ is received and no noise is detected and the synchronization signal is normal, the red light emitting elements 73 and 74 light up, and muting is not performed. 2 (i) shows the lighting mode of the light emitting element.

Next, a description will be given of the case where either the first input terminal or the second input terminal of the NAND circuit 56 becomes "0" in the frequency section described above, and when both input terminals become "0". . In this case, the output of the NAND circuit 56 becomes "1". In this case, the oscillation outputs of the NAND circuit 58, the NOR circuits 59, 60 appear at the output of the NOR circuit 67, and repeat "0" and "1". In this case, of course, muting is at stake. And the enemy's light emitting element will blink.

In the above fact, first, when the reception state is shown in FIG. 2 and is in the frequency section F ₂ or F ₂ ′, there is no registered signal, no noise, no muting, and the red light emitting element blinks. In this state, when there is noise or a missing synchronization signal, the enemy light emitting element blinks and muting is applied.

Next, the case where the reception state is in the frequency section F ₃ or F ₃ ′ shown in FIG. 2 will be described. In this case, since there is no noise and no synchronization signal, the transistor Q ₁₀ is "on" and muting is applied. Also in the display system, the output of the NAND circuit 55 is "1", and the output of the NAND circuit 56 is also "1". Therefore, the oscillation output is obtained from the NOR circuit 67, and the enemy flashes continuously.

Embodiments of the present invention have the following features in that unnecessary muting is suppressed.

The output of the automatic frequency tuning circuit has a so-called S-curve detection output applied to the first and second input terminals, and according to the detection output, the first frequency section F1 and quasi-tuning range in the tuning range. When the output of the second frequency section, F ₂ , F ₂ ′ in the output is obtained and the third frequency section F ₃ , F ₃ ′ in the tone range is identified, the first frequency section is identified. A tuning detection circuit which obtains an output equal to

A synchronous detection circuit which takes a logic of a horizontal synchronous signal and a flyback pulse and obtains an output in which both of these synchronous signals are identified or none is identified;

Noise detecting and rectifying means for inputting a voice intermediate frequency signal, having a function of detecting and rectifying noise outside the band of the voice intermediate frequency and obtaining an output for determining the presence or absence of noise;

When the outputs of the tuning detection circuit, the tuning detection circuit, the noise detection and the rectifying means are input, and the output of the singer tuning detection circuit is the output corresponding to the first tuning frequency section, the drive cycle for the light emitting element of the first color Driving the furnace, and continuously driving the driving circuit for the light emitting device of the second color when the output corresponds to the second tuning frequency section, and when the output corresponds to the third frequency section, the synchronization. A logic furnace for driving the driving circuit for the light emitting element of the second color by intermittently determining the same as the output of the detection circuit and the noise detection circuit is provided. Therefore, the reception status of the television receiver can be easily determined.

Embodiments of the present invention have the following characteristics in that the reception situation is easy to understand.

A detection output having a so-called S-shaped curve characteristic, which is an output of the automatic frequency tuning circuit, is applied to the first and second input terminals, and according to the detection output, the first frequency section F ₁ and quasi-driving range in the tuning range. The second frequency section F ₂ , F ₂ ′ in the output is obtained, and the third frequency section F ₃ , F ₃ ′ in this _pair is obtained when the first frequency section is identified. A tuning detection circuit which obtains the same output,

A synchronous detection circuit which takes a logic of a horizontal synchronous signal and a flyback pulse and obtains an output in which both of the mobile synchronous signals are identified or none of them are obtained;

Noise detecting and rectifying means for inputting a sound intermediate frequency signal, having a function of detecting and rectifying noise outside the band of the sound intermediate frequency, and obtaining an output for determining the presence or absence of noise;

The noise detection circuit, the noise detection circuit, the noise detection and the output of the rectifying means are input, and the logic is judged so that the noise is detected only when the output of the tuning detection circuit A is an output corresponding to the first tuning frequency section. And muting forced stop means for forcibly setting the output of the rectifying means to obtain the same determination output as the output obtained when it is determined that there is no noise. Therefore, there is no unnecessary muting operation.

In the embodiment according to the present invention, the noise detection call path (C) and the noise detection circuit (D) have functions having the following characteristics as a good detection function for muting.

That is, parallel resonant circuits are provided between the input / output terminals of these circuits in the capacitors 37, 39, coils 38, and the like. The impedance (Z) of this parallel resonance circuit is

Becomes However, C ₁ : capacity of the condenser 37

C ₂ : capacity of the capacitor 39

L: Inductance of the coil 38

therefore

Parallel resonant frequency

Series Resonant Frequency

to be. Here, if L and C ₁ and C ₂ are selected such that f ₁ is twice the horizontal synchronous frequency (about 31.5KH ₂ ) and f ₂ is a lower frequency than that, a series-parallel resonance circuit (base of transistor Q ₁ The frequency characteristics of (from) to collector are as shown by the solid line in FIG. In this figure, the broken line indicates the frequency characteristic when C ₁ is deleted (in the trap trap).

4 shows the total frequency characteristics up to the collector output of the transistor Q _{9 in} which the high pass filter and the low pass filter by the capacitors 33 and 32 are combined.

As can be seen from this characteristic diagram, the input of the transistor Q ₉ is mainly composed of frequency components of approximately 10 KHz-22 KHz and 40 KH ₂ or more. Therefore, this circuit detects the noise components of the frequency bands above 40KHz, 10KHz-22KHz and 40KHz. Therefore, it is possible to suppress generation of harmonic components that are likely to occur during detection without increasing the cutoff frequency more than necessary. In addition, in order to detect a noise component near the actual voice band, a squelch circuit capable of realizing a corresponding voice muting in the past, which is a problem of hearing, is realized.

It is effective to have a muting function in voice multiple broadcasting, because it has the characteristic filter characteristic as described above. The frequency spectrum of the audio intermediate frequency signal in the audio multiplexing is standardized as shown in FIG. That is, the frequency band of the main channel is 0KHz-15KHz, and the frequency band of the subchannel is 16KHz-47KHz. Therefore, the above filter characteristics are responsive to noise components located between the main channel and the sub channel and noise components located near the upper limit of the band of the sub channel.

In this way, the noise detection and rectification means has a characteristic filter characteristic that responds to noise between the two voice signal frequency bands and near the upper limit of the upper band. As a result, it is not necessary to increase the cutoff frequency of the audio signal detector more than necessary, and it is possible to prevent the screen bead interference due to generation of harmonic components during detection. Further, in order to detect noise in the vicinity of the voice signal band, it is an excellent noise detection means capable of performing a muting operation corresponding to the noise level that is a hearing problem. As the melting of these circuits, the frequency characteristics are changed by controlling the trap circuit “on” and “off” using a mode identification signal or the like during voice multicasting and non-voice multicasting (normal broadcasting). The optimum frequency band may be set.

The embodiment of the present invention has the following features in the operation of noise detection and the description as described above, and can perform extremely effective operation when receiving voice multiple broadcast.

A noise detection circuit to which the first and second channel signals having the lower and upper first and second frequency bands are input and provided in the noise detection circuit, and between the first and second frequency bands. A filter having a pass band of a frequency band and an upper frequency band near the upper limit of the second frequency band, and a detection rectifier circuit for controlling the switching transistor to "on" and "off" according to the level of rectifying the detection output of the noise detection circuit. It is a good muting means which is simple and simple and does not give unnecessary harmonics to other signals.

As described above, the present invention can provide an operation situation and a processing circuit for detecting a noise component of a frequency band which is to be essentially no signal, and obtaining a detection output for muting according to some of the noise component.

Claims (1)

Frequency between the noise detection circuit to which the first and second channel signals having the lower and higher bias first and second frequency bands are input, and the first and second frequency bands provided in the noise detection circuit. A filter for passing through the band and the frequency band near the upper limit of the second frequency band, and a switching transistor according to the level at which the detection output of the noise detection circuit is rectified. and a detection rectifier circuit for controlling the tran sistor on and off.

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