KR830001380B1 - A television set - Google Patents

Abstract

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Description

A television set

1 is a diagram showing the configuration of a memory.

2 is a timing chart showing the principles of the present invention.

3 is a circuit diagram showing an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

(13) Control circuit SA: A channel broadcasting signal

SB: B channel broadcasting signal (W ₁ ) (W ₂ ): Write pulse

(1G ₁ ), (1R ₁ ), (1B ₁ ), (1G ₂ ), (1R ₂ ), (1B ₂ ): memory

The present invention relates to a two-screen television receiver in which a screen of a B channel is reduced and displayed on a screen of an A channel. In particular, the horizontal resolution when the color screen is reduced and reflected is increased. .

In a conventional two-screen receiver, the video signal of the B-channel broadcasting station (hereinafter referred to as signal SB) is alternately written to two feed memories, and the other memory is read and read while one memory is being written. The signal is inserted into a blanking period formed at a predetermined position of a video signal of the A-channel broadcasting station (hereinafter referred to as signal SA). In this case, the signal SB is sampled and written by a write pulse of a predetermined frequency, and in this case, since the unsampled period occurs in the signal SB, the horizontal resolution of the screen decreases accordingly. The phases of the write pulses applied to the phases are reversed from each other, and the period of time that has not been sampled in one memory is sampled in the other memory This method is valid when the signal SB is a black and white signal, but when R, G, B (red, green, blue) signals are simultaneously sampled in one bit of the write pulse when the signal SB is a color signal, In some cases, a problem occurs such that a residual amount occurs in the vertical line of the image.

The present invention is to solve the above-described problem, and the following describes an embodiment of the present invention with reference to the drawings.

Fig. 1 shows the configuration of the dead memory 1 made of the BBD used in the present invention. In the case where the screen of the signal SB is reduced and inserted into the screen of the signal SA by 1/3, as shown in the memory 1, for example, 64 1-bit cells (x ₁ ) to (x ₆₄ ) are connected in series. For example, a BBD having a so-called SPS structure in which 88 BBDs are connected in parallel (y ₁ to y ₈₈ ) is used. And a signal, the 1H signal of a minute in each 3H 1H minutes of the signal SB is written, each _{(BBD) y 1 ~ (y} 88) is written for a single BBD. Therefore, the number of BBD is t1. In addition, each bit cell (x ₁ ) to (x ₆₄ ) is respectively (x ₁₁ ), (x ₁₂ ), (x ₂₁ ), (x ₂₂ ) ...... (x ₆₄₁ ), (x ₆₄₂ ) It consists of two half-bit cells. The information stored in (x ₁₂ ) to (x ₆₄₂ ) of each BBD is sequentially transmitted as arrows in the direction of (y ₁ ) to (y ₈₈ ) from (x ₁₂ ) to (x ₆₄₂ ) of the following BBD.

In the memory 1 configured as described above, at the time of writing, one feed of the signal SB is written by two-phase write pulses reversed from each other. First, information is written to (x ₁₁ ) of the BBD of (y ₁ ) by the first write pulse. This information is passed down to (x ₁₂ ) by the next pulse and again transferred to (x ₂₁ ) by the next pulse. In this manner, each time a write pulse is applied, new information is sampled, and stored information is sequentially transmitted from (x ₁ ) to (x ₆₄ ). When the information is stored in (x ₁₂ ) to (x ₆₄₂ ), writing for 1H ends. And then the shift pulse is applied to the, (y _1), information on _{(x 12) ~ (x 642} ) of the BBD (y ₂₎ from the BBD is respectively transmitted. The next 1H signal is input to the next (y ₁ ) BBD. And it is transmitted to a the (y ₂₎ by the next shift pulse at the same time the information is transmitted to the (y _3), information of _{(y 1) (y 2)} . The same operation is repeated below, and when information is stored in each of (x ₁₂ ) to (x ₆₄₂ ) of (y ₁ ) to (y ₈₈ ) as shown by the oblique lines in FIG. The contents of one feed of the signal SB are written. At the time of reading, reading is performed in the order of (y ₈₈ ) to (y ₁ ) by reading pulses of two phases which are inverse phases. This reading is performed at a speed three times as large as 1H in the horizontal direction.

In the present invention, a total of six memories each configured as described above are used for R, G, and B signals. A total of three memories, one for each of the R, G, and B signals, are used for the first feed and the remaining three are used for the second feed. In addition, while one of the three memories for the first feed and the three memories for the second feed is written, the other is read out, and this is alternately performed every one feed. In this case, in the present invention, the timing of writing to R, G, and B of the first and second feed is performed as shown in FIG. In Fig. 2, the signal SB represents the portion of the H period corresponding to each other of the first and second feeds. First, the first to-be-Ile by the write pulse (W ₁₎ a writing pulse (W ₁₎ and the reverse phase of the writing pulse (W ₂₎ at the same time to be written to a memory by sampling the G signal of the SB signal by, R signal The and signals are sampled simultaneously and written to two different memories. In the next second feed, the G signal is written to the other three memories by the write pulse W ₂ , and the R and B signals are simultaneously written by the write pulse W ₁ . As described with reference to FIG. 1, the write-out of the memory is performed by two phase clock pulses which are in phase with each other, and the write pulse W _{1 of} FIG. 2 shows the timing of sampling and transmission by the two phase pulses. To indicate. The same applies to the write pulse W ₂ . When the written signals are read out as described above to form one frame screen, G, R, and B compensate each other between adjacent long lines, and the write pulses W ₁ , W ₂ , etc. are in phase. Compared to the case where it is, the horizontal resolution can be doubled in appearance. In addition, it is more effective because there is no period in which sampling is not carried out even for one feed.

2 shows an embodiment of a two-screen receiver based on the principle described above. The signal SA obtained through the tuner 2, the IF amplifier 4, and the image detection circuit 6 at the antenna is applied to the decoder 9, and the R, G, and B signals are obtained by a known method. Are obtained, and these signals are applied to the mixer circuit 8. In addition, the signal SB obtained through the tuner 3, the IF amplifier 5, and the video detection circuit 7 is applied to the decoder 10 to obtain R, G, and B signals. These R, G, and B signals are respectively supplied to the memory 1G ₁ (1R ₁ ) 1B ₁ for the first feed and the memory 1G ₂ (1R ₂ ) 1B _{2 for the second} feed. . In addition, the signals SA and SB are applied to the moving mood circuits 11 and 12, respectively, so that the horizontal and vertical synchronization signals HD _A , HD _B , VD _A , and VD _B are separated.

The control circuit 13 writes the write pulses W ₁ , W _{2 that} are in phase with each other, the read pulses R ₁ , R _{2 that} are in phase with each other, and the shift pulse S to each memory based on the synchronization signal. Form and output. These pulses (W ₁ ), (W ₂ ), (R ₁ ), (R ₂ ), and S are in fact composed of two-phase pulses that are reversed from each other. In these pulse is applied to in order to perform a firm and read out based on the second-degree principle, pulse _{(W 1), (R 1} ) includes a memory _{(1G 1) (1R 2)} (1B 2), pulse (W ₂ ), (R ₂ ) is applied to the memory 1G ₂ (1R ₁ ) (1B ₁ ), and the shift pulse S is applied to all memories in common. And while writing the second feed into the memory 1G ₂ (1R ₂ ) 1B ₂ , the contents written in the first feed period in the memory 1G ₁ , 1R ₁ (1B ₁ ) When the reading is completed, the contents of the above-described shield of the memory 1G ₂ (1R ₂ ) 1B ₂ are read out next.

The writing of these memories is synchronized with the synchronization signal of the signal SB, and the reading is synchronized with the synchronization signal of the signal SA. The read signal is applied to the mixer circuit 8 and synthesized in a predetermined portion of the signal SA. In this case, the mixer circuit 8 is supplied with the retrace clear signal BLK obtained by the control circuit 13 based on HD _A and VD _A , and the signal SB is inserted into a predetermined portion of the signal SA based on the signal BLK. .

This synthesized signal is applied to the cathode ray tube 15 via the image amplifier 14. As a result, the screen of the signal SB is reduced to 1/3 in the screen of the signal SA and is reflected.

The pulses W ₂ and R ₂ can be obtained by shifting the pulses W ₁ and R ₁ by one bit when the memory has an SPS structure.

According to the present invention, in a television receiver which is embedded in a screen of a B-channel broadcast in a screen of an A-channel broadcast, the R, G, and B signals obtained from the first feed of the B-channel broadcast signal (for example, the signal SB) Three memory devices (e.g., memory 1G ₁ ) (1R ₁ ) (1B ₁ ) and three memory devices each for R, G and B signals obtained from the second feed (e.g., Memory 1G ₂ (1R ₂ ) (1B ₂ )), and one of the R, G, and B signals (for example, the G signal) and two signals (for example, the R and B signals) Write with the write pulses that are in phase opposite to each other in the first feed (for example, write G into (W ₁ ) and R and B into (W ₂ )), and in the second feed, The present invention relates to a television receiver characterized in that an enterprise (for example, G is written as (W ₂ ) and R and B is written as (W ₁ )) is written using a reversed write pulse.

Therefore, according to the present invention, when the color screen is embedded in a certain screen, the horizontal resolution of the screen to be inserted can be increased without producing a camera or the like.

Claims (1)

A television receiver in which a B-channel broadcast screen is displayed on an A-channel broadcast screen, wherein the three memory devices each store R, G, and B signals obtained from the first feed of the B-channel broadcast signal SB; Three memory devices for storing the R, G, and B signals obtained from the second feed are respectively provided so that one of the R, G, and B signals and two signals are reversed from each other at the first feed. ₁ ) W ₂ and write as write pulses W ₁ (W ₂ ) that are in phase opposite to the first feed in the second feed.

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