KR20240163616A - 자기 재료를 포함하는 집적 디바이스 및 집적 수동 디바이스 - Google Patents

자기 재료를 포함하는 집적 디바이스 및 집적 수동 디바이스 Download PDF

Info

Publication number
KR20240163616A
KR20240163616A KR1020247028946A KR20247028946A KR20240163616A KR 20240163616 A KR20240163616 A KR 20240163616A KR 1020247028946 A KR1020247028946 A KR 1020247028946A KR 20247028946 A KR20247028946 A KR 20247028946A KR 20240163616 A KR20240163616 A KR 20240163616A
Authority
KR
South Korea
Prior art keywords
die
interconnect
interconnects
magnetic layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
KR1020247028946A
Other languages
English (en)
Korean (ko)
Inventor
카이 리우
제-슝 란
종해 김
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20240163616A publication Critical patent/KR20240163616A/ko
Pending legal-status Critical Current

Links

Images

Classifications

    • H01L23/5223—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H10W20/496—Capacitor integral with wiring layers
    • H01L23/5226—
    • H01L23/5227—
    • H01L23/53295—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/20—Inductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/497—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
KR1020247028946A 2022-03-25 2023-03-09 자기 재료를 포함하는 집적 디바이스 및 집적 수동 디바이스 Pending KR20240163616A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/705,041 US12142561B2 (en) 2022-03-25 2022-03-25 Integrated device and integrated passive device comprising magnetic material
US17/705,041 2022-03-25
PCT/US2023/064058 WO2023183722A1 (en) 2022-03-25 2023-03-09 Integrated device and integrated passive device comprising magnetic material

Publications (1)

Publication Number Publication Date
KR20240163616A true KR20240163616A (ko) 2024-11-19

Family

ID=85979732

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020247028946A Pending KR20240163616A (ko) 2022-03-25 2023-03-09 자기 재료를 포함하는 집적 디바이스 및 집적 수동 디바이스

Country Status (7)

Country Link
US (1) US12142561B2 (enExample)
EP (1) EP4500593A1 (enExample)
JP (1) JP2025509903A (enExample)
KR (1) KR20240163616A (enExample)
CN (1) CN118805252A (enExample)
TW (1) TW202401725A (enExample)
WO (1) WO2023183722A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240355728A1 (en) * 2023-04-21 2024-10-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure
US20250037923A1 (en) * 2023-07-27 2025-01-30 Qualcomm Incorporated Package comprising a substrate with inductors and a magnetic layer

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7319599B2 (en) * 2003-10-01 2008-01-15 Matsushita Electric Industrial Co., Ltd. Module incorporating a capacitor, method for manufacturing the same, and capacitor used therefor
US8044755B2 (en) 2008-04-09 2011-10-25 National Semiconductor Corporation MEMS power inductor
US20150340422A1 (en) * 2014-05-23 2015-11-26 Texas Instruments Incorporated Method of manufacturing a micro-fabricated wafer level integrated inductor or transformer for high frequency switch mode power supplies
US10354950B2 (en) 2016-02-25 2019-07-16 Ferric Inc. Systems and methods for microelectronics fabrication and packaging using a magnetic polymer
US10064277B2 (en) * 2016-03-29 2018-08-28 Ferric, Inc. Integrated passive devices and assemblies including same
US12424543B2 (en) 2019-11-26 2025-09-23 Intel Corporation Selective interconnects in back-end-of-line metallization stacks of integrated circuitry

Also Published As

Publication number Publication date
CN118805252A (zh) 2024-10-18
JP2025509903A (ja) 2025-04-11
EP4500593A1 (en) 2025-02-05
WO2023183722A1 (en) 2023-09-28
US12142561B2 (en) 2024-11-12
US20230307355A1 (en) 2023-09-28
TW202401725A (zh) 2024-01-01

Similar Documents

Publication Publication Date Title
US12354948B2 (en) Integrated device and integrated passive device comprising magnetic material
US20250105145A1 (en) Integrated device and integrated passive device comprising inductively coupled inductors surrounded by a magnetic material
US12027476B2 (en) Package comprising substrate with coupling element for integrated devices
US12142561B2 (en) Integrated device and integrated passive device comprising magnetic material
US12100649B2 (en) Package comprising an integrated device with a back side metal layer
US20240258363A1 (en) Integrated device comprising plate interconnects and a magnetic material
US12125742B2 (en) Package comprising a substrate with high density interconnects
WO2024039939A1 (en) Package comprising a first substrate, a second substrate and an electrical device coupled to a bottom surface of the second substrate
US20250037923A1 (en) Package comprising a substrate with inductors and a magnetic layer
US20250022858A1 (en) Device comprising stacked through encapsulation via interconnects
US11869833B2 (en) Package comprising a substrate with a via interconnect coupled to a trace interconnect and method of fabricating the same
KR20250046259A (ko) 집적 디바이스 및 제2 금속화 부분에 커플링된 제1 금속화 부분을 포함하는 패키지
WO2025254841A1 (en) Package comprising an integrated device and an offset memory device
EP4537397A1 (en) Package comprising a substrate with a bridge configured for a back side power distribution network
KR20250010586A (ko) 고밀도 상호연결을 위해 구성된 상호연결 다이 및 기판을 포함하는 패키지

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000