KR20240116754A - 반도체 장치, 반도체 장치의 제작 방법 - Google Patents

반도체 장치, 반도체 장치의 제작 방법 Download PDF

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Publication number
KR20240116754A
KR20240116754A KR1020247020479A KR20247020479A KR20240116754A KR 20240116754 A KR20240116754 A KR 20240116754A KR 1020247020479 A KR1020247020479 A KR 1020247020479A KR 20247020479 A KR20247020479 A KR 20247020479A KR 20240116754 A KR20240116754 A KR 20240116754A
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South Korea
Prior art keywords
insulator
conductor
oxide
additionally
oxygen
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Pending
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KR1020247020479A
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English (en)
Korean (ko)
Inventor
료타 호도
사토루 사이토
히토시 쿠니타케
슌페이 야마자키
šœ페이 야마자키
마사히로 와쿠다
토시키 하마다
Original Assignee
가부시키가이샤 한도오따이 에네루기 켄큐쇼
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Publication of KR20240116754A publication Critical patent/KR20240116754A/ko
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H01L29/7869—
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H01L29/66969—
    • H01L29/78606—
    • H01L29/78696—
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    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
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    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional [2D] radiating surfaces
    • H05B33/14—Light sources with substantially two-dimensional [2D] radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material, or by the simultaneous addition of the electroluminescent material in or onto the light source
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    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
KR1020247020479A 2021-11-30 2022-11-17 반도체 장치, 반도체 장치의 제작 방법 Pending KR20240116754A (ko)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
JPJP-P-2021-194809 2021-11-30
JP2021194809 2021-11-30
JPJP-P-2022-030009 2022-02-28
JP2022030009 2022-02-28
JP2022080079 2022-05-16
JPJP-P-2022-080079 2022-05-16
PCT/IB2022/061054 WO2023100013A1 (ja) 2021-11-30 2022-11-17 半導体装置、半導体装置の作製方法

Publications (1)

Publication Number Publication Date
KR20240116754A true KR20240116754A (ko) 2024-07-30

Family

ID=86611604

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020247020479A Pending KR20240116754A (ko) 2021-11-30 2022-11-17 반도체 장치, 반도체 장치의 제작 방법

Country Status (5)

Country Link
US (1) US20250048676A1 (https=)
JP (1) JPWO2023100013A1 (https=)
KR (1) KR20240116754A (https=)
TW (1) TW202329333A (https=)
WO (1) WO2023100013A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12581747B2 (en) * 2022-06-20 2026-03-17 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
TWI871138B (zh) * 2023-12-18 2025-01-21 國立清華大學 半導體功率元件

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011151383A (ja) 2009-12-25 2011-08-04 Semiconductor Energy Lab Co Ltd 半導体装置
JP2012257187A (ja) 2010-08-06 2012-12-27 Semiconductor Energy Lab Co Ltd 半導体集積回路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102265405B (zh) * 2008-12-24 2015-09-23 3M创新有限公司 金属氧化物半导体薄膜晶体管中的稳定性增强
US10056497B2 (en) * 2015-04-15 2018-08-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US12142693B2 (en) * 2019-09-20 2024-11-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP7594550B2 (ja) * 2020-01-16 2024-12-04 株式会社半導体エネルギー研究所 半導体装置の作製方法
CN115244713A (zh) * 2020-03-31 2022-10-25 株式会社半导体能源研究所 半导体装置、半导体装置的制造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011151383A (ja) 2009-12-25 2011-08-04 Semiconductor Energy Lab Co Ltd 半導体装置
JP2012257187A (ja) 2010-08-06 2012-12-27 Semiconductor Energy Lab Co Ltd 半導体集積回路

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
S. Migita, et al, "Electrical Performances of Junctionless-FETs at the Scaling Limit(LCH=3nm)", IEDM Tech. Dig., pp.191-194, 2012.
S. Migita, et al, "Experimental Demonstration of Ultrashort-Channel(3nm) Junctionless FETs Utilizing Atomically Sharp V-Grooves on SOI", IEEE Trans. Nanotechnol., 13, pp.208-215, 2014.
S. Subhechha, et al, "First demonstration of sub-12nm Lg gate last IGZO-TFTs with oxygen tunnel architecture for front gate devices", Symposium on VLSI Technology Digest of Technical Papers, T10-5, 2021.

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JPWO2023100013A1 (https=) 2023-06-08
US20250048676A1 (en) 2025-02-06
TW202329333A (zh) 2023-07-16
WO2023100013A1 (ja) 2023-06-08

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P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000