KR20240102223A - Transparent display device - Google Patents

Abstract

A display device according to an embodiment of the present invention includes a substrate including a display area and a non-display area equipped with a plurality of pixels to display an image, a signal pad provided in the non-display area on the substrate, and a signal pad provided on the signal pad. A first insulating layer including a first opening area exposing at least a portion of the pad, a pad electrode provided on the first insulating layer and in contact with the signal pad exposed through the first opening area, and a pad electrode provided on the pad electrode and contacting the signal pad. and a second insulating layer including a second opening area exposing at least a portion of the electrode. The second opening area has a larger area than the first opening area.

Description

Display device {TRANSPARENT DISPLAY DEVICE}

The present invention relates to a display device.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Accordingly, recently, liquid crystal display (LCD), plasma display panel (PDP), quantum dot light emitting display (QLED), and organic light emitting display (OLED) have been developed. Various display devices such as Light Emitting Display (Light Emitting Display) are being used.

The display device may operate by receiving a driving signal from a flexible film provided with driving circuits. The display device is provided with a pad, and a flexible film is attached to the pad to transmit a driving signal to the pad. In the display device, if the pad is damaged or the flexible film is not well attached to the pad, a problem may occur in which the pad cannot receive a driving signal applied from the flexible film.

The technical problem of the present invention is to provide a display device that can prevent damage to the pad.

In addition, another technical problem of the present invention is to provide a display device that can ensure contact between a pad and a flexible film.

A display device according to an embodiment of the present invention includes a substrate including a display area and a non-display area equipped with a plurality of pixels to display an image, a signal pad provided in the non-display area on the substrate, and a signal pad provided on the signal pad. A first insulating layer including a first opening area exposing at least a portion of the pad, a pad electrode provided on the first insulating layer and in contact with the signal pad exposed through the first opening area, and a pad electrode provided on the pad electrode and contacting the signal pad. and a second insulating layer including a second opening area exposing at least a portion of the electrode. The second opening area has a larger area than the first opening area.

In the present invention, by providing a pad electrode on a signal pad, it is possible to block external oxygen or moisture, or an etchant used in the manufacturing process, from flowing into the second signal pad.

Additionally, in the present invention, the second opening area of the second insulating layer is formed to be wide, so that the pad electrode exposed through the second opening area can have a large area. Accordingly, the present invention can secure a wide contact area between the anisotropic conductive film of the flexible film and the pad electrode.

In addition, the present invention provides a convex portion on the pad electrode exposed through the second opening area of the second insulating layer, thereby increasing the contact area with the anisotropic conductive film of the flexible film and improving the adhesion of the flexible film with the anisotropic conductive film. It can be improved.

Additionally, in the present invention, the pad electrode covers the boundary between the second upper surface and the inclined surface of the first insulating layer, thereby preventing the etchant used in the manufacturing process from flowing into the signal pad through the seam of the first insulating layer.

In addition, the present invention covers the boundary between the pad electrode provided on the second upper surface of the first insulating layer and the pad electrode provided on the inclined surface of the first insulating layer, so that the etchant used in the manufacturing process is used in the core and the pad electrode. It is possible to prevent the material from flowing into the signal pad SP through the seam of the first insulating layer.

Additionally, in the present invention, since the second insulating layer is not provided on the first upper surface of the first insulating layer, the maximum step in the bonding area can be formed to be relatively small. Accordingly, the present invention facilitates contact between the pad electrode and the anisotropic conductive film of the flexible film, thereby reducing connection defects. Additionally, the present invention can expand the contact area between the pad electrode and the anisotropic conductive film of the flexible film and secure a sufficient bonding alignment margin.

Additionally, by providing a clad layer on the driving transistor, the present invention can block hydrogen particles from propagating to the driving transistor and further prevent electrodes of the driving transistor from being corroded. Accordingly, the present invention can prevent the threshold voltage of the driving transistor from shifting, thereby improving the operational reliability of the driving transistor. Furthermore, the present invention prevents the light-emitting device from being deteriorated by hydrogen by absorbing hydrogen generated inside the clad layer, and further, maintains high luminous efficiency even at low power and reduces power consumption. .

In addition, in the present invention, the signal pad can be formed of the same material on the same layer as any one of the active layer, gate electrode, source electrode, and drain electrode of the driving transistor, and the pad electrode can be formed of the same material on the same layer as the clad layer. there is.

The present invention can reduce production energy through process optimization. The effects that can be obtained from the present invention are not limited to the effects mentioned above, and other effects not mentioned can be found in the technical field to which the present invention belongs from the description below. It will be clearly understandable to those with ordinary knowledge.

1 is a perspective view schematically showing a display device according to an embodiment of the present invention.
Figure 2 is a plan view schematically showing a display panel according to an embodiment of the present invention.
FIG. 3 is a diagram schematically showing an embodiment of a pixel provided in area A of FIG. 2.
FIG. 4 is a diagram schematically showing an example of a pixel provided in a display panel.
FIG. 5 is a plan view showing an example of a plurality of pads provided in the pad area of FIG. 2.
Figure 6 is a cross-sectional view taken along line II-II' shown in the pad of Figure 5.
Figure 7 is a cross-sectional view showing a comparative example.

The advantages and features of the present specification and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below and will be implemented in various different forms, but the present embodiments only serve to ensure that the disclosure of the present specification is complete, and those with ordinary knowledge in the technical field to which the present specification pertains It is provided to fully inform the user of the scope of the invention.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining embodiments of the present specification are illustrative, and the present specification is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present specification, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present specification, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on the top', 'on the bottom', 'next to', etc., 'immediately' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

In the case of a description of a temporal relationship, for example, if a temporal relationship is described as 'after', 'successfully after', 'after', 'before', etc., 'immediately' or 'directly' Unless used, non-consecutive cases may also be included.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

The term 'at least one' should be understood to include all possible combinations from one or more related items. For example, ''at least one of the first item, the second item, and the third item'' means each of the first item, the second item, or the third item, as well as the first item, the second item, and the third item. It may mean a combination of all items that can be presented from two or more of them.

Each feature of the various embodiments of the present specification can be partially or entirely combined or combined with each other, various technological interconnections and operations are possible, and each embodiment may be implemented independently of each other or together in a related relationship. It may be possible.

Hereinafter, a preferred example of a display device according to the present invention will be described in detail with reference to the attached drawings. In adding reference numerals to components in each drawing, identical components may have the same reference numerals as much as possible even if they are shown in different drawings. Additionally, when describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

FIG. 1 is a perspective view schematically showing a display device according to an embodiment of the present invention, and FIG. 2 is a plan view schematically showing a display panel according to an embodiment of the present invention.

Hereinafter, the X-axis represents a direction parallel to the scan line, the Y-axis represents a direction parallel to the data line, and the Z-axis represents the height direction of the display device 100.

The display device 100 according to an embodiment of the present invention has been described with a focus on being implemented as an Organic Light Emitting Display, but it can also be implemented as a Liquid Crystal Display or a Plasma Display (PDP). Panel), Quantum dot Light Emitting Display (QLED), or electrophoresis display.

1 and 2, a display device 100 according to an embodiment of the present invention includes a display panel 110, a source drive integrated circuit (hereinafter referred to as “IC”) 210, and a flexible film. It includes 220, a circuit board 230, and a timing control unit 240.

The display panel 110 includes a first substrate 111 and a second substrate 112 facing each other. The second substrate 112 may be an encapsulation substrate. The first substrate 111 may be a plastic film, a glass substrate, or a silicon wafer substrate formed using a semiconductor process. The second substrate 112 may be a plastic film, a glass substrate, or an encapsulation film. The first substrate 111 and the second substrate 112 may be made of a transparent material.

The display panel 110 may be divided into a display area (DA) in which pixels are formed to display images, and a non-display area (NDA) in which images are not displayed.

The display area DA may be provided with first signal lines SL1, second signal lines SL2, and pixels, and the non-display area NDA may include a pad area PA where pads are arranged and at least one A scan driver 205 may be provided.

The first signal lines SL1 may extend in a first direction (eg, Y-axis direction) and intersect the second signal lines SL2 in the display area DA. The second signal lines SL2 may extend from the display area DA in a second direction (eg, X-axis direction). The pixels are provided in an area where the first signal line SL1 is provided or an area where the first signal line SL1 and the second signal line SL2 intersect, and display an image by emitting a predetermined amount of light.

The source drive IC 210 receives digital video data and source control signals from the timing control unit 240. The source drive IC 210 converts digital video data into analog data voltages according to the source control signal and supplies them to the data lines. When the source drive IC 210 is manufactured as a driving chip, it may be mounted on the flexible film 220 using a chip on film (COF) or chip on plastic (COP) method.

Wires connecting the pads and the source drive IC 210 and wires connecting the pads and the wires of the circuit board 230 may be formed in the flexible film 220. The flexible film 220 is attached to the pads using an anisotropic conducting film, so that the pads and the wires of the flexible film 220 can be connected.

The circuit board 230 may be attached to the flexible films 220. The circuit board 230 may be equipped with multiple circuits implemented with driving chips. For example, the timing control unit 240 may be mounted on the circuit board 230. The circuit board 150 may be a printed circuit board or a flexible printed circuit board.

The timing control unit 240 receives digital video data and timing signals from an external system board (not shown). The timing control unit 240 generates a gate control signal for controlling the operation timing of the scan driver and a source control signal for controlling the source drive ICs 210 based on the timing signal. The timing control unit 240 supplies a gate control signal to the scan driver 205 and a source control signal to the source drive ICs 210.

FIG. 3 is a diagram schematically showing an example of a pixel provided in area A of FIG. 2, and FIG. 4 is a cross-sectional view schematically showing an example along line II' of FIG. 3.

Referring to FIGS. 3 and 4 , the display panel 110 may be divided into a display area (DA) in which pixels are formed to display images, and a non-display area (NDA) in which images are not displayed.

As shown in FIG. 3, the display area DA includes a transmissive area (TA) and a non-transmissive area (NTA). The transmissive area (TA) is an area that passes through most of the light incident from the outside, and the non-transmissive area (NTA) is an area that does not transmit most of the light incident from the outside. For example, the transmissive area (TA) may be an area where the light transmittance is greater than α%, and the non-transmissive area (NTA) may be an area where the light transmittance is less than β%. At this time, α is a value greater than β. The transparent display panel 110 allows objects or background located on the back of the transparent display panel 110 to be visible due to the transmission areas (TA).

The non-transmissive area (NTA) may include a first non-transmissive area (NTA1), a second non-transmissive area (NTA2), and a pixel (P).

As shown in FIG. 3, the first non-transmissive area NTA1 extends in the first direction (e.g., Y-axis direction) from the display area DA, and is at least partially aligned with the light-emitting areas EA1, EA2, EA3, and EA4. They can be arranged to overlap. In the display panel 110, a plurality of first non-transmissive areas NTA1 are disposed to be spaced apart from each other, and a transmissive area TA may be provided between two adjacent first non-transmissive areas NTA1. In this first non-transmissive area NTA1, first signal lines SL1 extending in a first direction (eg, Y-axis direction) may be spaced apart from each other.

The first signal lines SL1 may include at least one of a common power line, a reference line, data lines, and a pixel power line.

The pixel power line may supply first power to the driving transistor T of each of the sub-pixels SP1, SP2, SP3, and SP4 provided in the display area DA. The common power line may supply second power to the cathode electrodes of the sub-pixels SP1, SP2, SP3, and SP4 provided in the display area DA. At this time, the second power source may be a common power supply commonly supplied to the sub-pixels SP1, SP2, SP3, and SP4.

The reference line may supply an initialization voltage (or reference voltage) to the driving transistor T of each of the sub-pixels SP1, SP2, SP3, and SP4 provided in the display area DA. Each of the data lines may supply a data voltage to the sub-pixels SP1, SP2, SP3, and SP4.

The display panel 110 according to an embodiment of the present invention is provided with a pixel (P) between adjacent transmissive areas (TA), and the pixel (P) is a light-emitting area (EA1) where a light-emitting element is disposed to emit light. EA2, EA3, EA4). Since the non-transmissive area NTA of the display panel 110 is small, the circuit elements may be arranged to overlap the emission areas EA1, EA2, EA3, and EA4.

As shown in FIG. 3, the second non-transmissive area NTA2 extends from the display area DA in the second direction (e.g., They can be arranged to overlap. The display panel 110 may have a plurality of second non-transmissive areas NTA2 spaced apart from each other, and a transmissive area TA may be provided between two adjacent second non-transmissive areas NTA2. A second signal line SL2 may be disposed in this second non-transmissive area NTA2.

The second signal line SL2 extends in a second direction (eg, X-axis direction) and may include, for example, a scan line SCANL. The scan line (SCANL) can supply a scan signal to the sub-pixels (SP1, SP2, SP3, and SP4) of the pixel (P).

Each of the pixels P may include a first sub-pixel (SP1), a second sub-pixel (SP2), a third sub-pixel (SP3), and a fourth sub-pixel (SP4) as shown in FIG. 3. . The first sub-pixel SP1 includes a first light-emitting area EA1 that emits light of a first color, and the second sub-pixel SP2 includes a second light-emitting area EA2 that emits light of a second color. can do. The third sub-pixel SP3 includes a third light-emitting area EA3 that emits third color light, and the fourth sub-pixel SP4 includes a fourth light-emitting area EA4 that emits fourth color light. can do.

For example, the first to fourth light emitting areas EA1, EA2, EA3, and EA4 may all emit light of different colors. For example, the first emission area EA1 may emit white light, and the second emission area EA2 may emit green light. The third emission area EA3 may emit red light, and the fourth emission area EA4 may emit blue light. However, it is not necessarily limited to this. Additionally, the arrangement order of each sub-pixel (SP1, SP2, SP3, SP4) can be changed in various ways.

As shown in FIG. 4, each of the plurality of sub-pixels (SP1, SP2, SP3, and SP4) may be provided with a driving transistor (T) and a light emitting device (OLED).

Specifically, an active layer (ACT) may be provided on the first substrate 111. The active layer (ACT) may be formed of a silicon-based semiconductor material or an oxide-based semiconductor material.

A light blocking layer (LS) may be provided between the active layer (ACT) and the first substrate 111 to block external light incident on the active layer (ACT). The light blocking layer (LS) may be made of a conductive material, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). ) and copper (Cu) or an alloy thereof may be formed as a single layer or multiple layers. In this case, a buffer layer 120 may be provided between the light blocking layer LS and the active layer ACT. The buffer layer 120 may extend to the non-display area (NDA) including the pad area (PA) as well as the display area (DA) including the non-transmissive area (NTA) and the transmissive area (TA).

A gate insulating layer 130 may be provided on the active layer (ACT). The gate insulating layer 130 may be formed of an inorganic film, for example, a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof.

A gate electrode (GE), a source electrode (SE), and a drain electrode (DE) may be provided on the gate insulating layer 130. The gate electrode (GE), source electrode (SE), and drain electrode (DE) of the driving transistor (DTR) may be formed of the same material on the same layer as shown in FIG. 4, but are not necessarily limited thereto. In another embodiment, the source electrode (SE) and drain electrode (DE) of the driving transistor (DTR) may be formed on a different layer from the gate electrode (GE) and of a different material.

The gate electrode (GE), source electrode (SE), and drain electrode (DE) are made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium ( It may be formed as a single layer or multiple layers made of any one of Nd) and copper (Cu) or an alloy thereof.

In one embodiment, the gate electrode GE may be made of a double layer including the first gate electrode GE1 and the second gate electrode GE2, as shown in FIG. 4. The first gate electrode GE1 is provided between the gate insulating layer 130 and the second gate electrode GE2 to improve adhesion between the gate insulating layer 130 and the second gate electrode GE2. Additionally, the first gate electrode GE1 protects the lower surface of the second gate electrode GE2, thereby preventing the second gate electrode GE2 from being corroded. The first gate electrode GE1 may be made of a material with a lower oxidation degree than the second gate electrode GE2. For example, the first gate electrode GE1 may be made of an alloy (MoTi) of molybdenum (Mo) and titanium (Ti), but is not necessarily limited thereto.

The second gate electrode GE2 may be provided on the first gate electrode GE1. The second gate electrode GE2 may be made of a metal with lower resistance than the first gate electrode GE1. For example, the second gate electrode GE2 may be made of copper (Cu), a metal with low resistance, but is not limited thereto. The second gate electrode GE2 may be formed thicker than the first gate electrode GE1 to reduce overall resistance.

In one embodiment, the source electrode SE may be made of a double layer including the first source electrode SE1 and the second source electrode SE2, as shown in FIG. 4. The first source electrode SE1 is provided between the first insulating layer 140 and the second source electrode SE2 to improve adhesion between the first insulating layer 140 and the second source electrode SE2. . Additionally, the first source electrode SE1 protects the lower surface of the second source electrode SE2, thereby preventing the second source electrode SE2 from being corroded. This first source electrode (SE1) may be made of a material with a lower oxidation degree than the second source electrode (SE2). As an example, the first source electrode SE1 may be made of an alloy (MoTi) of molybdenum (Mo) and titanium (Ti), but is not necessarily limited thereto.

The second source electrode SE2 may be provided on the first source electrode SE1. The second source electrode SE2 may be made of a metal with lower resistance than the first source electrode SE1. For example, the second source electrode SE2 may be made of copper (Cu), a metal with low resistance, but is not necessarily limited thereto. The second source electrode SE2 may be formed to be thicker than the first gate electrode GE1 to reduce overall resistance.

In one embodiment, the drain electrode DE may be made of a double layer including the first drain electrode DE1 and the second drain electrode DE2, as shown in FIG. 4. The first drain electrode DE1 is provided between the first insulating layer 140 and the second drain electrode DE2 to improve adhesion between the first insulating layer 140 and the second drain electrode DE2. . Additionally, the first drain electrode DE1 protects the lower surface of the second drain electrode DE2, thereby preventing the second drain electrode DE2 from being corroded. The first drain electrode DE1 may be made of a material with a lower oxidation degree than the second drain electrode DE2. As an example, the first drain electrode DE1 may be made of an alloy (MoTi) of molybdenum (Mo) and titanium (Ti), but is not necessarily limited thereto.

The second drain electrode DE2 may be provided on the first drain electrode DE1. The second drain electrode DE2 may be made of a metal with lower resistance than the first drain electrode DE1. For example, the second drain electrode DE2 may be made of copper (Cu), a metal with low resistance, but is not limited thereto. The second drain electrode DE2 may be formed thicker than the first drain electrode DE1 to reduce overall resistance.

A first insulating layer 140 may be provided on the gate electrode (GE), source electrode (SE), and drain electrode (DE). The first insulating layer 140 may be formed of an inorganic layer, for example, a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof. The first insulating layer 140 may extend to the non-display area (NDA) including the pad area (PA) as well as the display area (DA) including the non-transmissive area (NTA) and the transmissive area (TA).

A clad layer (CD) may be provided on the first insulating layer 140.

In one embodiment, the clad layer (CD) may be made of a material that has excellent properties for absorbing hydrogen particles. Additionally, the clad layer (CD) may be made of a material with a lower oxidation degree than the gate electrode (GE), source electrode (SE), and drain electrode (DE). For example, the clad layer (CD) may be made of an alloy (MoTi) of molybdenum (Mo) and titanium (Ti), but is not necessarily limited thereto.

The clad layer (CD) is provided to overlap at least a portion of the gate electrode (GE), source electrode (SE), and drain electrode (DE), and overlaps the gate electrode (GE), source electrode (SE), and drain electrode (DE). It can be protected. The clad layer (CD) absorbs hydrogen particles and blocks the hydrogen particles from propagating to the gate electrode (GE), source electrode (SE), and drain electrode (DE). ) and drain electrode (DE) can be prevented from corrosion. Accordingly, the display panel 110 according to an embodiment of the present invention can prevent the threshold voltage of the driving transistor T from shifting, thereby improving the operational reliability of the driving transistor T.

In addition, the display panel 110 according to an embodiment of the present invention prevents the light emitting device (OLED) from being deteriorated by hydrogen by absorbing hydrogen generated inside the clad layer (CD), and furthermore, operates at low power. High luminous efficiency can be maintained and power consumption can be reduced.

A second insulating layer 150 may be provided on the clad layer (CD) to protect the driving transistor (T) and the clad layer (CD). The second insulating layer 150 may be formed of an inorganic film, for example, a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof. The second insulating layer 150 may extend not only to the display area DA but also to the non-display area NDA including the pad area PA.

A flattening layer 160 may be provided on the second insulating layer 150 to flatten the step caused by the driving transistor (T). The planarization layer 160 may be formed of an organic film such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. there is.

On the planarization layer 160, light emitting elements (OLED) consisting of a first electrode (E1), an organic light emitting layer (EL), and a second electrode (E2) and a bank 170 are provided.

The first electrode E1 may be provided on the planarization layer 160 and electrically connected to the driving transistor T. Specifically, the first electrode E1 is the source of the driving transistor T through the second contact hole CH2 penetrating the planarization layer 160, the first insulating layer 140, and the second insulating layer 150. It may be connected to the electrode (SE) or the drain electrode (DE). This first electrode E1 may be provided for each sub-pixel.

The first electrode (E1) has a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), an Ag alloy, and a stacked structure of Ag alloy and ITO ( It can be formed of a highly reflective metal material such as ITO/Ag alloy/ITO), MoTi alloy, and a laminated structure of MoTi alloy and ITO (ITO/MoTi alloy/ITO). The Ag alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu). MoTi alloy may be an alloy of molybdenum (Mo) and titanium (Ti).

Meanwhile, the first electrode E1 may be made of a conductive material that can transmit light in the lower light-emitting structure. As an example, the second electrode 140 is made of a transparent conductive material (TCO) such as ITO or IZO, magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). It can be formed of the same semi-transmissive conductive material. This first electrode (E1) may be an anode electrode of a light emitting device.

The bank 170 may be provided on the planarization layer 160. Additionally, the bank 170 may be provided between the first electrodes E1 provided in each of the plurality of sub-pixels. Additionally, the bank 170 may be formed to cover an edge of each of the first electrodes E1 and expose a portion of each of the first electrodes E1. Accordingly, the bank 170 can prevent the problem of decreasing luminous efficiency due to current concentration at the ends of each of the first electrodes E1.

Meanwhile, the bank 170 may define an emission area (EA) of each sub-pixel. The light emitting area (EA) of each sub-pixel is formed by sequentially stacking a first electrode (E1), an organic light emitting layer (EL), and a second electrode (E2), so that holes from the first electrode (E1) and a second electrode (E2) are formed. It represents a region where electrons from (E2) combine with each other in the organic light emitting layer (EL) to emit light. In this case, the area where the bank 170 is formed does not emit light and thus becomes a non-emission area, and the area where the bank 170 is not formed and the first electrodes E1 are exposed may become the light emitting area EA. .

The bank 170 may be formed of an organic film such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. .

The organic light emitting layer (EL) may be provided on the first electrode (E1). The organic light emitting layer El may include a hole transporting layer, a light emitting layer, and an electron transporting layer. In this case, when voltage is applied to the first electrode (E1) and the second electrode (E2), holes and electrons move to the light-emitting layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the light-emitting layer to emit light.

In one embodiment, the organic light emitting layer EL may be a common layer commonly formed in sub-pixels. At this time, the light emitting layer may be a white light emitting layer that emits white light.

In another embodiment, the organic light emitting layer EL may be formed for each sub-pixel. For example, a red light-emitting layer emitting red light is formed in the red sub-pixel, a green light-emitting layer emitting green light is formed in the green sub-pixel, a blue light-emitting layer emitting blue light is formed in the blue sub-pixel, and a white light-emitting layer is formed in the white sub-pixel. A white light emitting layer that emits white light may be formed in the pixel.

The second electrode E2 may be provided on the organic light emitting layer EL and the bank 170. The second electrode E2 may be a common layer that is commonly formed in the sub-pixels and applies the same voltage.

The second electrode E2 may be made of a conductive material capable of transmitting light in the upper light-emitting structure. For example, the second electrode E2 is made of a transparent conductive material (TCO) such as ITO or IZO, magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). It can be formed of the same semi-transmissive conductive material.

Meanwhile, the second electrode (E2) has a stacked structure of aluminum and titanium (Ti/Al/Ti), a stacked structure of aluminum and ITO (ITO/Al/ITO), an Ag alloy, and a stacked structure of Ag alloy and ITO in the lower light emitting structure. It can be formed of a highly reflective metal material, such as a structure (ITO/Ag alloy/ITO), a MoTi alloy, and a laminated structure of MoTi alloy and ITO (ITO/MoTi alloy/ITO). The Ag alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu). MoTi alloy may be an alloy of molybdenum (Mo) and titanium (Ti). This second electrode E2 may be a cathode electrode.

An encapsulation layer 180 may be provided on the light emitting devices (OLED). The encapsulation layer 180 may be formed on the second electrode E2 to cover the second electrode E2. The encapsulation layer 180 serves to prevent oxygen or moisture from penetrating into the organic light emitting layer (EL) and the second electrode (E2). To this end, the encapsulation layer 180 may include at least one inorganic layer and at least one organic layer.

Meanwhile, although not shown in FIG. 4, a capping layer may be additionally formed between the second electrode E2 and the encapsulation layer 180.

A color filter (not shown) may be provided on the encapsulation layer 180. The color filter may be provided on one side of the second substrate 112 facing the first substrate 111. In this case, the first substrate 111 provided with the encapsulation layer 180 and the second substrate 112 provided with the color filter may be bonded by a separate adhesive layer (not shown). At this time, the adhesive layer may be a transparent adhesive resin layer (optically clear resin layer, OCR) or a transparent adhesive resin film (optically clear adhesive film, OCA).

Referring again to FIG. 2 , the non-display area NDA may be provided with a pad area PA and at least one scan driver 205.

The scan driver 205 is connected to the scan line and supplies scan signals. This scan driver 205 may be formed in the non-display area (NDA) outside one or both sides of the display area (DA) of the display panel 110 using a gate driver in panel (GIP) method. Alternatively, the scan driving unit 205 is manufactured as a driving chip, mounted on a flexible film, and formed in a non-display area (NDA) outside one or both sides of the display area (DA) of the display panel 110 using a TAB (tape automated bonding) method. It may be attached to .

As an example, the scan driver 205 is connected to the first gate driver 205 and the display area DA formed in the non-display area NDA outside the first side of the display area DA, as shown in FIG. It may include a second gate driver 205 formed in the non-display area NDA outside the second side facing the first side, but is not necessarily limited thereto.

A plurality of pads may be disposed in the pad area PA. Since the size of the first substrate 111 is larger than that of the second substrate 112, a portion of the first substrate 111 may be exposed without being covered by the second substrate 112. A portion of the first substrate 111 that is exposed and not covered by the second substrate 112 may be provided with pads such as power pads and data pads.

The plurality of pads include power pads, data pads, etc., and a flexible film 220 may be attached to the upper portion through a film attachment process. The flexible film 220 is attached to the pads using an anisotropic conducting film, so that the pads and the wires of the flexible film 220 can be connected.

Hereinafter, a pad according to an embodiment of the present invention will be described in detail with reference to FIGS. 5 to 7.

FIG. 5 is a plan view showing an example of a plurality of pads provided in the pad area of FIG. 2, FIG. 6 is a cross-sectional view taken along line II-II′ shown in the pad of FIG. 5, and FIG. 7 is a cross-sectional view showing a comparative example. .

Referring to FIGS. 5 and 6 , the pad area PA is provided in the non-display area NDA. The pad area (PA) is for electrically connecting the display panel 110 and the driving chips provided on the flexible film 220 or the circuit board 230, and is provided in the area where the flexible film 220 is bonded. It can be.

A plurality of pads (PAD) may be provided in the pad area (PA). The plurality of pads PAD may be formed to be long in a second direction (eg, Y-axis direction) and may be spaced apart from each other in a first direction (eg, X-axis direction). Each of the plurality of pads (PAD) may be connected to at least one of the plurality of signal lines provided in the display area (DA). Each of the plurality of signal lines extends from the display area DA to the non-display area NDA and may be electrically connected to one of the plurality of pads PAD provided in the pad area PA.

Each of the plurality of pads (PAD) includes a signal pad (SP) and a pad electrode (PE) as shown in FIG. 6.

The signal pad SP may be provided in the pad area PA on the first substrate 111. In one embodiment, the signal pad SP may be provided on the buffer layer 120. That is, the buffer layer 120 may be provided between the signal pad SP and the first substrate 111. The buffer layer 120 may be formed to extend not only to the display area DA but also to the non-display area NDA including the pad area PA. The buffer layer 120 provided in the pad area PA may block moisture or impurities penetrating through the first substrate 111 from moving to the signal pad SP.

In one embodiment, the signal pad SP may be provided on the gate insulating layer 130. That is, the gate insulating layer 130 is provided between the signal pad (SP) and the buffer layer 120, so that moisture or impurities penetrating through the first substrate 111 together with the buffer layer 120 move to the signal pad (SP). You can block it from doing so. At this time, the gate insulating layer 130 may be patterned only in the area where the signal pad SP is formed.

The signal pad (SP) and the gate electrode (GE) are made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). ) may be formed as a single layer or multiple layers made of any one or an alloy thereof.

In one embodiment, the signal pad SP may be made of a double layer including the first signal pad SP1 and the second signal pad SP2, as shown in FIG. 6. The first signal pad SP1 is provided between the gate insulating layer 130 and the second signal pad SP2 to improve adhesion between the gate insulating layer 130 and the second signal pad SP2. Additionally, the first signal pad SP1 protects the lower surface of the second signal pad SP2, thereby preventing the second signal pad SP2 from being corroded. The first signal pad SP1 may be made of a material with a lower oxidation degree than the second signal pad SP2. As an example, the first signal pad SP1 may be made of an alloy (MoTi) of molybdenum (Mo) and titanium (Ti), but is not necessarily limited thereto.

The second signal pad SP2 may be provided on the first signal pad SP1. The second signal pad SP2 may be made of a metal with lower resistance than the first signal pad SP1. For example, the second signal pad SP2 may be made of copper (Cu), a metal with low resistance, but is not necessarily limited thereto. The second signal pad SP2 may be formed to be thicker than the first signal pad SP1 to reduce overall resistance.

In one embodiment, the signal pad SP may be formed of the same material on the same layer as the gate electrode GE, source electrode SE, and drain electrode DE of the driving transistor T. Specifically, the first signal pad SP1 may be formed of the same material on the same layer as the first gate electrode GE1, first source electrode SE1, and first drain electrode DE1 of the driving transistor T. there is. The second signal pad SP2 may be formed of the same material on the same layer as the second gate electrode GE2, second source electrode SE2, and second drain electrode DE2 of the driving transistor T. The display panel 110 according to an embodiment of the present invention can reduce production energy through process optimization.

A first insulating layer 140 may be provided on the signal pad SP. The first insulating layer 140 may be formed to extend not only to the display area DA but also to the non-display area NDA including the pad area PA.

The first insulating layer 140 may include a first opening area OA1 exposing at least a portion of the signal pad SP. At least a portion of the top surface of the signal pad SP is exposed in the first opening area OA1, and the area excluding the first opening area OA1 may be covered by the first insulating layer 140.

The first insulating layer 140 is provided to overlap the signal pad SP in the area excluding the first opening area OA1 and the area exposed by the first opening area OA1 of the signal pad SP. It may include a first overlapping area (OVA1) and a first non-overlapping area (NOVA1) that does not overlap the signal pad (SP).

The first insulating layer 140 includes a first upper surface (S1) provided in the first overlapping area (OVA1), a second upper surface (S2) and a first upper surface (S1) provided in the first non-overlapping area (NOVA1). It may include a third upper surface (S3) connecting the second upper surface (S2). At this time, the first upper surface S1 may be a flat surface formed along the upper surface of the signal pad SP, and the second upper surface S2 may be a flat surface formed flat along the upper surface of the first insulating layer 120. . The third upper surface S3 may be an inclined surface formed to be inclined along the side of the signal pad SP.

Additionally, the first insulating layer 140 may further include a side surface S4 exposed by the first opening area OA1. The first insulating layer 140 may be provided with a convex surface consisting of a side surface (S4), a first top surface (S1), and a third top surface (S3). The first insulating layer 140 may be provided with convex surfaces on both sides with the first opening area OA1 in between.

The pad electrode (PE) may be provided on the first insulating layer 140 and the signal pad (SP). Specifically, the pad electrode PE may be provided on the signal pad SP exposed by the first opening area OA1. The pad electrode PE may be electrically connected to the signal pad SP by contacting the signal pad SP exposed by the first opening area OA1.

The pad electrode PE may be provided on the first insulating layer 140 in an area excluding the first opening area OA1. The pad electrode PEA may extend along the side surface S4 of the first insulating layer 140 exposed in the first opening area OA1 to the first upper surface S1 of the first insulating layer 140 . Additionally, the pad electrode PE may extend to the inclined surface S3 and the second upper surface S2. That is, the pad electrode PE may overlap the first opening area OA1 and the first overlapping area OVA1 of the first insulating layer 140 as well as at least a portion of the first non-overlapping area NOVA1.

This pad electrode PE may include a first flat portion FS1, a convex portion CS, and a second flat portion FS2. The first flat portion FS1 may include a flat surface formed along the upper surface of the signal pad SP in the first opening area OA1 of the first insulating layer 140 . The second flat portion FS2 may include a flat surface formed along the upper surface of the first insulating layer 140 in the first non-overlapping area NOVA1 of the first insulating layer 140 . The convex portion CS is disposed between the first flat portion FS1 and the second flat portion FS2, and is located on the side surface S4 of the first insulating layer 140 exposed in the first opening area OA1. 1 The insulating layer 140 may include a convex surface formed convexly by the first upper surface S1 and the inclined surface S3.

The pad electrode (PE) and the gate electrode (GE) are made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). ) may be formed as a single layer or multiple layers made of any one or an alloy thereof.

In one embodiment, the pad electrode PE may be made of a single layer as shown in FIG. 6. The pad electrode PE protects the top surface of the second signal pad SP2, thereby preventing the second signal pad SP2 from being damaged by external factors. The pad electrode (PE) can block external oxygen, moisture, or etchant used in the manufacturing process from flowing into the second signal pad (SP2). This pad electrode (PE) may be made of a material with a lower oxidation degree than the second signal pad (SP2). For example, the pad electrode (PE) may be made of an alloy (MoTi) of molybdenum (Mo) and titanium (Ti), but is not necessarily limited thereto.

In one embodiment, the pad electrode PE may be on the same layer as the clad layer CD and may be made of the same material. Specifically, the pad electrode (PE) may be on the same layer as the clad layer (CD) and may be made of the same material. The display panel 110 according to an embodiment of the present invention can reduce production energy through process optimization.

A second insulating layer 150 may be provided on the pad electrode (PE). The second insulating layer 150 may be formed to extend not only to the display area DA but also to the non-display area NDA including the pad area PA.

The second insulating layer 150 may include a second opening area OA2 exposing at least a portion of the pad electrode PE. At least a portion of the top surface of the pad electrode PE is exposed in the second opening area OA2, and the area excluding the second opening area OA2 may be covered by the second insulating layer 150.

The second opening area OA2 may have a larger width than the first opening area OA1. The first opening area OA1 may have a first width W1, and the second opening area OA1 may have a second width W2 that is larger than the first width W1. At this time, the first opening area OA1 may be disposed within the second opening area OA2. This second opening area (OA2) may have a larger area than the first opening area (OA1).

That is, the pad electrode PE exposed by the second opening area OA2 may have a larger width than the signal pad SP exposed by the first opening area OA1. The signal pad (SP) exposed by the first opening area (OA1) has a first width (W1), and the pad electrode (PE) exposed by the second opening area (OA2) has a first width (W1). It may have a large second width W2. The pad electrode PE exposed by the second opening area OA2 may have a larger area than the signal pad SP exposed by the first opening area OA1.

Meanwhile, the second opening area OA2 may overlap the first overlapping area OVA1 of the first insulating layer 140 . The first overlapping area OVA1 of the first insulating layer 140 may be disposed within the second opening area OA2.

That is, the pad electrode PE exposed by the second opening area OA2 may have a larger width than the signal pad SP. The signal pad SP has a third width W3, and the pad electrode PE exposed by the second opening area OA2 may have a second width W2 that is larger than the third width W3. . The pad electrode PE exposed by the second opening area OA2 may have a larger area than the signal pad SP.

Furthermore, the pad electrode PE may have a width greater than that of the signal pad SP. The pad electrode PE may have a fourth width W4 that is larger than the third width W3. The pad electrode (PE) may have a larger area than the signal pad (SP).

The second insulating layer 150 may be provided to cover the boundary between the second upper surface S2 and the third upper surface S3 of the first insulating layer 140. In one embodiment, the second insulating layer 150 may be provided on at least a portion of the second upper surface S2 and the third upper surface S3 of the first insulating layer 140. On the other hand, the second insulating layer 150 may not be provided on the first upper surface (S1) of the first insulating layer 140.

Accordingly, the maximum step (MS) in the bonding area (BA) where the flexible film is bonded is greater than the sum of the thickness (t1) of the first insulating layer 140 and the thickness (t2) of the second insulating layer 150. It can be small. The bonding area BA may correspond to the second opening area OA2 of the second insulating layer 150 where the pad electrode PE is exposed to the outside, but is not necessarily limited thereto. The bonding area BA may have a larger width than the second opening area OA to reflect process errors. The maximum step MS in the bonding area BA may represent the difference between a configuration provided at the maximum height and a configuration provided at the minimum height within the bonding area BA.

Since the second insulating layer 150 according to an embodiment of the present invention is not provided on the first upper surface S1 of the first insulating layer 140, the maximum height within the bonding area BA is the first insulating layer 140. ) may be the height of the upper surface of the pad electrode (PE) provided on the first upper surface (S1). Additionally, the minimum height within the bonding area BA may be the height of the top surface of the pad electrode PE provided on the signal pad SP exposed by the first opening area OA1. Accordingly, the maximum step MS in the bonding area BA is determined by the upper surface of the pad electrode PE provided on the first upper surface S1 of the first insulating layer 140 and the first opening area OA1. It may represent a difference between the upper surfaces of the pad electrodes (PE) provided on the exposed signal pad (SP).

Additionally, the step between the second insulating layer 150 and the pad electrode PE may be smaller than the sum of the thickness t1 of the first insulating layer 140 and the thickness t2 of the second insulating layer 150. . The upper surface of the pad electrode PE provided in the first opening area OA1 may have a first separation distance d1 perpendicular to the first substrate 111 . The second insulating layer 150 includes a second overlapping area OVA2 that overlaps at least a portion of the pad electrode PE, and the upper surface of the second insulating layer 150 provided in the second overlapping area OVA2 is It may have a second separation distance d2 perpendicular to the first substrate 111 . The difference between the first distance d1 and the second distance d2 may be smaller than the sum of the thickness t1 of the first insulating layer 140 and the thickness t2 of the second insulating layer 150.

The display panel 110 according to an embodiment of the present invention is provided with a pad electrode (PE) on the signal pad (SP), so that external oxygen or moisture, or an etchant used in the manufacturing process, is prevented from entering the second signal pad (SP2). ) can be blocked from entering.

In addition, the display panel 110 according to an embodiment of the present invention forms the second opening area OA2 of the second insulating layer 150 to be wide, so that the pad electrode exposed through the second opening area OA2 PE) can have a large area. Accordingly, the display panel 110 according to an embodiment of the present invention can secure a large contact area with the anisotropic conductive film of the flexible film.

In addition, the display panel 110 according to an embodiment of the present invention is provided with a convex portion (CS) on the pad electrode (PE), and the convex portion (CS) of the pad electrode (PE) is connected to the second insulating layer 150. It may be exposed through the second opening area OA2. The display panel 110 according to an embodiment of the present invention has the pad electrode PE forming convex portions CS on both sides with the first flat portion FS1 in between, so that the pad electrode PE forms a convex portion CS1 on both sides of the anisotropic conductive film of the flexible film. By increasing the contact area and improving the adhesion of the flexible film to the anisotropic conductive film, defects in which the flexible film comes off can be reduced.

Additionally, in the display panel 110 according to an embodiment of the present invention, the pad electrode PE may cover the boundary between the second upper surface S2 and the inclined surface S3 of the first insulating layer 140. The pad electrode PE extends to the first upper surface S1 of the first insulating layer 140 along the side surface S4 of the first insulating layer 140 exposed in the first opening area OA1, and has an inclined surface ( S3) and may extend to the second upper surface (S2).

A seam may occur in the first insulating layer 140 due to a step at the boundary between the second upper surface S2 and the inclined surface S3. The display panel 110 according to an embodiment of the present invention is used in the manufacturing process by having a pad electrode (PE) covering the boundary between the second upper surface (S2) and the inclined surface (S3) of the first insulating layer 140. It is possible to prevent the etchant from flowing into the signal pad SP through the seam of the first insulating layer 140.

In addition, the display panel 110 according to an embodiment of the present invention may include a second insulating layer 150 provided on the boundary between the second upper surface S2 and the inclined surface S3 of the first insulating layer 140. there is. That is, the second insulating layer 150 according to the present invention includes a pad electrode (PE) provided on the second upper surface (S2) of the first insulating layer 140 and an inclined surface (S3) of the first insulating layer 140. The boundary of the pad electrode (PE) provided on the surface may be covered. In one embodiment, the second insulating layer 150 may be provided on at least a portion of the second upper surface S2 and the inclined surface S3 of the first insulating layer 140.

A seam may occur in the pad electrode PE due to a step at the boundary between the second upper surface S2 and the inclined surface S3 of the first insulating layer 140. The display panel 110 according to an embodiment of the present invention includes a pad electrode (PE) provided on the second upper surface (S2) of the first insulating layer 140 and an inclined surface (S3) of the first insulating layer 140. By covering the boundary of the pad electrode (PE) provided on the surface, the etchant used in the manufacturing process is prevented from flowing into the signal pad (SP) through the seam of the pad electrode (PE) and the seam of the first insulating layer 140. can do.

Additionally, the display panel 110 according to an embodiment of the present invention may not include the second insulating layer 150 on the first upper surface S1 of the first insulating layer 140 . Accordingly, the maximum step (MS) in the bonding area (BA) where the flexible film is bonded is greater than the sum of the thickness (t1) of the first insulating layer 140 and the thickness (t2) of the second insulating layer 150. It can be small.

On the other hand, when the second insulating layer 150 is provided on the first upper surface (S1) of the first insulating layer 140 as shown in FIG. 7, the maximum step (BA) in the bonding area (BA) where the flexible film is bonded MS) may be equal to the sum of the thickness t1 of the first insulating layer 140 and the thickness t2 of the second insulating layer 150.

Since the pad area (PA) shown in FIG. 7 has a relatively large maximum step (MS) in the bonding area (BA), contact between the anisotropic conductive film of the flexible film and the pad electrode (PE) is easy when bonding the flexible film. don't do it Furthermore, because the anisotropic conductive film of the flexible film and the pad electrode (PE) are not completely adhered to each other, the flexible film may easily be separated from the pad electrode (PE). Additionally, the pad electrode PE in FIG. 7 has a smaller exposed area compared to the pad electrode PE shown in FIG. 6. When bonding flexible films, the contact area is small.

On the other hand, in the display panel 110 according to an embodiment of the present invention, the second insulating layer 150 is not provided on the first upper surface S1 of the first insulating layer 140, so that the bonding area BA The maximum step (MS) in is formed to be relatively small, and the exposed area of the pad electrode (PE) can be increased. Accordingly, the display panel 110 according to an embodiment of the present invention facilitates contact between the pad electrode (PE) and the anisotropic conductive film of the flexible film, thereby reducing connection defects. Additionally, the display panel 110 according to an embodiment of the present invention can expand the contact area between the pad electrode (PE) and the anisotropic conductive film of the flexible film and secure a sufficient bonding alignment margin.

Although embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made without departing from the spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of the present invention should be interpreted in accordance with the claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

100: display device 110: display panel
111: first substrate 112: second substrate
120: buffer layer 130: gate insulating layer
140: first insulating layer 150: second insulating layer
E1: First electrode EL: Organic light emitting layer
E2: Second electrode 180: Encapsulation film
SP: Signal pad PE: Pad electrode

Claims (15)

A substrate including a display area and a non-display area provided with a plurality of pixels to display an image;
a signal pad provided in the non-display area on the substrate;
a first insulating layer provided on the signal pad and including a first opening area exposing at least a portion of the signal pad;
a pad electrode provided on the first insulating layer and in contact with a signal pad exposed through the first opening area; and
A second insulating layer provided on the pad electrode and including a second opening area exposing at least a portion of the pad electrode,
The second opening area has a larger area than the first opening area. According to paragraph 1,
The display device wherein the first opening area is disposed within the second opening area. According to paragraph 1,
The first insulating layer includes a first overlapping area that overlaps at least a portion of the signal pad and a first non-overlapping area that does not overlap the signal pad,
A first overlapping area of the first insulating layer is disposed within the second opening area. According to paragraph 3,
The first insulating layer includes a first upper surface provided in the first overlapping area, a second upper surface provided in the first non-overlapping area, and an inclined surface connecting the first upper surface and the second upper surface,
The second insulating layer is provided on a boundary between the second upper surface and the inclined surface of the first insulating layer. According to paragraph 4,
The second insulating layer is provided on at least a portion of the second upper surface and the inclined surface of the first insulating layer. According to paragraph 1,
A display device wherein the pad electrode is provided with a width greater than the signal pad. According to paragraph 1,
A display device in which an area of the pad electrode exposed by the second opening area is larger than an area of the signal pad. According to paragraph 1,
The second insulating layer includes a second overlapping area overlapping at least a portion of the pad electrode,
The upper surface of the pad electrode provided in the first opening area has a first separation distance perpendicular to the substrate, and the upper surface of the second insulating layer provided in the second overlapping area has a second separation distance perpendicular to the substrate. have,
A difference between the first distance and the second distance is less than the sum of the thicknesses of the first and second insulating layers. According to paragraph 1,
Further comprising a flexible film bonded on the pad electrode exposed in the second opening area,
A display device in which the maximum step in the bonding area where the flexible film is bonded is smaller than the sum of the thicknesses of the first insulating layer and the second insulating layer. According to paragraph 1,
The pad electrode exposed by the second opening region includes a flat portion formed in the first opening region and a convex portion formed to be convex from a side of the first insulating layer exposed in the first opening region to an upper surface. According to paragraph 1,
a buffer layer provided between the substrate and the signal pad; and
The display device further includes a gate insulating layer provided between the buffer layer and the signal pad. According to clause 11,
A display device in which the gate insulating layer is patterned to overlap the signal pad. According to paragraph 1,
Each of the plurality of pixels includes a driving transistor including the active layer, a gate electrode, a source electrode, and a drain electrode,
The gate electrode, source electrode, and drain electrode of the driving transistor are spaced apart from each other on the same layer,
The signal pad is formed on the same layer and made of the same material as the gate electrode, source electrode, and drain electrode of the driving transistor. According to clause 13,
It further includes a clad layer provided on the driving transistor and made of a material that absorbs hydrogen particles,
A display device in which the pad electrode is formed of the same material on the same layer as the clad layer. According to paragraph 1,
The signal pad includes a lower signal pad and an upper signal pad provided on the lower signal pad,
The display device wherein the pad electrode is made of the same material as the lower signal pad.

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