KR20240088958A - 의사 채널 기반 메모리 시스템의 레이턴시 감소 - Google Patents

의사 채널 기반 메모리 시스템의 레이턴시 감소 Download PDF

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Publication number
KR20240088958A
KR20240088958A KR1020247013125A KR20247013125A KR20240088958A KR 20240088958 A KR20240088958 A KR 20240088958A KR 1020247013125 A KR1020247013125 A KR 1020247013125A KR 20247013125 A KR20247013125 A KR 20247013125A KR 20240088958 A KR20240088958 A KR 20240088958A
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KR
South Korea
Prior art keywords
pseudo
channel
data bus
memory access
channel selection
Prior art date
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Pending
Application number
KR1020247013125A
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English (en)
Korean (ko)
Inventor
시얌쿠마르 토지요르
판카즈 데쉬무크
정원 서
수바라오 팔라차를라
Original Assignee
퀄컴 인코포레이티드
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Publication of KR20240088958A publication Critical patent/KR20240088958A/ko
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0635—Configuration or reconfiguration of storage systems by changing the path, e.g. traffic rerouting, path reconfiguration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0022—Multibus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Bus Control (AREA)
  • Dram (AREA)
  • Memory System (AREA)
KR1020247013125A 2021-10-28 2022-10-03 의사 채널 기반 메모리 시스템의 레이턴시 감소 Pending KR20240088958A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/452,606 US11893240B2 (en) 2021-10-28 2021-10-28 Reducing latency in pseudo channel based memory systems
US17/452,606 2021-10-28
PCT/US2022/045561 WO2023075993A1 (en) 2021-10-28 2022-10-03 Reducing latency in pseudo channel based memory systems

Publications (1)

Publication Number Publication Date
KR20240088958A true KR20240088958A (ko) 2024-06-20

Family

ID=84246003

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020247013125A Pending KR20240088958A (ko) 2021-10-28 2022-10-03 의사 채널 기반 메모리 시스템의 레이턴시 감소

Country Status (7)

Country Link
US (3) US11893240B2 (https=)
EP (1) EP4423618A1 (https=)
JP (1) JP2024542933A (https=)
KR (1) KR20240088958A (https=)
CN (1) CN118056195A (https=)
TW (1) TW202321896A (https=)
WO (1) WO2023075993A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11893240B2 (en) 2021-10-28 2024-02-06 Qualcomm Incorporated Reducing latency in pseudo channel based memory systems
US12147713B2 (en) * 2022-08-09 2024-11-19 Innosilicon Microelectronics (Zhuhai) Co., Ltd. High-bandwidth DDR DIMM, memory system, and operation method thereof
US20250061070A1 (en) * 2023-08-14 2025-02-20 Micron Technology, Inc. Memory device with a die having multiple pseudo channels per channel

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7269709B2 (en) * 2002-05-15 2007-09-11 Broadcom Corporation Memory controller configurable to allow bandwidth/latency tradeoff
DE10339787B4 (de) 2003-08-28 2005-11-03 Infineon Technologies Ag Speichermodul
US7263566B2 (en) * 2004-12-30 2007-08-28 Qualcomm Incorporated Method and apparatus of reducing transfer latency in an SOC interconnect
US8164936B2 (en) 2009-10-14 2012-04-24 Seagate Technology Llc Switched memory devices
US8819309B1 (en) * 2013-06-14 2014-08-26 Arm Limited Low latency bypass buffer
US9430434B2 (en) * 2013-09-20 2016-08-30 Qualcomm Incorporated System and method for conserving memory power using dynamic memory I/O resizing
KR20160076195A (ko) 2014-12-22 2016-06-30 에스케이하이닉스 주식회사 다수의 채널로 동작할 수 있는 적층 반도체 장치
US10402110B2 (en) * 2016-08-04 2019-09-03 Rambus Inc. Adjustable access energy and access latency memory system and devices
KR102395463B1 (ko) 2017-09-27 2022-05-09 삼성전자주식회사 적층형 메모리 장치, 이를 포함하는 시스템 및 그 동작 방법
US10546628B2 (en) * 2018-01-03 2020-01-28 International Business Machines Corporation Using dual channel memory as single channel memory with spares
US20190294548A1 (en) * 2018-03-21 2019-09-26 Macom Technology Solutions Holdings, Inc. Prefetch module for high throughput memory transfers
US10884958B2 (en) * 2018-06-25 2021-01-05 Intel Corporation DIMM for a high bandwidth memory channel
US10770129B2 (en) 2018-08-21 2020-09-08 Intel Corporation Pseudo-channeled DRAM
US10937518B2 (en) 2018-12-12 2021-03-02 Micron Technology, Inc. Multiple algorithmic pattern generator testing of a memory device
US11194726B2 (en) 2019-02-25 2021-12-07 Micron Technology, Inc. Stacked memory dice for combined access operations
US11308017B2 (en) * 2019-05-31 2022-04-19 Micron Technology, Inc. Reconfigurable channel interfaces for memory devices
US12347818B2 (en) 2021-03-26 2025-07-01 Intel Corporation Logic die in a multi-chip package having a configurable physical interface to on-package memory
US11893240B2 (en) 2021-10-28 2024-02-06 Qualcomm Incorporated Reducing latency in pseudo channel based memory systems
US20230013181A1 (en) * 2022-09-14 2023-01-19 Intel Corporation Method to implement half width modes in dram and doubling of bank resources

Also Published As

Publication number Publication date
US20230136996A1 (en) 2023-05-04
US20240111424A1 (en) 2024-04-04
US11893240B2 (en) 2024-02-06
EP4423618A1 (en) 2024-09-04
CN118056195A (zh) 2024-05-17
US12307092B2 (en) 2025-05-20
WO2023075993A1 (en) 2023-05-04
US20250251862A1 (en) 2025-08-07
JP2024542933A (ja) 2024-11-19
TW202321896A (zh) 2023-06-01

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