KR20240085852A - Gamma Voltage Generation Circuit and Source Driver Circuit - Google Patents

Abstract

The present invention relates to a gamma voltage generation circuit and a source driver circuit, comprising: a first voltage divider that outputs a plurality of voltages having different voltage levels between a high-potential reference voltage and a low-potential reference voltage; a plurality of amplifiers that transmit the voltages output from the first voltage divider to output terminals as gamma voltages; a second voltage divider connected between the high-potential reference voltage and the low-potential reference voltage and connected to output terminals of the amplifiers; and one or more self-drivers connected to the second voltage divider to adjust at least one gamma voltage other than the gamma voltages output from the amplifiers.

Description

Gamma Voltage Generation Circuit and Source Driver Circuit

The present invention relates to a gamma voltage generation circuit and a source driver circuit.

Liquid crystal display (LCD), electroluminescence display (ELD) such as organic light emitting diode display (OLED display), field emission display (FED) , various flat panel displays such as plasma display panels (PDP) and electrophoresis displays (EPD) are known.

The display device includes a display panel on which pixels that display an input image are arranged, and a display panel driving circuit that writes data to the pixels of the display panel. The display panel driving circuit includes a data driving circuit that supplies a data signal of source data to the data lines of the display panel, and a gate driving circuit that supplies a gate signal to the gate lines of the display panel.

The display panel driving circuit further includes a gamma voltage generating circuit that supplies a gamma voltage to the data driving circuit. The gamma voltage generation circuit includes many buffer amplifiers, has a large circuit area, and generates a lot of heat and power consumption due to the large peak voltage that occurs when the transition width of the data voltage is large. Since the intermediate gray level voltage output from the gamma voltage generation circuit is generated by driving the buffer amplifier and the voltage distribution circuit, there is a problem that the settling time until it reaches the target voltage becomes long.

The present invention provides a gamma voltage generation circuit and a source driver circuit that can reduce circuit size and improve heat generation, power consumption, and settling time.

A gamma voltage generation circuit according to an embodiment of the present invention includes a first voltage divider that outputs a plurality of voltages having different voltage levels between a high-potential reference voltage and a low-potential reference voltage; a plurality of amplifiers that transmit the voltages output from the first voltage divider to output terminals as gamma voltages; a second voltage divider connected between the high-potential reference voltage and the low-potential reference voltage and connected to output terminals of the amplifiers; and one or more self-drivers connected to the second voltage divider to adjust at least one gamma voltage other than the gamma voltages output from the amplifiers. The self-driver includes a first transistor and a second transistor connected in series.

The first transistor may be an n-channel transistor, and the second transistor may be a p-channel transistor.

The first transistor may include a gate electrode connected to an i (i is a natural number) gamma voltage, a first electrode connected to a driving voltage, and a second electrode connected to an i+1 gamma voltage. The second transistor may include a gate electrode connected to the i+2th gamma voltage, a first electrode connected to the i+1th gamma voltage, and a second electrode connected to the ground voltage.

The i-th gamma voltage may be higher than the i+1-th gamma voltage, and the i+2-th gamma voltage may be lower than the i+1-th gamma voltage.

The first transistor includes a gate electrode connected to the dividing voltage node of the first voltage divider, a first electrode connected to the driving voltage, and an ith (i is a natural number) + 1 gamma voltage corresponding to the voltage output from the dividing node. It may include 2 electrodes. The second transistor may include a gate electrode connected to the voltage dividing node of the first voltage divider, a first electrode connected to the i+1 gamma voltage, and a second electrode connected to the ground voltage.

The first transistor has a gate electrode connected to the dividing node of the first voltage divider, a first electrode connected to the i (i is a natural number) gamma voltage, and an i+1 gamma voltage corresponding to the voltage output from the dividing node. It may include a connected second electrode. The second transistor may include a gate electrode connected to the voltage dividing node of the first voltage divider, a first electrode connected to the i+1th gamma voltage, and a second electrode connected to the i+2th gamma voltage.

The i-th gamma voltage may be higher than the i+1-th gamma voltage, and the i+2-th gamma voltage may be lower than the i+1-th gamma voltage.

The gamma voltage generating circuit includes a first switch element connected to a gate electrode of the first transistor to selectively deactivate the first transistor; And it may further include a second switch element connected to the gate electrode of the second transistor to selectively deactivate the second transistor.

A source driver circuit according to an embodiment of the present invention includes the gamma voltage generation circuit.

The present invention can reduce the settling time of the gamma voltage without adding an amplifier by using a self-driving unit using two transistors. As a result, the present invention can reduce the circuit size of the gamma voltage generation circuit and the source driver circuit and improve heat generation, power consumption, and settling time.

The present invention can increase the settling time or speed of the gamma voltage without reducing the resistance value or increasing the power of the voltage distribution circuit and without consuming constant current, and as a result, when the gray level value of the source data changes, the gamma voltage and the output from the source driver can be increased. The response speed and slew rate of data voltage can be increased.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

1 is a block diagram showing a display device according to an embodiment of the present invention.
Figure 2 is a block diagram schematically showing the circuit configuration of the data driver.
Figures 3 and 4 are circuit diagrams showing a gamma voltage generator according to an embodiment of the present invention.
Figures 5 and 6 are circuit diagrams showing the linear operation of the self-driver.
Figures 7a and 7b are simulation results showing the peak voltage suppression effect of the self-driver with a comparative example.
9 and 10 are circuit diagrams showing a gamma voltage generator according to another embodiment of the present invention.
FIG. 11 is a circuit diagram showing another example of the driving voltage applied to the self-driver shown in FIGS. 9 and 10.
FIG. 12 is a circuit diagram showing an example of additional switch elements connected to the self-driver shown in FIGS. 9 and 10.
Figures 13 and 14 are circuit diagrams showing the linear operation of the self-driver.
Figure 15 is a simulation result diagram verifying the peak voltage suppression effect of the self-driver shown in Figures 9 and 10.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms. The embodiments only serve to ensure that the disclosure of the present invention is complete, and those skilled in the art will be able to understand the present invention. It is provided to completely inform the scope of the invention, and the invention is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. shown in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown in the drawings. Like reference numerals refer to substantially like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

When “provides,” “includes,” “has,” “consists of,” etc. mentioned in this specification are used, other parts may be added unless ‘only’ is used. If a component is expressed in the singular, it may be interpreted as plural unless specifically stated.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

Position between two components, such as 'on', 'on top', 'on the bottom', 'next to', '~ connect, couple', crossing, intersecting, etc. When relationships and interconnections are described, one or more other components may be interposed between the components, unless reference is made to 'immediately' or 'directly'.

If a temporal relationship is described as 'after', 'successfully after', 'after', 'before', etc., it may not be continuous on the time axis unless 'immediately' or 'directly' is used. .

First, second, etc. may be used to distinguish components, but the function or structure of these components is not limited by the ordinal number or component name in front of the component.

The following embodiments can be partially or fully combined or combined with each other, and various technological interconnections and drives are possible. Each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

In the following embodiments, the transistor is a three-electrode device including a gate, source, and drain. In the case of an n-channel transistor, because the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-channel transistor, the direction of current flows from the drain to the source. In the case of a p-channel transistor (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. The source and drain of a transistor are not fixed. In the following description, the source and drain of the transistor will be referred to as first and second electrodes.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

1 is a block diagram showing a display device according to an embodiment of the present invention.

Referring to FIG. 1, a display device according to an embodiment of the present invention includes a display panel 100 and a display panel driving circuit for writing source data into pixels of the display panel 100. Source data can be interpreted as pixel data.

The substrate of the display panel 100 may be a plastic substrate, a thin glass substrate, or a metal substrate, but is not limited thereto. The display panel 100 may be a panel with a rectangular structure having a length in the first direction, a width in the second direction, and a thickness in the third direction, but is not limited thereto. In Figure 1, X, Y, and Z may be a first direction, a second direction, and a third direction, respectively.

In the case of a liquid crystal display device, a back light unit (BLU) may be disposed below the display panel 100. In the case of a self-luminous display device such as an electroluminescent display device, a separate light source such as a backlight unit is not required.

The display area AA of the display panel 100 includes a pixel array that displays an input image. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 crossing the data lines 102, and a pixel 101 connected to the data lines 102 and the gate lines 103. includes them.

Each of the pixels 101 may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to implement color. Each of the pixels may further include a white subpixel. In a liquid crystal display, pixels contain liquid crystal cells. In an electroluminescent display device, pixels include light-emitting elements such as OLED. Each subpixel includes a pixel circuit for driving a liquid crystal cell or a light emitting device.

The display panel driving circuit writes source data of the input image to pixels of the display panel 100 under the control of a timing controller 130. The display panel driving circuit includes a source driver circuit that converts source data into a data voltage and a gate driver 120. The source driver circuit includes a gamma voltage generator 140 and a data driver 110.

The display panel driving circuit may further include a touch sensor driving unit for driving the touch sensors. The touch sensor driver is omitted in FIG. 1. In a mobile terminal or wearable terminal, the timing controller 130, data driver 110, touch sensor driver, etc. may be integrated into one drive IC.

The data driver 110 receives source data of the input image received as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 converts the source data of the input image into a gamma compensation voltage using a digital to analog converter (DAC) and outputs the data voltage.

The gamma voltage generator 140 generates a plurality of gamma voltages with different voltage levels and provides them to the data driver 110. Gamma voltage can be interpreted as a gamma reference voltage, or gamma tab voltage. In the case of light-emitting devices, luminous efficiency may vary depending on color. In accordance with these color-specific luminous efficiency characteristics, the gamma voltages can be separated into independent voltages for each color according to the colors of the subpixels. The gamma voltage generator 140 may be included in the data driver 110 to form a source driver circuit.

Gamma voltages generated by the gamma voltage generator 140 are supplied to the data driver 110. The gamma voltages are divided into gray level voltages corresponding to each gray level of the source data in the data driver 110 and supplied to the DAC. The DAC converts source data, which is a digital signal, into an analog data voltage by outputting a grayscale voltage corresponding to the grayscale value of the source data using a plurality of transistors. The data voltage output from the DAC is output to the data line 102 through an output buffer in each of the data output channels of the data driver 110.

The circuit of the gate driver 120 may be disposed in the non-display area (NA) outside the display area (AA) of the display panel 100, or at least a portion may be disposed in the display area (AA). The gate driver 120 may be integrated into a separate gate drive IC and electrically connected to the gate lines 103 of the display panel 100.

The gate driver 120 sequentially outputs pulses of gate signals to gate lines under the control of the timing controller 130. The gate driver 120 may sequentially supply the gate signal pulses to the gate lines 103 by shifting the gate signal pulses using a shift register.

The timing controller 130 receives source data of the input image and a timing signal synchronized with this data from the external host system 200. The timing signal may include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), and a main clock. Since the vertical period and horizontal period can be known by counting the data enable signal (DE), the vertical synchronization signal (Vsync) and horizontal synchronization signal (Hsync) can be omitted. The vertical synchronization signal (Vsync) has a period of 1 frame. The horizontal synchronization signal (Hsync) and the data enable signal (DE) have a period of 1 horizontal period (1H).

The timing controller 130 controls the operation timing of the display panel driving circuits 110 and 120 based on timing signals (Vsync, Hsync, DE) received from the host system 200.

The host system 200 may scale an image signal from a video source to match the resolution of the display panel 100 and transmit it to the timing controller 130 along with a timing signal. In a mobile system, the host system 200 may be implemented as an Application Processor (AP). The host system 200 may transmit source data of the input image to the drive IC through MIPI (Mobile Industry Processor Interface). The host system 200 may be electrically connected to the drive IC through a flexible printed circuit, for example, a flexible printed circuit (FPC). The drive IC may be bonded onto the display panel 100 using a chip on glass (COG) process. The drive IC may be a chip on film (COF) mounted on a flexible circuit film. The COF may be bonded to data pads disposed in a non-display area of the display panel 100 during a bonding process and electrically connected to data lines on the display panel 100.

Figure 2 is a block diagram schematically showing the circuit configuration of the data driver.

Referring to FIG. 2, the data driver 110 includes a receiving unit 111, a logic control unit 112, a shift register 113, a first latch 114, a second latch 115, It may include a grayscale voltage generator 116, a DAC 117, and an output buffer 118.

The receiving unit 111 receives data (DATA) received serially from the timing controller 130, restores a clock from the data (DATA), and uses the restored clock to receive control data and input video from the data (DATA). The source data is sampled and provided to the logic control unit 112. The timing controller 130 can convert clock and data into low-voltage differential signals and transmit them to the data driver 110 through a high-speed serial interface.

The logic control unit 112 rearranges the pixel data supplied from the receiving unit 111 on a sub-pixel basis. The logic control unit 112 supplies a start pulse and clock to the shift register 113 using the restored clock and control data, and outputs the first and second latch units 114 and 115 and the output buffer 118. Timing can be controlled.

The shift register 113, the first latch 114, and the second latch 115 convert serial data into parallel data. When a start pulse is input, the shift register 113 shifts the clock and outputs it to the channels of the first latch 114. The first latch 114 samples the source data input from the receiver 111 through the logic control unit 112 in response to clocks sequentially input from the shift register 113, and when the source data is latched in all channels, the latch The data is simultaneously output to the channels of the second latch 115. The second latch 115 latches data simultaneously input from the first latch 114 and simultaneously outputs the latched data to the DAC 117 in response to an output enable signal from the logic control unit 112.

The grayscale voltage generator 116 receives a gamma voltage from the gamma voltage generator 140. The gray voltage generator 116 includes a voltage distribution circuit using a plurality of resistors connected in series. The voltage distribution circuit of the gray voltage generator 116 divides the gamma voltages and supplies gray voltages corresponding to each gray level of the source data to the DAC 117.

The DAC 117 selects a grayscale voltage corresponding to the grayscale value of the source data input from the second latch 115 and outputs it as a data voltage (Vdata). The data voltage Vdata is output through the output buffer 118 and applied to the data lines 102 of the display panel 100.

As the gray level of the source data increases, the data voltage Vdata output through the DAC 117 to which the gamma voltage is applied may decrease. On the other hand, as the gray level of the source data decreases, the data voltage (Vdata) may increase.

Figures 3 and 4 are circuit diagrams showing the gamma voltage generator 140 according to an embodiment of the present invention. Hereinafter, 'Vn' is the gamma voltage corresponding to the grayscale value 'n' of the source data.

3 and 4, the gamma voltage generator 140 is connected between the node to which the high-potential reference voltage (MDBV_TOP) is applied and the node to which the low-potential reference voltage (MDBV_BOT) is applied to generate the high-potential reference voltage (MDBV_TOP). ), a low-potential reference voltage (MDBV_BOT), and a first voltage divider ( RS), a plurality of amplifiers (AMP1 to AMP9) connected to the first voltage divider (RS1), connected between the node to which the high-potential reference voltage (MDBV_TOP) is applied and the node to which the low-potential reference voltage (MDBV_BOT) is applied, A second voltage divider (RS2) connected to the output terminal of the amplifiers (AMP1 to AMP9), and gamma voltages (V256, One or more self-drivers (S1 to S8).

In the case of an independent gamma circuit for each color, the gamma voltage generator 140 may include a first gamma voltage generator 140R, a second gamma voltage generator 140G, and a third gamma voltage generator 140B. However, it is not limited to this. The first gamma voltage generator 140R outputs gamma voltages to generate a data voltage (Vdata) applied to the red subpixel. The second gamma voltage generator 140G outputs gamma voltages to generate a data voltage (Vdata) applied to the green subpixel. The third gamma voltage generator 140R outputs gamma voltages to generate a data voltage (Vdata) applied to the blue subpixel.

A high potential reference voltage (MDBV_TOP), a low potential reference voltage (MDBV_BOT), an amplifier driving voltage, a self-driver driving voltage (VDD), etc. are applied to the gamma voltage generator 140. The high potential reference voltage (MDBV_TOP) may be 6V, and the low potential reference voltage (MDBV_BOT) may be 2V, but are not limited thereto. The voltage levels of the high-potential reference voltage (MDBV_TOP) and the low-potential reference voltage (MDBV_BOT) may vary when the brightness is adjusted by the host system 200. For example, when the brightness becomes dark depending on the user interface or the illuminance of the usage environment, the low potential reference voltage (MDBV_BOT) may increase.

The gamma voltage generator 140 outputs first to seventeenth gamma voltages V0 to V2048 having different voltage levels. The gamma voltages may be gamma voltages from gray level 0 to gray level 2048, but are not limited thereto. In the gamma voltage generator 140, gamma voltages output through adjacent output terminals have a predetermined voltage difference. The first gamma voltage V0 output from the gamma voltage generator 140 is 6V, the ninth gamma voltage V1024 is 3.5V, the seventeenth gamma voltage V2048 is 1V, and the nth gamma voltage is Vn= It may be 6V-(6V-1V)ⅹn/2048), but is not limited to this.

The first voltage divider RS1 includes a plurality of resistors connected in series. The first voltage divider (RS1) divides the high-potential reference voltage (MDBV_TOP) between the high-potential reference voltage (MDBV_TOP) and the low-potential reference voltage (MDBV_BOT) to generate voltages (VR256, VR512, VR768, VR1024, VR1280, VR1536, VR1792).

The amplifiers (AMP1 to AMP9) can be interpreted as buffers or voltage followers made of operational amplifiers. Each of the amplifiers (AMP1 to AMP9) includes a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal.

The first amplifier (AMP1) outputs the high potential reference voltage (MDBV_TOP) input to the non-inverting input terminal (+) as the first gamma voltage (V0). The inverting input terminal (-) and the output terminal of the first amplifier (AMP1) are connected to the first output terminal of the gamma voltage generator 140 through which the first gamma voltage (V0) is output. The ninth amplifier (AMP9) outputs the low-potential reference voltage (MDBV_BOT) input to the non-inverting input terminal (+) as the 17th gamma voltage (V2048). The inverting input terminal (-) and the output terminal of the ninth amplifier (AMP9) are connected to the 17th output terminal of the gamma voltage generator 140, which outputs the 17th gamma voltage (V2048). The dynamic range of the data voltage Vdata output from each channel of the data driver 110 is determined by the voltage range of the first gamma voltage V0 and the seventeenth gamma voltage V2048.

The second amplifier AMP2 outputs the voltage VR256 output from the first division node of the first voltage divider RS1 as the third gamma voltage V256. The inverting input terminal (-) and the output terminal of the second amplifier (AMP2) are connected to the third output terminal of the gamma voltage generator 140 from which the third gamma voltage (V256) is output. The third amplifier AMP3 outputs the voltage VR512 output from the second division node of the first voltage divider RS1 as the fifth gamma voltage V512. The inverting input terminal (-) and the output terminal of the third amplifier (AMP3) are connected to the fifth output terminal of the gamma voltage generator 140 from which the fifth gamma voltage (V512) is output. The fourth amplifier AMP4 outputs the voltage VR768 output from the third division node of the first voltage divider RS1 as the seventh gamma voltage V768. The inverting input terminal (-) and the output terminal of the fourth amplifier (AMP4) are connected to the seventh output terminal of the gamma voltage generator 140, which outputs the seventh gamma voltage (V768). The fifth amplifier AMP5 outputs the voltage VR1024 output from the fourth division node of the first voltage divider RS1 as the ninth gamma voltage V1024. The inverting input terminal (-) and the output terminal of the fifth amplifier (AMP5) are connected to the ninth output terminal of the gamma voltage generator 140 through which the fifth gamma voltage (V1024) is output.

The sixth amplifier AMP6 outputs the voltage V1280 output from the fifth division node of the first voltage divider RS1 as the eleventh gamma voltage V1280. The inverting input terminal (-) and the output terminal of the sixth amplifier (AMP6) are connected to the 11th output terminal of the gamma voltage generator 140, which outputs the 11th gamma voltage (V1280). The seventh amplifier AMP7 outputs the voltage VR1536 output from the sixth division node of the first voltage divider RS1 as the thirteenth gamma voltage V1536. The inverting input terminal (-) and the output terminal of the seventh amplifier (AMP7) are connected to the thirteenth output terminal of the gamma voltage generator 140 from which the thirteenth gamma voltage (V1536) is output. The eighth amplifier AMP8 outputs the voltage VR1792 output from the seventh division node of the first voltage divider RS1 as the fifteenth gamma voltage V1792. The inverting input terminal (-) and the output terminal of the eighth amplifier (AMP8) are connected to the fifteenth output terminal of the gamma voltage generator 140 from which the fifteenth gamma voltage (V1792) is output.

The second voltage divider RS2 includes a plurality of resistors connected in series. The second voltage divider RS2 divides the first gamma voltage V0 between the first gamma voltage V0 and the 17th gamma voltage V2048. The first voltage divider RS1 generates a second gamma voltage V128, a third gamma voltage V256, and a voltage level between the first gamma voltage V0 and the third gamma voltage V256 through the voltage dividing nodes. A fourth gamma voltage (V384) having a voltage level between the fifth gamma voltage (V512), a sixth gamma voltage (V640) having a voltage level between the fifth gamma voltage (V512) and the seventh gamma voltage (V768), An 8th gamma voltage (V896) having a voltage level between the 7th gamma voltage (V768) and the 9th gamma voltage (V1024), and a voltage level between the 9th gamma voltage (V1024) and the 11th gamma voltage (V1280) The 10th gamma voltage (V1152), the 12th gamma voltage (V1408) having a voltage level between the 11th gamma voltage (V1280) and the 13th gamma voltage (V1536), the 13th gamma voltage (V1536) and the 15th gamma voltage ( A 14th gamma voltage (V1664) having a voltage level between V1792) and a 16th gamma voltage (V1920) having a voltage level between the 15th gamma voltage (V1792) and the 17th gamma voltage (V2048) can be generated. It is not limited to this.

When the peak voltage of the data voltage (Vdata) is generated, the gamma voltage generator 140 lowers the peak voltage using pre-driving self-drivers (S1 to S8), thereby reducing the peak voltage of the source data. When the gray level changes, the data voltage (Vdata) is allowed to reach the target gray level voltage at a high speed. The gamma voltage generator 140 may include first to eighth self drivers S1 to S8 as shown in FIG. 3 .

Each of the self-drivers (S1 to S8) uses self-driving transistors (MN, MP) in response to the peak voltage of the i (i is a natural number) gamma voltage and the i+2 gamma voltage. The peak voltage of the i+1th gamma voltage can be lowered. The i+1th gamma voltage is lower than the ith gamma voltage and higher than the i+2th gamma voltage. The driving voltage (VDD) of the self-drivers (S1 to S8) may be 8V, and the ground voltage (GND) may be 0V, but is not limited thereto.

The first transistor (MN) may be an n-channel transistor, and the second transistor (MP) may be a p-channel transistor. The first transistor (MN) turns on when Vi - (Vi+1) > Vthn. Here, Vi is the ith gamma voltage (Vi). Vi+1 is a voltage lower than Vi and is the i+1th gamma voltage output through the output node between the first transistor (MN) and the second transistor (MP). Vthn is the threshold voltage of the first transistor (MN).

The second transistor MP is turned on when (Vi+2) - (Vi+1) < Vthp. Here, Vi+2 is the i+2th gamma voltage (Vi+2). Vthp is the threshold voltage of the second transistor (MP).

The first transistor (MN) has a gate electrode connected to the output terminal to which the i-th gamma voltage is applied, a first electrode (drain) connected to the node to which the driving voltage (VDD) is applied, and an output to which the i+1-th gamma voltage is applied. It may include a second electrode (source) connected to the terminal. The second transistor MP has a gate electrode connected to the output terminal to which the i+2th gamma voltage is applied, a first electrode (source) connected to the output terminal to which the i+1th gamma voltage is applied, and a ground voltage (GND). It may include a second electrode (drain) connected to the applied node.

Since the gate-source voltage is applied at a voltage close to the threshold voltage (Vthn, Vthp), the first and second transistors (MN, MP) change their own voltage when the grayscale of the source data changes and the i+1th gamma voltage changes. Even at a voltage lower than the threshold voltage, one of the voltages is turned on to lower the peak voltage of the i+1th gamma voltage. As a result, each self-driver has the effect of lowering the threshold voltage (Vthn, Vthp) of the transistor, and this effect can be further improved as the voltage difference between the high-potential reference voltage (MDVB_TOP) and the low-potential reference voltage (MDBV_BOT) is larger. .

The first self-driver S1 includes first and second transistors MN and MP connected in series between the first gamma voltage V0 and the third gamma voltage V256. The first and second transistors (MN, MP) are connected in series between the driving voltage (VDD) and the ground voltage (GND). The first transistor (MN) has a gate electrode connected to the first gamma voltage (V0), a first electrode (drain) connected to the driving voltage (VDD), and a second electrode (source) connected to the second gamma voltage (V128). Includes. The first transistor MN is turned on when a falling peak voltage is generated in the second gamma voltage V128, thereby lowering the peak voltage so that the second gamma voltage V128 quickly reaches the target voltage. The second transistor (MP) has a gate electrode connected to the third gamma voltage (V256), a first electrode (source) connected to the second gamma voltage (V128), and a second electrode (drain) connected to the ground voltage (GND). Includes. The second transistor MP is turned on when a rising peak voltage is generated in the second gamma voltage V128 and lowers the peak voltage so that the second gamma voltage V128 quickly reaches the target voltage.

The first transistor (MN) of the second self-driver (S2) is turned on when a falling peak voltage is generated in the fourth gamma voltage (V384) to lower the peak voltage. The second transistor (MP) of the second self-driver (S2) is turned on when a rising peak voltage is generated in the fourth gamma voltage (V384) and lowers the peak voltage. The first transistor (MN) of the third self-driver (S3) is turned on when a peak voltage falling from the sixth gamma voltage (V640) is generated to lower the peak voltage. The second transistor MP of the third self-driver S3 is turned on when a peak voltage rising from the sixth gamma voltage V640 is generated to lower the peak voltage.

The first transistor (MN) of the fourth self-driver (S4) is turned on when a peak voltage falling from the eighth gamma voltage (V896) is generated to lower the peak voltage. The second transistor MP of the fourth self-driver S4 is turned on when a peak voltage rising from the eighth gamma voltage V896 is generated to lower the peak voltage. The first transistor (MN) of the fifth self-driver (S5) is turned on when a peak voltage falling from the tenth gamma voltage (V1152) is generated to lower the peak voltage. The second transistor MP of the fifth self-driver S5 is turned on when a peak voltage rising from the tenth gamma voltage V1152 is generated to lower the peak voltage. The first transistor (MN) of the sixth self-driver (S6) is turned on when a peak voltage falling from the 12th gamma voltage (V1408) is generated to lower the peak voltage. The second transistor MP of the sixth self-driver S6 is turned on when a rising peak voltage is generated in the twelfth gamma voltage V1408 to lower the peak voltage. The first transistor (MN) of the seventh self-driver (S7) is turned on when a peak voltage falling from the 14th gamma voltage (V1664) is generated to lower the peak voltage. The second transistor (MP) of the seventh self-driver (S7) is turned on when a rising peak voltage is generated at the 14th gamma voltage (V1664) and lowers the peak voltage.

The eighth self-driver (S8) includes first and second transistors (MN, MP) connected in series between the 15th gamma voltage (V1792) and the 17th gamma voltage (V2048). The first transistor (MN) has a gate electrode connected to the 15th gamma voltage (V1792), a first electrode (drain) connected to the driving voltage (VDD), and a second electrode (source) connected to the 16th gamma voltage (V1920). Includes. The first transistor MN is turned on when a falling peak voltage occurs in the 16th gamma voltage V1920 and lowers the peak voltage so that the 16th gamma voltage V1920 quickly reaches the target voltage. The second transistor (MP) has a gate electrode connected to the 17th gamma voltage (V2048), a first electrode (source) connected to the 16th gamma voltage (V1920), and a second electrode (drain) connected to the ground voltage (GND). Includes. The second transistor MP is turned on when a rising peak voltage is generated in the 16th gamma voltage V1920 and lowers the peak voltage so that the 16th gamma voltage V1920 quickly reaches the target voltage.

Some of the self-drivers may be omitted. For example, the gamma voltage generator 140 may be connected to a self-driver (SD) only to a gamma voltage that reaches the target voltage at a relatively slow speed, as shown in FIG. 4 . For example, the 16th gamma voltage V1920 reaches the target voltage at a relatively slow rate compared to other gamma voltages when the gray level of the source data input to the data driver 110 changes. In this case, the number of self-drivers is less than the number of amplifiers.

Referring to FIG. 4, the gamma voltage generator 140 generates a first gamma voltage (V0), a second gamma voltage (V256) lower than the first gamma voltage (V0), and a third gamma voltage (V256) lower than the second gamma voltage (V256). Gamma voltage (V512), fourth gamma voltage (V768) lower than third gamma voltage (V512), fifth gamma voltage (V1024) lower than fourth gamma voltage (V768), lower than fifth gamma voltage (V1024) 6 gamma voltage (V1280), 7th gamma voltage (V1536) lower than 6th gamma voltage (V1280), 8th gamma voltage (V1792) lower than 7th gamma voltage (V1536), lower than 8th gamma voltage (V1792) A ninth gamma voltage (V1920) and a tenth gamma voltage (V2048) lower than the ninth gamma voltage (V1920) are output.

The voltage levels of the first to eighth and tenth gamma voltages (V0 to V1792, V2048) are determined by the output voltages of the amplifiers (AMP1 to AMP9). The ninth gamma voltage (V1920) is output from the dividing voltage node between the eighth gamma voltage (V1792) and the tenth gamma voltage (V2048) in the resistance column of the second voltage divider (RS2), and is used as a line driving force of the self-driver (SD). The peak voltage is suppressed.

When the grayscale value of the source data increases, the data voltage Vdata output from the data driver 110 may decrease. At this time, a peak voltage occurs in the gamma voltage due to the peak current flowing in the gamma voltage wire connected to the DAC 117. Self-drivers (S1 to S8) are driven when a peak voltage occurs in the gamma voltage and lower the peak voltage. The linear driving movement of these self-drivers (S1 to S8) will be described in detail with reference to FIGS. 5 to 7B.

Referring to FIG. 5, the gate-source voltage of the first transistor (MN) is V1792-V1920. When the grayscale value of the source data decreases, the peak voltage (Vp) that rapidly decreases in the gamma voltage (V1920) may occur. For example, when the grayscale value of the source data changes from 2048 to 1920, a falling peak voltage may occur in the gamma voltage (V1920) output as the data voltage (Vdata) through the DAC 117. At this time, the source voltage of the first transistor (MN) decreases. When the source voltage of the first transistor (MN) becomes lower than the threshold voltage (Vthn) of the first transistor (MN), the gate-source voltage of the first transistor (MN) becomes greater than the threshold voltage (Vthn) and the first transistor (MN) ) turns on. As a result, the driving voltage VDD is applied to the gamma voltage 1920 through the turned-on first transistor MN, thereby lowering the falling peak voltage Vp. When the peak voltage Vp falling in the gamma voltage V1920 occurs, the source voltage of the second transistor MP is lowered, so the second transistor MP is not turned on.

Referring to FIG. 6, the gate-source voltage of the second transistor MP is V2048-V1920. When the gray level value of the source data increases, a peak voltage (Vp) that rapidly increases in the gamma voltage (V1920) may occur. For example, when the grayscale value of the source data changes from 1792 to 1920, a rising peak voltage may be generated in the gamma voltage (V1920) output as the data voltage (Vdata) through the DAC (117). At this time, the source voltage of the second transistor MP increases. When the source voltage of the second transistor MP increases and the gate-source voltage of the second transistor MP becomes smaller than the threshold voltage Vthp, the second transistor MP is turned on. As a result, the peak voltage of the gamma voltage V1920 is discharged to the ground voltage GND through the turned-on second transistor MP, thereby lowering the peak voltage Vp. When the peak voltage Vp that rises in the gamma voltage V1920 occurs, the source voltage of the first transistor MN increases, so the first transistor MN is not turned on. The first and second transistors (MN, MP) cannot be turned on at the same time.

Figures 7a and 7b are simulation results showing the peak voltage suppression effect of the self-driver with a comparative example.

Figure 7a is a simulation result showing the peak voltage (Vp) of the gamma voltage (V1920) in a comparative example without a self-driver (SD). In the case of the comparative example, without reducing the resistance value of the voltage divider (RS2) or adding an amplifier, when the gray level of the source data changes, the time until the data voltage (Vdata) reaches the target voltage is limited by the resistance value, and the data voltage (Vdata) ), there is a limit to improving the slew rate, and constant current consumption is large when the data voltage (Vdata) changes.

Figure 7b is a simulation result in which the peak voltage (Vp) is lowered by connecting the self-driver (SD) to the gamma voltage (V1920). In this simulation, it was confirmed that when the grayscale value of the source data increases from 0 to 1920, the peak voltage of the gamma voltage (V1920), which is the target voltage of the grayscale value of 1920, is discharged through the self-driver (SD) and lowered. Due to the line driving effect of the self-driver (SD), the data voltage 80 increases when the gradation of the source data changes without reducing the resistance value of the second voltage divider RS2 or connecting an additional amplifier to the gamma voltage V1920. The slew rate is improved by quickly reaching the target voltage. Additionally, connecting the self-driver (SD) to the gamma voltage (V1920) improves the slew rate of the data voltage without consuming constant current. In FIGS. 7A and 7B, '1H' is 1 horizontal period in which the data voltage (Vdata) is written to 1 pixel line.

Figure 8 is a circuit diagram showing the third voltage divider of the gamma voltage generator.

Referring to FIG. 8 , the gamma voltage generator 140 may further include a third voltage distributor (RS3) and first and second multiplexers (MUX1 and MUX2).

The third voltage divider RS3 includes a plurality of resistors connected in series between the high potential input voltage VREG and the low potential input voltage VREF. The third voltage divider RS3 generates a plurality of voltages with different voltage levels between the high-potential input voltage VREG and the low-potential input voltage VREF through the voltage dividing nodes.

The first multiplexer (MUX1) selects one of the high potential voltages output from the third voltage divider (RS3) in response to a preset register value or a digital brightness value (DBV) generated from the host system 200. Select one and print it. The output voltage of the first multiplexer (MUX1) is the high potential reference voltage (MDBV_TOP) transmitted to the first voltage divider (RS1) through the first amplifier (AMP1).

The second multiplexer (MUX2) selects one of the low potential voltages output from the third voltage divider (RS3) in response to a preset register value or a digital brightness value (DBV) generated from the host system 200. and print it out. The output voltage of the second multiplexer (MUX2) is the total potential reference voltage (MDBV_BOT) transmitted to the first voltage divider (RS1) through the ninth amplifier (AMP9).

9 and 10 are circuit diagrams showing a gamma voltage generator according to another embodiment of the present invention. In FIGS. 9 and 10 , components that are substantially the same as those in the above-described embodiment are given the same reference numerals, and detailed descriptions thereof are omitted.

9 and 10, the gamma voltage generator 140 includes a first voltage divider (RS1), a second voltage divider (RS2), a plurality of amplifiers (AMP1 to AMP9), and one or more self-drivers ( S11~S18). The gamma voltage generator 140 may further include a third voltage divider RS3 and first and second multiplexers MUX1 and MUX2.

Each of the self-drivers (S1 to S8) uses the first and second transistors (MN, MP) connected between the first voltage divider (RS1) and the second voltage divider (RS2) to generate the i-th gamma voltage and The peak voltage of the i+1th gamma voltage between the i+2th gamma voltage is suppressed.

The first transistor (MN) may be an n-channel transistor, and the second transistor (MP) may be a p-channel transistor. The first transistor (MN) turns on when (VRi+1) - (Vi+1) > Vthn. Here, VRi+1 is the voltage of the first voltage divider RS1 corresponding to the i+1th gamma voltage (Vi+1). Vthn is the threshold voltage of the first transistor (MN).

The second transistor MP is turned on when (VRi+1) - (Vi+1) < Vthp. Here, Vthp is the threshold voltage of the second transistor MP.

The first self-driver S11 operates first when a peak voltage is generated in the second gamma voltage V128 between the first gamma voltage V0 and the third gamma voltage V256 to lower the peak voltage. The first transistor (MN) has a gate electrode connected to the voltage (VR128) output from the voltage dividing node of the first voltage divider (RS1), a first electrode (drain) connected to the driving voltage (VDD), and a second gamma voltage ( It includes a second electrode (source) connected to V128). The first transistor MN is turned on when a falling peak voltage is generated in the second gamma voltage V128 and lowers the peak voltage so that the second gamma voltage V128 quickly reaches the target voltage. The second transistor MP has a gate electrode connected to the voltage VR128 output from the dividing voltage node of the first voltage divider RS1, a first electrode (source) connected to the second gamma voltage V128, and a ground voltage ( It includes a second electrode (drain) connected to GND). The second transistor MP is turned on when a rising peak voltage is generated in the second gamma voltage V128 and lowers the peak voltage so that the second gamma voltage V128 quickly reaches the target voltage.

The first transistor (MN) of the second self-driver (S12) is turned on when a falling peak voltage is generated in the fourth gamma voltage (V384) to lower the peak voltage. The second transistor MP of the second self-driver S12 is turned on when a rising peak voltage is generated in the fourth gamma voltage V384 and lowers the peak voltage. The first transistor (MN) of the third self-driver (S13) is turned on when a peak voltage falling from the sixth gamma voltage (V640) is generated to lower the peak voltage. The second transistor (MP) of the third self-driver (S13) is turned on when a rising peak voltage is generated in the sixth gamma voltage (V640) and lowers the peak voltage.

The first transistor (MN) of the fourth self-driver (S14) is turned on when a peak voltage falling from the eighth gamma voltage (V896) is generated to lower the peak voltage. The second transistor MP of the fourth self-driver S14 is turned on when a peak voltage rising from the eighth gamma voltage V896 is generated to lower the peak voltage. The first transistor (MN) of the fifth self-driver (S15) is turned on when a peak voltage falling from the tenth gamma voltage (V1152) is generated to lower the peak voltage. The second transistor MP of the fifth self-driver S15 is turned on when a peak voltage rising from the tenth gamma voltage V1152 is generated to lower the peak voltage. The first transistor (MN) of the sixth self-driver (S16) is turned on when a peak voltage falling from the 12th gamma voltage (V1408) is generated to lower the peak voltage. The second transistor MP of the sixth self-driver S16 is turned on when a rising peak voltage is generated in the twelfth gamma voltage V1408 to lower the peak voltage. The first transistor (MN) of the seventh self-driver (S17) is turned on when a falling peak voltage is generated in the 14th gamma voltage (V1664) to lower the peak voltage. The second transistor (MP) of the seventh self-driver (S17) is turned on when a rising peak voltage is generated in the 14th gamma voltage (V1664) and lowers the peak voltage.

The eighth self-driver (S11) operates first when a peak voltage is generated in the 16th gamma voltage (V1920) between the 15th gamma voltage (V1792) and the 17th gamma voltage (V2048) to lower the peak voltage. The first transistor MN includes a gate electrode connected to the voltage VR1920 output from the voltage dividing node of the first voltage divider RS1, a first electrode (drain) connected to the driving voltage VDD, and a 16th gamma voltage ( It includes a second electrode (source) connected to V1920). The first transistor MN is turned on when a falling peak voltage is generated in the 16th gamma voltage V1920 and lowers the peak voltage so that the 16th gamma voltage V1920 quickly reaches the target voltage. The second transistor MP has a gate electrode connected to the voltage VR1920 output from the dividing voltage node of the first voltage divider RS1, a first electrode (source) connected to the 16th gamma voltage V1920, and a ground voltage ( It includes a second electrode (drain) connected to GND). The second transistor MP is turned on when a rising peak voltage is generated in the 16th gamma voltage V1920 and lowers the peak voltage so that the 16th gamma voltage V1920 quickly reaches the target voltage.

Some of the self-drivers may be omitted. For example, the gamma voltage generator 140 may be connected to the self-driver SD2 only to a gamma voltage that reaches the target voltage at a relatively slow speed, as shown in FIG. 10 . For example, the 16th gamma voltage V1920 reaches the target voltage at a relatively slow rate compared to other gamma voltages when the gray level of the source data input to the data driver 110 changes.

Referring to FIG. 10, the gamma voltage generator 140 generates a first gamma voltage (V0), a second gamma voltage (V256) lower than the first gamma voltage (V0), and a third gamma voltage (V256) lower than the second gamma voltage (V256). Gamma voltage (V512), fourth gamma voltage (V768) lower than third gamma voltage (V512), fifth gamma voltage (V1024) lower than fourth gamma voltage (V768), lower than fifth gamma voltage (V1024) 6 gamma voltage (V1280), 7th gamma voltage (V1536) lower than 6th gamma voltage (V1280), 8th gamma voltage (V1792) lower than 7th gamma voltage (V1536), lower than 8th gamma voltage (V1792) A ninth gamma voltage (V1920) and a tenth gamma voltage (V2048) lower than the ninth gamma voltage (V1920) are output.

The voltage levels of the first to eighth and tenth gamma voltages (V0 to V1792, V2048) are determined by the output voltages of the amplifiers (AMP1 to AMP9). The ninth gamma voltage (V1920) is output from the dividing voltage node between the eighth gamma voltage (V1792) and the tenth gamma voltage (V2048) in the resistance column of the second voltage divider (RS2), and is used as a line driving force of the self-driver (SD2). The peak voltage is suppressed.

The driving voltage applied to the self-drivers (S11 to S18) can be changed as shown in FIG. 11.

Referring to FIG. 11, the first transistor MN has a gate electrode connected to the voltage dividing node of the first voltage divider RS1, a first electrode connected to the i-th gamma voltage higher than the i+1-th gamma voltage, and a voltage dividing node. It includes a second electrode connected to the i+1th gamma voltage corresponding to the voltage output from. The second transistor MP has a gate electrode connected to the voltage dividing node of the first voltage divider RS1, a first electrode connected to the i+1th gamma voltage, and an i+2th gamma voltage lower than the i+1th gamma voltage. It includes a second electrode connected to.

An i-th gamma voltage higher than the i+1-th gamma voltage is applied to the first electrode of the first transistor (MN), and an i+2-th gamma voltage lower than the i+1-th gamma voltage is applied to the second electrode of the second transistor (MP). A gamma voltage may be applied. For example, in the self-driver SD2 for suppressing the peak voltage of the gamma voltage V1920, the gamma voltage V1792 is applied to the first electrode of the first transistor MN, and the gamma voltage V1792 is applied to the first electrode of the second transistor MP. A gamma voltage (V2048) may be applied to the second electrode.

Self-drivers (S11~S18, SD2) can be selectively disabled. To this end, as shown in FIG. 12, switch elements SW1 and SW2 may be connected to the gate electrodes of each of the first and second transistors MN and MP. Each of the switch elements SW1 and SW2 may be implemented as a CMOS transistor. The switch elements SW1 and SW2 may be controlled by any one of the host system 200, the timing controller 130, and the logic control unit 112. When the customer or user does not want to use the self-driver function, the self-driver (S11~S18, SD2) can be deactivated using the first and second switch elements (SW1, SW2) by register (or memory) setting. You can. For example, if an EMI issue occurs due to excessive transition speed of gamma voltage and data voltage due to the self-driver depending on the system, the customer may disable the self-driver (S11~S18, SD2) to increase the transition speed. can be delayed.

When the first switch element (SW1) connects the gate electrode of the first transistor (MN) to the ground voltage (GND), the first transistor (MN) remains in an off state. When the first switch element (SW1) connects the gate electrode of the first transistor (MN) in the same manner as shown in FIGS. 3, 5, 9, and 10, the first transistor (MN) responds to changes in the gamma voltage (V1920). It can be turned on accordingly.

When the first switch element (SW1) connects the gate electrode of the first transistor (MN) to the ground voltage (GND), the first transistor (MN) remains in an off state. When the first switch element (SW1) connects the gate electrode of the first transistor (MN) in the same manner as shown in FIGS. 3, 4, 9, and 10, the first transistor (MN) changes the gamma voltage (V1920). It may be turned on depending on . When the second switch element SW2 connects the gate electrode of the second transistor MP to the driving voltage VDD, the second transistor MP remains in an off state. When the second switch element (SW2) connects the gate electrode of the second transistor (MP) in the same manner as shown in FIGS. 3, 4, 9, and 10, the second transistor (MP) changes the gamma voltage (V1920). It may be turned on depending on .

The linear driving of the self-drivers (S11 to S18, SD2) will be described in detail with reference to FIGS. 13 to 15.

Referring to FIG. 13, the gate-source voltage of the first transistor (MN) is VR1920-V1920. When the grayscale value of the source data decreases, the peak voltage (Vp) that rapidly decreases in the gamma voltage (V1920) may occur. At this time, the source voltage of the first transistor (MN) decreases. When the source voltage of the first transistor (MN) becomes lower than the threshold voltage (Vthn) of the first transistor (MN), the gate-source voltage of the first transistor (MN) becomes greater than the threshold voltage (Vthn) and the first transistor (MN) ) turns on. As a result, the driving voltage VDD is applied to the gamma voltage 1920 through the turned-on first transistor MN, thereby lowering the falling peak voltage Vp. When the peak voltage Vp falling in the gamma voltage V1920 occurs, the source voltage of the second transistor MP is lowered, so the second transistor MP is not turned on.

Referring to FIG. 14, the gate-source voltage of the second transistor MP is VR1920-V1920. When the gray level value of the source data increases, a peak voltage (Vp) that rapidly increases in the gamma voltage (V1920) may occur. For example, when the grayscale value of the source data changes from 1792 to 1920, a rising peak voltage may be generated in the gamma voltage (V1920) output as the data voltage (Vdata) through the DAC (117). At this time, the source voltage of the second transistor MP increases. When the source voltage of the second transistor MP increases and the gate-source voltage of the second transistor MP becomes smaller than the threshold voltage Vthp, the second transistor MP is turned on. As a result, the peak voltage of the gamma voltage V1920 is discharged to the ground voltage GND through the turned-on second transistor MP, thereby lowering the peak voltage Vp. When the peak voltage Vp that rises in the gamma voltage V1920 occurs, the source voltage of the first transistor MN increases, so the first transistor MN is not turned on.

Figure 15 is a simulation result diagram verifying the peak voltage suppression effect of the self-driver shown in Figures 9 and 10. In this simulation, it was confirmed that when the grayscale value of the source data increases from 0 to 1920 in all channels of the data driver 110, the peak voltage of the gamma voltage (V1920) is discharged through the self-driver (SD2) and lowered. As can be seen from this simulation result, when the second transistor (MP) is driven, the first transistor (MN) remains in an off state and no current flows. In FIG. 15, 'EN' is an output enable signal that controls the output timing of the second latch 115 of the data driver 110.

Since the contents of the specification described in the problem to be solved, the means to solve the problem, and the effect described above do not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the content of the specification.

Although embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

100: display panel 110: data driver
120: Gate driver 130: Timing controller
RS1: first voltage divider RS2: second voltage divider
RS3: Third voltage divider AMP1~AMP9: Amplifier
S1~S8, S11~S18, SD, SD2: Self-driver

Claims (10)

a first voltage divider that outputs a plurality of voltages having different voltage levels between a high-potential reference voltage and a low-potential reference voltage;
a plurality of amplifiers that transmit the voltages output from the first voltage divider to output terminals as gamma voltages;
a second voltage divider connected between the high-potential reference voltage and the low-potential reference voltage and connected to output terminals of the amplifiers; and
One or more self-drivers connected to the second voltage divider to adjust at least one gamma voltage other than the gamma voltages output from the amplifiers,
The self-driver,
A gamma voltage generating circuit including a first transistor and a second transistor connected in series. According to claim 1,
The first transistor is an n-channel transistor, and the second transistor is a p-channel transistor. According to claim 2,
The first transistor includes a gate electrode connected to an i (i is a natural number) gamma voltage, a first electrode connected to a driving voltage, and a second electrode connected to an i+1 gamma voltage,
The second transistor is a gamma voltage generating circuit including a gate electrode connected to the i+2th gamma voltage, a first electrode connected to the i+1th gamma voltage, and a second electrode connected to the ground voltage. According to claim 3,
The i-th gamma voltage is higher than the i+1-th gamma voltage,
A gamma voltage generating circuit in which the i+2th gamma voltage is lower than the i+1th gamma voltage. According to claim 2,
The first transistor includes a gate electrode connected to the dividing voltage node of the first voltage divider, a first electrode connected to the driving voltage, and an ith (i is a natural number) + 1 gamma voltage corresponding to the voltage output from the dividing node. Contains 2 electrodes,
The second transistor is a gamma voltage generating circuit including a gate electrode connected to the dividing voltage node of the first voltage divider, a first electrode connected to the i+1th gamma voltage, and a second electrode connected to the ground voltage. According to claim 2,
The first transistor has a gate electrode connected to the dividing voltage node of the first voltage divider, a first electrode connected to the i (i is a natural number) gamma voltage, and an i+1 gamma voltage corresponding to the voltage output from the dividing node. Comprising a connected second electrode,
The second transistor is a gamma voltage generating circuit including a gate electrode connected to a voltage dividing node of the first voltage divider, a first electrode connected to the i+1th gamma voltage, and a second electrode connected to the i+2th gamma voltage. The method of claim 5 or 6,
The i-th gamma voltage is higher than the i+1-th gamma voltage,
A gamma voltage generating circuit in which the i+2th gamma voltage is lower than the i+1th gamma voltage. According to any one of claims 3, 5 and 6,
a first switch element connected to the gate electrode of the first transistor to selectively deactivate the first transistor; and
A gamma voltage generating circuit further comprising a second switch element connected to the gate electrode of the second transistor to selectively deactivate the second transistor. a data driver that converts source data into data voltages based on gamma voltages; and
It includes a gamma voltage generator that generates the gamma voltages,
The gamma voltage generator,
a first voltage divider that outputs a plurality of voltages having different voltage levels between a high-potential reference voltage and a low-potential reference voltage;
a plurality of amplifiers that transmit the voltages output from the first voltage divider to output terminals as gamma voltages;
a second voltage divider connected between the high-potential reference voltage and the low-potential reference voltage and connected to output terminals of the amplifiers; and
One or more self-drivers connected to the second voltage divider to adjust at least one gamma voltage other than the gamma voltages output from the amplifiers,
The self-driver,
A source driver circuit including a first transistor and a second transistor connected in series. According to clause 9,
The first transistor is an n-channel transistor, and the second transistor is a p-channel transistor.