KR20240071966A - Printed circuit board and manufacturing method for the same - Google Patents

Abstract

The present disclosure includes: a first insulating layer; a plurality of first circuit patterns each disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer and covering a portion of a side surface of each of the plurality of first circuit patterns; and an insulating portion disposed between at least one pair of adjacent first circuit patterns among the plurality of first circuit patterns and integrated with the first insulating layer. It relates to printed circuit boards and their manufacturing methods, including.

Description

Printed circuit board and manufacturing method thereof {PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD FOR THE SAME}

The present disclosure relates to a printed circuit board, for example, a printed circuit board including microcircuits, and a method of manufacturing the same.

Recently, in the electronic components industry, highly integrated printed circuit boards are being required to respond to 5G high-speed communication and artificial intelligence. Microcircuitry is a core technology for manufacturing highly integrated printed circuit boards, and research and development is actively underway to secure technology that can implement microcircuits with lines/spaces of approximately several microns, for example. However, conventional circuit formation methods, such as SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), and ETS (Embedded Trace Substrate), are limited in the resolution of exposure equipment and the margin of the seed etching process. There are limitations in implementing fine circuits in the above-described line/space range, and in addition, recess steps and circuit thickness deviations inevitably occur during the seed etching process, which may reduce reliability.

One of the several purposes of the present disclosure is to provide a printed circuit board capable of forming fine circuits and a method of manufacturing the same.

Another purpose of the present disclosure is to provide a highly reliable printed circuit board and a method of manufacturing the same.

One of the several solutions proposed through this disclosure is to expose and develop the dry film so that the line/space ratio is not 1:1 but more than 1:1 to form a plurality of dry film patterns, and to form a seed metal layer thereon. A plating layer is formed to an approximately constant thickness on the seed metal layer, and then covered with a second insulating layer and then subjected to primary polishing. After removing a plurality of dry film patterns, covered with a first insulating layer and then subjected to secondary polishing. , forming a fine circuit.

For example, a method of manufacturing a printed circuit board according to one example includes forming a first dry film on a detach substrate; patterning the first dry film to form a plurality of dry film patterns spaced apart from each other on the detach substrate; forming a seed metal layer covering each of the plurality of dry film patterns on the detach substrate; forming a first plating layer on the seed metal layer along the detach substrate and the plurality of dry film patterns; forming a second insulating layer on the first plating layer, covering the first plating layer and filling the space between the first plating layers; polishing at least a portion of each of the second insulating layer, the first plating layer, and the seed metal layer; removing the plurality of dry film patterns remaining between the seed metal layers; forming a first insulating layer on the detach substrate, covering the second insulating layer and the first plating layer and filling a space between the seed metal layers; removing the detach substrate; and polishing at least a portion of each of the seed metal layer, the first plating layer, and the first insulating layer. It may include.

In addition, the printed circuit board according to one example includes a first insulating layer; a plurality of first circuit patterns each disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer and covering a portion of a side surface of each of the plurality of first circuit patterns; and an insulating portion disposed between at least one pair of adjacent first circuit patterns among the plurality of first circuit patterns and integrated with the first insulating layer. It may include.

Additionally, a printed circuit board according to one example includes an insulating material; and a plurality of first circuit patterns each embedded in the insulating material. A seed metal layer is disposed on one side facing each other of at least one pair of adjacent first circuit patterns among the plurality of first circuit patterns, and the seed metal layer is disposed on the other side opposite to the one side. It may not work.

As one of the many effects of the present disclosure, a printed circuit board capable of forming a fine circuit and a method of manufacturing the same can be provided.

As another effect among the various effects of the present disclosure, a printed circuit board with excellent reliability and a method of manufacturing the same can be provided.

1 is a block diagram schematically showing an example of an electronic device system.
Figure 2 is a perspective view schematically showing an example of an electronic device.
Figure 3 is a cross-sectional view schematically showing an example of a printed circuit board.
Figure 4 is a plan view showing a schematic top view of the printed circuit board of Figure 3.
FIGS. 5A to 5K are process diagrams schematically showing an example of manufacturing the printed circuit board of FIGS. 3 and 4.
FIGS. 6A to 6E are process diagrams schematically showing an example of the cut etching of FIG. 5E.
Figure 7 is a cross-sectional view schematically showing another example of a printed circuit board.
Figure 8 is a plan view showing a schematic top view of the printed circuit board of Figure 7.
FIGS. 9A to 9I are process diagrams schematically showing an example of manufacturing the printed circuit board of FIGS. 7 and 8.
Figure 10 is a cross-sectional view schematically showing another example of a printed circuit board.
FIGS. 11A to 11C are process diagrams schematically showing an example of manufacturing the printed circuit board of FIG. 10.
Figure 12 is a cross-sectional view schematically showing another example of a printed circuit board.
FIGS. 13A to 13C are process diagrams schematically showing an example of manufacturing the printed circuit board of FIG. 12.
Figure 14 is a cross-sectional view schematically showing another example of a printed circuit board.
Figures 15A to 15F are process charts schematically showing an example of manufacturing the printed circuit board of Figure 14.

Hereinafter, the present disclosure will be described with reference to the attached drawings. The shapes and sizes of elements in the drawings may be exaggerated or reduced for clearer explanation.

Electronics

1 is a block diagram schematically showing an example of an electronic device system.

Referring to the drawing, the electronic device 1000 accommodates the main board 1010. The main board 1010 is physically and/or electrically connected to chip-related components 1020, network-related components 1030, and other components 1040. These are combined with other electronic components described later to form various signal lines 1090.

Chip-related components 1020 include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory; Application processor chips such as central processors (eg, CPU), graphics processors (eg, GPU), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; Logic chips such as analog-digital converters and ASICs (application-specific ICs) are included, but are not limited thereto, and other types of chip-related electronic components may also be included. Additionally, it goes without saying that these chip-related components 1020 can be combined with each other. The chip-related component 1020 may be in the form of a package including the above-described chip or electronic component.

Network-related parts (1030) include Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM. , GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and any other wireless and wired protocols designated as such, but are not limited to, and many other wireless or wired protocols. Any of the standards or protocols may be included. In addition, of course, the network-related components 1030 can be combined with the chip-related components 1020.

Other parts (1040) include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (Electro Magnetic Interference) filter, MLCC (Multi-Layer Ceramic Condenser), etc. . However, it is not limited to this, and may include passive elements in the form of chip components used for various other purposes. In addition, of course, the other components 1040 may be combined with the chip-related components 1020 and/or the network-related components 1030.

Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and/or electrically connected to the main board 1010. Examples of other electronic components include a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. However, it is not limited to this, and may include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), etc. It may be possible. In addition to this, of course, other electronic components used for various purposes may be included depending on the type of electronic device 1000.

The electronic device 1000 includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, and a computer ( It may be a computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive, etc. However, it is not limited to this, and of course, it can be any other electronic device that processes data.

Figure 2 is a perspective view schematically showing an example of an electronic device.

Referring to the drawings, the electronic device may be, for example, a smartphone 1100. A motherboard 1110 is accommodated inside the smartphone 1100, and various components 1120 are physically and/or electrically connected to the motherboard 1110. Additionally, other components that may or may not be physically and/or electrically connected to the motherboard 1110, such as the camera module 1130 and/or the speaker 1140, are accommodated therein. Some of the components 1120 may be the chip-related components described above, for example, the component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components including active components and/or passive components are surface mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board with built-in active components and/or passive components. Meanwhile, the electronic device is not necessarily limited to the smartphone 1100, and of course may be other electronic devices as described above.

printed circuit board

Figure 3 is a cross-sectional view schematically showing an example of a printed circuit board.

Figure 4 is a plan view showing a schematic top view of the printed circuit board of Figure 3.

Referring to the drawing, a printed circuit board 100A according to an example includes a first insulating layer 111, a plurality of first circuit patterns 121 respectively disposed on the first insulating layer 111, and a first insulating layer. It is disposed on 111 and includes a second insulating layer 112 covering a portion of the side surface of each of the plurality of first circuit patterns 121. A portion of the first insulating layer 111, for example, the insulating portion 111P, is disposed to extend between at least one pair of adjacent first circuit patterns 121 among the plurality of first circuit patterns 121. An interlayer interface, such as a boundary, exists between the first and second insulating layers 111 and 112, while an interlayer interface, such as a boundary, exists between the first insulating layer 111 and the insulating portion 111P. does not exist. For example, the insulating portion 111P and the first insulating layer 111 may be integrated with each other without a boundary.

Meanwhile, the insulating portion 111P may be disposed between one side of each of at least one pair of adjacent first circuit patterns 121. Additionally, the second insulating layer 112 may cover the other side of each of at least one pair of adjacent first circuit patterns 121 . At this time, one of the at least a pair of adjacent first circuit patterns 121 and the other one of the at least a pair of first circuit patterns 121 adjacent to the insulating portion 111P and the second insulating layer 112 are cross-sectional. It can be placed repeatedly in this order at least twice. Each of the at least one pair of adjacent first circuit patterns 121 may have substantially the same line width in the cross-section, and thus the circuit patterns 121 with a constant line width may be repeatedly arranged. For example, in a cross-section, when the line width of each of the adjacent pair of first circuit patterns 121 is W1, the width of the insulating portion 111P is W2, and the width of the second insulating layer 112 is W3. , the line width or width may be repeated at least twice in the order of W1, W2, W1, and W3.

Meanwhile, a seed metal layer (m) may be disposed between one side of each of the adjacent pairs of first circuit patterns 121 facing each other and the insulating portion 111P, while the at least one pair of adjacent first circuit patterns 121 may be disposed between the insulating portion 111P. The seed metal layer m may not be disposed on the other side opposite to one side of each of the patterns 121 and on the upper and lower surfaces.

Meanwhile, the upper surface of each of the plurality of first circuit patterns 121, the upper surface of the second insulating layer 112, and the upper surface of the insulating portion 111P may substantially coplanar with each other. Additionally, the lower surface of each of the plurality of first circuit patterns 121 and the lower surface of the second insulating layer 112 may substantially coplanar with each other.

Meanwhile, the first and second insulating layers 111 and 112 may include different insulating materials. However, it is not limited to this, and may include insulating materials that are substantially the same as each other. Even in this case, interlayer boundaries as described above may exist.

A printed circuit board (100A) according to an example of this structure can be formed through a new process described later, and in this case, unlike conventional SAP, MSAP, ETS, etc., the line/space of the dry film for forming the pattern is 1:1. As described above, for example, it is possible to pattern by exposing and developing to a ratio of approximately 1:3, so it is possible to overcome the limitations of the resolution of exposure equipment, and a separate seed etching process may not be performed, and as a result, A fine circuit with a line/space of, for example, approximately 2㎛/2㎛ or less can be easily formed. In addition, recess steps and circuit thickness deviations that occurred unnecessarily during the ETS seed etching process do not occur, thereby improving product reliability.

Hereinafter, components of the printed circuit board 100A according to an example will be described in more detail with reference to the drawings.

The first and second insulating layers 111 and 112 may each include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material containing an inorganic filler, an organic filler, and/or glass fiber (Glass Fiber, Glass Cloth, Glass Fabric) along with a resin. For example, the insulating material may be a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film) or PPG (Prepreg), but is not limited thereto, and other polymer materials may be used. Additionally, the insulating material may be a photosensitive insulating material such as PID (Photo Imageable Dielectric). The insulating portion 111P may include substantially the same insulating material as the first insulating layer 111.

Each of the plurality of first circuit patterns 121 may include metal. Metals include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and/or alloys thereof. It can be included. Preferably, it may include copper (Cu), but is not limited thereto. The plurality of first circuit patterns 121 may perform various functions depending on the design. For example, it may include a signal pattern. Each of the plurality of first circuit patterns 121 may include an electrolytic plating layer (or electrolytic copper).

The seed metal layer (m) may include metal. Metals include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and/or alloys thereof. It can be included. Preferably, it may include copper (Cu), but is not limited thereto. The seed metal layer (m) may include an electroless plating layer (or chemical copper) or a sputter layer, and may preferably include a sputter layer, but is not limited thereto. The sputter layer may be one layer or multiple layers. The seed metal layer (m) may be distinguished from the plurality of first circuit patterns 121, respectively.

FIGS. 5A to 5K are process diagrams schematically showing an example of manufacturing the printed circuit board of FIGS. 3 and 4.

Referring to the drawings, a method of manufacturing a printed circuit board (100A) according to an example includes forming a first dry film 220 on a detach substrate 210, patterning the first dry film 220, and performing a detach. Forming a plurality of dry film patterns 221 spaced apart from each other on the substrate 210, forming a seed metal layer (m) covering each of the plurality of dry film patterns 221 on the detach substrate 210. Step, forming a first plating layer (M1) on the seed metal layer (m) along the detach substrate 210 and a plurality of dry film patterns 221, forming a first plating layer (M1) on the first plating layer (M1) ) and forming a second insulating layer 112 that fills the space (G1) between the first plating layer (M1), the second insulating layer 112, the first plating layer (M1), and the seed metal layer (m) Polishing at least a portion of each, removing the plurality of dry film patterns 221 remaining between the seed metal layers (m), forming the second insulating layer 112 and the first plating layer on the detach substrate 210. forming a first insulating layer 111 covering (M1) and filling the space (G2) between the seed metal layers (m), removing the detach substrate 210, and removing the seed metal layer (m) and the first insulating layer (111). 1 includes polishing at least a portion of each of the plating layer (M1) and the first insulating layer (111).

Meanwhile, in the step of forming the plurality of dry film patterns 221, when the width on the cross section of each of the plurality of dry film patterns 221 is n, the spacing between the plurality of dry film patterns 221 on the cross section is The distance can practically satisfy 3n. Additionally, in the step of forming the first plating layer (M1), the thickness or width on the cross section of the first plating layer (M1) may substantially satisfy n. For example, even if the first dry film 220 is exposed at a line/space ratio of approximately 1:3, the result is a plurality of first circuit patterns 121 with a line/space ratio of approximately 1:1. Since it can be formed, it may be possible to secure the exposure process margin.

As described above, the printed circuit board (100A) according to an example formed by this manufacturing method is different from the conventional SAP, MSAP, ETS, etc., and the line/space of the dry film for forming a pattern is 1:1 or more, for example, approximately 1:1. Patterning can be done by exposing and developing to a ratio of about 3, so it is possible to overcome the limitations of the resolution of exposure equipment, and a separate seed etching process can not be performed. As a result, the line/space can be, for example, approximately Fine circuits of 2㎛/2㎛ or less can be easily formed. In addition, recess steps and circuit thickness deviations that occurred unnecessarily during the ETS seed etching process do not occur, thereby improving product reliability.

Hereinafter, a method of manufacturing a printed circuit board (100A) according to an example will be described in more detail with reference to the drawings.

Referring to FIG. 5A, a first dry film 220 is formed on the detach substrate 210. The detach substrate 210 may be CCL (Copper Clad Laminate), but is not limited thereto, and various types of carrier substrates capable of detach may be used. The detach substrate 210 may include a detach core 211 and a detach layer 212. The detach core 211 may include an insulating material, and the detach layer 212 may include a metal. If necessary, a release layer may be further disposed between the two. The first dry film 220 may include a positive or negative type photosensitive insulating material.

Referring to FIG. 5B, the first dry film 220 is patterned to form a plurality of dry film patterns 221 spaced apart from each other on the detach substrate 210. Patterning of the first dry film 220 may use a photolithography process, for example, an exposure and development process. At this time, as described above, when the width of each of the plurality of dry film patterns 221 on the cross section is n, the separation distance between the plurality of dry film patterns 221 on the cross section may substantially satisfy 3n. That is, the line/space ratio may be approximately n/3n, but is not limited to this.

Referring to FIG. 5C, a seed metal layer (m) covering each of the plurality of dry film patterns 221 is formed on the detach substrate 210. The seed metal layer (m) may be formed by a sputtering process, but is not limited to this, and may be formed by electroless plating, for example, chemical copper, if necessary. The seed metal layer (m) may be formed to a thin thickness along the detach substrate 210 and the plurality of dry film patterns 221.

Referring to FIG. 5D, a first plating layer (M1) is formed on the seed metal layer (m) along the detach substrate 210 and a plurality of dry film patterns 221. The first plating layer M1 may be formed by electrolytic plating, for example, electrolytic copper. At this time, as described above, the thickness or width on the cross section of the first plating layer M1 may substantially satisfy n. Accordingly, a plurality of first circuit patterns 121 having a line/space ratio of approximately 1:1 can be formed, but the present invention is not limited thereto.

Referring to FIG. 5E, a portion of the first plating layer M1 disposed at both ends of each of the plurality of dry film patterns 221 on a plane is removed. For example, cut etching is performed. Through this, it is possible to prevent the first plating layer M1 from continuing at both ends of each of the plurality of dry film patterns 221. In this process, portions of the seed metal layer (m) disposed at both ends of each of the plurality of dry film patterns 221 on a plane may also be removed. The specific process for this will be described later.

Referring to FIG. 5F, a second insulating layer 112 is formed on the first plating layer M1, covering the first plating layer M1 and filling the space G1 between the first plating layers M1. The second insulating layer 112 may be formed by laminating an uncured film and then curing it, but is not limited thereto. The second insulating layer 112 may entirely cover the surface of the first plating layer (M1).

Referring to FIG. 5G, on the side opposite to the side where the detach substrate 210 is disposed, at least a portion of each of the second insulating layer 112, the first plating layer M1, and the seed metal layer m is polished. For example, at least the plurality of dry film patterns 221 may be polished until they are exposed. If necessary, each of the plurality of dry film patterns 221 may be partially polished. Meanwhile, CMP (Chemical Mechanical Polishing) can be used as a polishing process, but it is not limited to this, and other mechanical and/or chemical planarization processes can also be used.

Referring to FIG. 5H, the plurality of dry film patterns 221 remaining between the seed metal layers (m) are removed. The plurality of dry film patterns 221 can be removed using a known stripping solution, but the present invention is not limited to this and mechanical stripping can also be performed.

Referring to FIG. 5I, the first insulating layer 111 covers the second insulating layer 112 and the first plating layer (M1) on the detach substrate 210 and fills the space (G2) between the seed metal layers (m). ) is formed. The first insulating layer 111 may be formed by laminating uncured films and then curing them, but is not limited thereto. The first insulating layer 111 may entirely cover the exposed surfaces of the second insulating layer 112, the first plating layer M1, and the seed metal layer m.

Referring to FIG. 5J, the detach substrate 210 is removed. For example, the detach substrate 210 can be removed by separating the detach core 211 from the detach layer 212. The remaining detach layer 212 may be removed first, or may be removed in a second polishing step described later.

Referring to FIG. 5K, on the side from which the detach substrate 210 was removed, at least a portion of each of the seed metal layer (m), the first plating layer (M1), and the first insulating layer (111) is polished. For example, they may be polished until at least the second insulating layer 112 is exposed. If necessary, part of the second insulating layer 112 may also be polished. Additionally, the remaining detach layer 212 may also be polished. Meanwhile, CMP can be used as the polishing process, but it is not limited to this, and other mechanical and/or chemical planarization processes can also be used. After polishing, a plurality of first circuit patterns 121 may be formed respectively embedded in the insulating materials 111, 111P, and 112.

Through a series of processes, the printed circuit board 100A according to the above-described example can be formed, and other contents are substantially the same as those described in the printed circuit board 100A according to the above-described example, and there is no overlap therein. The explanation is omitted.

FIGS. 6A to 6E are process diagrams schematically showing an example of the cut etching of FIG. 5E.

Referring to FIG. 6A, as described above with reference to FIGS. 5A to 5D, a first plating layer (M1) is formed along the detach substrate 210 and a plurality of dry film patterns 221 on the seed metal layer (m). form At this time, the first plating layer (M1) and the seed metal layer (m) may be connected to both ends of each of the plurality of dry film patterns 221.

Referring to FIG. 6B, the third dry film 240 is formed on the first plating layer (M1) and then patterned to form the first plating layer (M1) disposed on both ends of each of the plurality of dry film patterns 221. An exposing opening (240h) is formed. The third dry film 240 may include a positive or negative type photosensitive insulating material. The opening 240h may be formed through a photolithography process, such as an exposure and development process.

Referring to FIG. 6C, the continuous portion of the first plating layer M1 exposed through the opening 240h is removed by cut etching. As cut etching, known wet or dry etching can be used. At this time, the continuous portion of the seed metal layer (m) may also be removed.

Referring to FIG. 6D, a thin first plating layer M1 is additionally formed on the seed metal layer m exposed through the opening 240h. The additionally formed first plating layer M1 may be formed using electrolytic plating, for example, electrolytic copper. At this time, the additionally formed first plating layer (M1) may be disconnected from the first plating layer (M1) disposed on the plurality of dry film patterns 221 on the sidewalls of both ends of each of the plurality of dry film patterns 221. .

Referring to FIG. 6E, the third dry film 240 is removed. The third dry film 240 can be removed using a known stripping solution, but is not limited to this, and mechanical peeling may also be performed.

The above-described cut etching may be performed through a series of processes, and through this, the first plating layer (M1) and/or the seed metal layer (m) can be prevented from continuing at both ends of each of the plurality of dry film patterns 221. there is.

Figure 7 is a cross-sectional view schematically showing another example of a printed circuit board.

Figure 8 is a plan view showing a schematic top view of the printed circuit board of Figure 7.

Referring to the drawings, the printed circuit board 100B according to another example includes a second circuit pattern 122 and a pad respectively disposed on the first insulating layer 111 in the printed circuit board 100A according to the above-described example. It further includes a pattern 123. The second circuit pattern 122 may be a general circuit rather than a fine circuit, and therefore may have a wider line width than each of the plurality of first circuit patterns 121 in cross section. The pad pattern 123 may be a pattern in which vias for interlayer connection are connected, and therefore its width in cross section is greater than the line width of each of the plurality of first circuit patterns 121 and/or the line width of the second circuit pattern 122. It could be wider.

Meanwhile, the first insulating layer 111 may be disposed to be spaced apart from both sides of each of the second circuit pattern 122 and the pad pattern 123, and the second insulating layer 112 may be disposed on the second circuit pattern 122. and both sides of each pad pattern 123.

Meanwhile, the upper surface of each of the second circuit patterns 122 and the pad pattern 123 is the upper surface of each of the plurality of first circuit patterns 121, the upper surface of the second insulating layer 112, and the insulating portion 111P. You can substantially co-plan with the upper surface and each other. In addition, the lower surfaces of each of the second circuit patterns 122 and the pad patterns 123 are substantially coplanar with the lower surfaces of each of the plurality of first circuit patterns 121 and the lower surfaces of the second insulating layer 112. can do.

Meanwhile, the seed metal layer m may not be disposed on both sides and the top and bottom surfaces of the second circuit pattern 122 and the pad pattern 123, respectively.

A printed circuit board (100B) according to another example of this structure can be formed through a new process described later, and in this case, it can include both fine circuits and general circuits, so more diverse designs can be possible. Additionally, since it may include a pad pattern, it can be more easily applied to a multilayer substrate.

Hereinafter, components of the printed circuit board 100B according to another example will be described in more detail with reference to the drawings.

The second circuit pattern 122 may include metal. Metals include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and/or alloys thereof. It can be included. Preferably, it may include copper (Cu), but is not limited thereto. The second circuit pattern 122 can perform various functions depending on the design. For example, it may include signal patterns, power patterns, ground patterns, etc. There may be a plurality of second circuit patterns 122, and each of the plurality of second circuit patterns 122 may have various shapes such as a line or a plane. The second circuit pattern 122 may include an electrolytic plating layer (or electrolytic copper).

The pad pattern 123 may include metal. Metals include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and/or alloys thereof. It can be included. Preferably, it may include copper (Cu), but is not limited thereto. The pad pattern 123 can perform various functions depending on the design. For example, it may include a signal pad pattern, a power pad pattern, and a ground pad pattern. There may be a plurality of pad patterns 123 and may be electrically connected to at least one of the plurality of first circuit patterns 121 and second circuit patterns 122. The pad pattern 123 may include an electrolytic plating layer (or electrolytic copper).

Other than that, other contents are substantially the same as those described in the printed circuit board 100A according to the above-described example, and thus redundant description thereof will be omitted.

FIGS. 9A to 9I are process diagrams schematically showing an example of manufacturing the printed circuit board of FIGS. 7 and 8.

Referring to the drawings, the method of manufacturing the printed circuit board 100B according to another example includes, in the method of manufacturing the printed circuit board 100A according to the above-described example, after the step of forming the first plating layer M1, 1 Forming a second dry film 230 on the plating layer (M1), patterning the second dry film 230 to form a plurality of opening patterns 230h exposing the first plating layer (M1), It further includes forming a second plating layer M2 in the plurality of opening patterns 230h and removing the second dry film 230.

Meanwhile, in the step of forming the second insulating layer 112, the second insulating layer 112 further covers the second plating layer (M2) and the space G3 between the second plating layer (M2) and the first and first plating layers (M2). The space (G4) between the two plating layers (M1, M2) can be further filled. Additionally, in the step of polishing at least a portion of each of the second insulating layer 112, the first plating layer M1, and the seed metal layer m, at least a portion of the second plating layer M2 may be further polished. Additionally, in the step of forming the first insulating layer 111, the first insulating layer 111 may further cover the second plating layer M2.

A printed circuit board (100B) according to another example formed by this manufacturing method may include both fine circuits and general circuits, and may include pad patterns, allowing for more diverse designs and enabling more diverse designs than for multi-layer boards. It can be applied easily.

Hereinafter, a method of manufacturing a printed circuit board 100B according to another example will be described in more detail with reference to the drawings.

Referring to FIG. 9A, a plurality of dry film patterns 221, a seed metal layer (m), and a first plating layer (M1) are formed on the detach substrate 210 through substantially the same process as in FIGS. 5A to 5E described above. form

Referring to FIG. 9B, a second dry film 230 is formed on the first plating layer (M1), and the second dry film 230 is patterned to expose a plurality of opening patterns 230h to expose the first plating layer (M1). ), then the second plating layer M2 is formed within the plurality of opening patterns 230h. The second dry film 230 may include a positive or negative type photosensitive insulating material, and may form a plurality of opening patterns 230h through a photolithography process, such as an exposure and development process. The second plating layer M2 may be formed by electrolytic plating, for example, electrolytic copper.

Referring to FIG. 9C, the second dry film 230 is removed. The second dry film 230 can be removed using a known stripping solution, but is not limited to this, and mechanical peeling may also be performed.

Referring to FIG. 9D, the first and second plating layers (M1, M2) are covered on the first and second plating layers (M1, M2), and the space (G1) between the first plating layers (M1) and the second plating layer ( A second insulating layer 112 is formed to fill the space G3 between M2) and the space G4 between the first and second plating layers M1 and M2. The second insulating layer 112 may be formed by laminating an uncured film and then curing it, but is not limited thereto. The second insulating layer 112 may entirely cover the surfaces of the first and second plating layers (M1 and M2).

Referring to FIG. 9E, on the side opposite to the side where the detach substrate 210 is disposed, at least a portion of each of the second insulating layer 112, the first and second plating layers (M1, M2), and the seed metal layer (m) is Polish it. For example, at least the plurality of dry film patterns 221 may be polished until they are exposed. If necessary, each of the plurality of dry film patterns 221 may also be partially polished. Meanwhile, CMP can be used as the polishing process, but it is not limited to this, and other mechanical and/or chemical planarization processes can also be used.

Referring to FIG. 9F, the plurality of dry film patterns 221 remaining between the seed metal layers (m) are removed. The plurality of dry film patterns 221 can be removed using a known stripping solution, but the present invention is not limited to this and mechanical stripping can also be performed.

Referring to FIG. 9g, the second insulating layer 112 and the first and second plating layers (M1, M2) are covered on the detach substrate 210 and the space (G2) between the seed metal layers (m) is filled. 1 Form the insulating layer 111. The first insulating layer 111 may be formed by laminating uncured films and then curing them, but is not limited thereto. The first insulating layer 111 may entirely cover the exposed surfaces of the second insulating layer 112, the first and second plating layers (M1, M2), and the seed metal layer (m).

Referring to FIG. 9H, the detach substrate 210 is removed. For example, the detach substrate 210 can be removed by separating the detach core 211 from the detach layer 212. The remaining detach layer 212 may be removed first, or may be removed in a second polishing step described later.

Referring to FIG. 9I, on the side from which the detach substrate 210 was removed, at least a portion of each of the seed metal layer (m), the first plating layer (M1), and the first insulating layer (111) is polished. For example, at least the second insulating layer 112 and the second plating layer M2 may be polished until they are exposed. If necessary, a portion of each of the second insulating layer 112 and the second plating layer M2 may also be polished. Additionally, the remaining detach layer 212 may also be polished. Meanwhile, CMP can be used as the polishing process, but it is not limited to this, and other mechanical and/or chemical planarization processes can also be used. After polishing, a plurality of first circuit patterns 121, second circuit patterns 122, and pad patterns 123 may be formed respectively embedded in the insulating materials 111, 111P, and 112.

Through a series of processes, a printed circuit board (100B) according to another example described above can be formed, and other details include the manufacturing of the above-described printed circuit boards (100A, 100B) and the above-described printed circuit board (100A). Since it is substantially the same as described in the method, redundant description thereof will be omitted.

Figure 10 is a cross-sectional view schematically showing another example of a printed circuit board.

Referring to the drawings, a printed circuit board (100C) according to another example includes a plurality of build-up insulating layers (110-1, 110-2), a plurality of build-up wiring layers (120-1, 120-2), and a plurality of build-up wiring layers (120-1, 120-2). Includes build-up via layers (130-1, 130-2). At least one (110-1) of the plurality of build-up insulating layers (110-1, 110-2) is the first and second insulating layers (111, 112) of the printed circuit board (100B) according to another example described above. It may include an insulating portion 111P, and at least one of the plurality of build-up wiring layers 120-1 and 120-2 (120-1) is a plurality of components of the printed circuit board 100B according to another example described above. It may include a first circuit pattern 121, a second circuit pattern 122, and a pad pattern 123. The build-up insulating layer 110-1 including the first and second insulating layers 111 and 112 and the insulating portion 111P is located on the outermost layer of the plurality of build-up insulating layers 110-1 and 110-2. It can be arranged, and the build-up wiring layer 120-1 including a plurality of first circuit patterns 121, second circuit patterns 122, and pad patterns 123 is a plurality of wiring layers 120-1, 120- 2) It can be placed on the outermost layer of the middle. For example, the structure of the printed circuit board 100B according to another example described above may be applied as the outermost layer in the structure of a multilayer coreless board of the printed circuit board 100C according to another example.

Meanwhile, the printed circuit board 100C according to another example further includes first and second resist layers 141 and 142 respectively disposed on both sides of the plurality of build-up insulating layers 110-1 and 110-2. can do. The first and second resist layers 141 and 142 are formed at least on each of the build-up wiring layers 120-2 and 120-1 disposed on the outermost sides of the plurality of build-up wiring layers 120-1 and 120-2, respectively. It may have first and second openings 141h and 142h that are partially open.

Meanwhile, the build-up wiring layer 120-1 including a plurality of first circuit patterns 121, second circuit patterns 122, and pad patterns 123 is formed on one side of each of the plurality of first circuit patterns 121. A seed metal layer (m) may be disposed on the top and bottom surfaces of the plurality of first circuit patterns 121, second circuit patterns 122, and pad patterns 123, respectively. On the other hand, among the plurality of build-up wiring layers (120-1, 120-2), except for the above-described build-up wiring layer (120-1), the remaining build-up wiring layers (120-2) have a seed metal layer (seed metal layer) on the upper or lower surface of each circuit pattern. (not shown) may be placed. As described above, the plurality of build-up wiring layers 120-1 and 120-2 have different manufacturing processes, as will be described later, and the arrangement of the seed metal layers may be different.

Hereinafter, components of a printed circuit board 100C according to another example will be described in more detail with reference to the drawings.

Each of the plurality of build-up insulating layers 110-1 and 110-2 may include an insulating material. Insulating materials may include thermosetting resins such as epoxy resins, thermoplastic resins such as polyimide, or materials containing these resins along with inorganic fillers, organic fillers, and/or glass fibers (Glass Fiber, Glass Cloth, Glass Fabric). . For example, the insulating material may be a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film) or PPG (Prepreg), but is not limited thereto, and other polymer materials may be used. Additionally, the insulating material may be a photosensitive insulating material such as PID (Photo Imageable Dielectric).

The build-up insulating layer 110-1 disposed on the outermost layer among the plurality of build-up insulating layers 110-1 and 110-2 may include a plurality of insulating layers 111 and 112 and an insulating portion 111P. there is. The plurality of insulating layers 111 and 112 may include substantially the same insulating material or different insulating materials, and in either case, a boundary between the layers may exist. The insulating layer 111 and the insulating portion 111P may include substantially the same insulating material and may be integrated with each other without boundaries. Among the plurality of build-up insulating layers 110-1 and 110-2, the remaining build-up insulating layers 110-2 may include substantially the same insulating materials, but may include different insulating materials as needed.

Each of the plurality of build-up wiring layers 120-1 and 120-2 may include metal. Metals include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and/or alloys thereof. It can be included. Preferably, it may include copper (Cu), but is not limited thereto. Each of the plurality of build-up wiring layers 120-1 and 120-2 may perform various functions depending on the design. For example, it may include signal patterns, power patterns, ground patterns, etc. Each of these patterns can have various forms such as lines, planes, and pads.

The build-up wiring layer 120-1 disposed on the outermost layer among the plurality of build-up wiring layers 120-1 and 120-2 is disposed on the outermost layer among the plurality of build-up insulating layers 110-1 and 110-2. It may be disposed within the build-up insulating layer 110-1. The remaining build-up wiring layer (120-2) among the plurality of build-up wiring layers (120-1, 120-2) is the remaining build-up insulating layer (110-2) among the plurality of build-up insulating layers (110-1, 110-2), respectively. 2) It can be placed on or within. The build-up wiring layer (120-1) disposed on the outermost layer among the plurality of build-up wiring layers (120-1, 120-2) may include an electrolytic plating layer (or electrolytic copper), and only some of the fine circuits are part of the side surface. It may include a sputter layer and/or an electroless plating layer (or chemical copper) as a seed metal layer. The remaining build-up wiring layer 120-2 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrical copper), respectively. Alternatively, it may include a metal foil (or copper foil) and an electrolytic plating layer (or electrolytic copper). Alternatively, it may include a metal foil (or copper foil), an electroless plating layer (or chemical copper), and an electrolytic plating layer (or electrolytic copper). A sputtering layer may be included instead of an electroless plating layer (or chemical copper), and both may be included if necessary.

Each of the plurality of build-up via layers 130-1 and 130-2 may include metal. Metals include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and/or alloys thereof. It can be included. Preferably, it may include copper (Cu), but is not limited thereto. The plurality of build-up via layers 130-1 and 130-2 may each include a filed via that fills the via hole, but may also include a conformal via arranged along the wall of the via hole. there is. The vias included in each of the plurality of build-up via layers 130-1 and 130-2 may perform various functions depending on the design. For example, it may include ground vias, power vias, signal vias, etc. The vias included in each of the plurality of build-up via layers 130-1 and 130-2 may have a tapered shape in the same direction in cross section.

The build-up via layer (130-1) disposed on the outermost layer among the plurality of build-up via layers (130-1, 130-2) is on the outermost layer among the plurality of build-up insulating layers (110-1, 110-2). It can penetrate the disposed build-up insulating layer 110-1 and be connected to the build-up wiring layer 120-1 disposed on the outermost layer among the plurality of build-up wiring layers 120-1 and 120-2. Among the plurality of build-up via layers (130-1, 130-2), the remaining build-up via layer (130-2) is the remaining build-up insulating layer (110) among the plurality of build-up insulating layers (110-1, 110-2). -2), respectively, and can each be connected to the remaining build-up wiring layer (120-2) among the plurality of build-up wiring layers (120-1, 120-2). The plurality of build-up via layers 130-1 and 130-2 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper), respectively. A sputtering layer may be included instead of an electroless plating layer (or chemical copper), and both may be included if necessary.

The first and second resist layers 141 and 142 may include liquid or film-type solder resist, but are not limited thereto, and other types of insulating materials may be used. A surface treatment layer may be formed on the pattern exposed through the first opening 141h and/or the second opening 142h, if necessary. Alternatively, metal bumps may be formed on the pattern exposed through the first opening 141h and/or the second opening 142h. The second resist layer 142 may be in contact with the second insulating layer 112 and the insulating portion 111P, respectively.

Other contents are substantially the same as those described for the above-mentioned printed circuit boards 100A and 100B, and thus redundant description thereof will be omitted.

FIGS. 11A to 11C are process diagrams schematically showing an example of manufacturing the printed circuit board of FIG. 10.

Referring to the drawings, the method of manufacturing the printed circuit board 100C according to another example is after the step of forming the first insulating layer 111 in the method of manufacturing the printed circuit board 100B according to another example described above. It further includes forming a plurality of build-up insulating layers 110-2, a plurality of build-up wiring layers 120-2, and a plurality of build-up via layers 130-1 and 130-2. For example, the manufacturing method of the printed circuit board 100C according to another example may form a multi-layer coreless substrate before the detach step in the manufacturing method of the printed circuit board 100B according to another example described above, Therefore, the structure of the printed circuit board 100B according to another example described above can be applied as the outermost layer in the structure of a multilayer coreless board of the printed circuit board 100C according to another example.

Meanwhile, a method of manufacturing a printed circuit board (100C) according to another example involves polishing at least a portion of each of the seed metal layer (m), the first plating layer (M1), and the first insulating layer (111), followed by a plurality of build-ups. It may further include forming first and second resist layers 141 and 142 on both sides of the insulating layers 110-1 and 110-2, respectively. In addition, build-up wiring layers 120-2 and 120-1 disposed on the outermost sides of the plurality of build-up wiring layers 120-1 and 120-2 in each of the first and second resist layers 141 and 142, respectively. It may further include forming first and second openings 141h and 142h to open at least a portion of the .

Hereinafter, a method of manufacturing a printed circuit board (100C) according to another example will be described in more detail with reference to the drawings.

Referring to FIG. 11A, first and second insulating layers 111 and 112 and first and second plating layers (M1, M2) and a seed metal layer (m) are formed. Next, a plurality of build-up insulating layers 110-2, a plurality of build-up wiring layers 120-2, and a plurality of build-up via layers 130-1 and 130-2 are formed through a build-up process. The plurality of build-up insulating layers 110-2 can be formed by laminating uncured insulating materials and then curing them, and the plurality of build-up wiring layers 120-2 and the plurality of build-up via layers 130-1, 130-2) can be formed by processing via holes in the first insulating layer 111 and the plurality of build-up insulating layers 110-2 and then using a plating process using SAP, MSAP, tenting, etc.

Referring to FIG. 11B, the detach substrate 210 is removed. For example, the detach substrate 210 can be removed by separating the detach core 211 from the detach layer 212. The remaining detach layer 212 may be removed first, or may be removed in a second polishing step described later. Next, on the side from which the detach substrate 210 was removed, at least a portion of each of the seed metal layer (m), the first plating layer (M1), and the first insulating layer (111) is polished. For example, at least the second insulating layer 112 and the second plating layer M2 may be polished until they are exposed. If necessary, a portion of each of the second insulating layer 112 and the second plating layer M2 may also be polished. Additionally, the remaining detach layer 212 may also be polished. Meanwhile, CMP can be used as the polishing process, but it is not limited to this, and other mechanical and/or chemical planarization processes can also be used. After polishing, a plurality of first circuit patterns 121, second circuit patterns 122, and pad patterns 123 may be formed respectively embedded in the insulating materials 111, 111P, and 112. The build-up insulating layer 110-1 disposed as the outermost layer among the plurality of build-up insulating layers 110-1 and 110-2 may include first and second insulating layers 111 and 112. The build-up wiring layer 120-1 disposed on the outermost layer among the plurality of build-up wiring layers 120-1 and 120-2 includes a plurality of first circuit patterns 121, second circuit patterns 122, and a pad pattern ( 123) may be included.

Referring to FIG. 11C, first and second resist layers 141 and 142 are formed on both sides of the plurality of build-up insulating layers 110-1 and 110-2, respectively. In addition, build-up wiring layers 120-2 and 120-1 disposed on the outermost sides of the plurality of build-up wiring layers 120-1 and 120-2 in each of the first and second resist layers 141 and 142, respectively. First and second openings 141h and 142h are formed to open at least a portion of the openings 141h and 142h. A surface treatment layer may be formed on the pattern exposed through the first opening 141h and/or the second opening 142h. Alternatively, metal bumps may be formed on the pattern exposed through the first opening 141h and/or the second opening 142h.

Through a series of processes, a printed circuit board (100C) according to another example described above can be formed, and other details include the above-described printed circuit boards (100A, 100B, 100C) and the above-described printed circuit boards ( It is substantially the same as that described in the manufacturing method of 100A, 100B), and redundant description thereof will be omitted.

Figure 12 is a cross-sectional view schematically showing another example of a printed circuit board.

Referring to the drawings, a printed circuit board (100D) according to another example includes a plurality of build-up insulating layers (110-1, 110-2, 110-3) and a plurality of build-up wiring layers (120-1, 120-2). , 120-3) and a plurality of build-up via layers (130-1, 130-2, 130-3). At least one (110-1) of the plurality of build-up insulating layers (110-1, 110-2, 110-3) is the first and second insulating layers (111) of the printed circuit board (100B) according to another example described above. , 112) and an insulating portion 111P, and at least one (120-1) of the plurality of build-up wiring layers (120-1, 120-2, 120-3) is a printed circuit according to another example described above. The substrate 100B may include a plurality of first circuit patterns 121, second circuit patterns 122, and pad patterns 123. The build-up insulating layer 110-1 including the first and second insulating layers 111 and 112 and the insulating portion 111P includes a plurality of build-up insulating layers 110-1, 110-2, and 110-3. The build-up wiring layer 120-1, which may be disposed on the inner layer and includes a plurality of first circuit patterns 121, second circuit patterns 122, and pad patterns 123, is a plurality of wiring layers 120-1. , 120-2, 120-3) may be placed in the inner layer. For example, the structure of the printed circuit board 100B according to another example described above may be applied to the inner layer of the multilayer coreless board structure of the printed circuit board 100D according to another example.

Meanwhile, the printed circuit board 100D according to another example includes first and second resist layers 141 and 142 respectively disposed on both sides of the plurality of build-up insulating layers 110-1, 110-2, and 110-3. ) may further be included. The first and second resist layers 141 and 142 are built-up wiring layers 120-2 and 120-3 disposed on the outermost sides of the plurality of build-up wiring layers 120-1, 120-2 and 120-3, respectively. ) It may have first and second openings 141h and 142h that open at least a portion of each.

Meanwhile, the build-up wiring layer 120-1 including a plurality of first circuit patterns 121, second circuit patterns 122, and pad patterns 123 is formed on one side of each of the plurality of first circuit patterns 121. A seed metal layer (m) may be disposed on the top and bottom surfaces of the plurality of first circuit patterns 121, second circuit patterns 122, and pad patterns 123, respectively. On the other hand, among the plurality of build-up wiring layers (120-1, 120-2, 120-3), except for the above-mentioned build-up wiring layer (120-1), the remaining build-up wiring layers (120-2, 120-3) have circuit patterns, respectively. A seed metal layer (not shown) may be disposed on the upper or lower surface of . As described above, the plurality of build-up wiring layers 120-1, 120-2, and 120-3 have different manufacturing processes, as will be described later, and the arrangement of the seed metal layers may be different.

Hereinafter, components of a printed circuit board 100D according to another example will be described in more detail with reference to the drawings.

Each of the plurality of build-up insulating layers 110-1, 110-2, and 110-3 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material containing an inorganic filler, an organic filler, and/or glass fiber (Glass Fiber, Glass Cloth, Glass Fabric) along with a resin. For example, the insulating material may be a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film) or PPG (Prepreg), but is not limited thereto, and other polymer materials may be used. Additionally, the insulating material may be a photosensitive insulating material such as PID (Photo Imageable Dielectric).

Among the plurality of build-up insulating layers 110-1, 110-2, and 110-3, the build-up insulating layer 110-1 disposed on the inner layer includes the plurality of insulating layers 111 and 112 and the insulating portion 111P. It can be included. The plurality of insulating layers 111 and 112 may include substantially the same insulating material or different insulating materials, and in either case, a boundary between the layers may exist. The insulating layer 111 and the insulating portion 111P may include substantially the same insulating material and may be integrated with each other without boundaries. Among the plurality of build-up insulating layers (110-1, 110-2, 110-3), the remaining build-up insulating layers (110-2, 110-3) may include substantially the same insulating materials, but may include different insulating materials. You may.

Each of the plurality of build-up wiring layers 120-1, 120-2, and 120-3 may include metal. Metals include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and/or alloys thereof. It can be included. Preferably, it may include copper (Cu), but is not limited thereto. Each of the plurality of build-up wiring layers 120-1, 120-2, and 120-3 may perform various functions depending on the design. For example, it may include signal patterns, power patterns, ground patterns, etc. Each of these patterns can have various forms such as lines, planes, and pads.

Among the plurality of build-up wiring layers (120-1, 120-2, 120-3), the build-up wiring layer (120-1) disposed on the inner layer is a plurality of build-up insulating layers (110-1, 110-2, 110-3). ) may be disposed within the build-up insulating layer 110-1 disposed on the inner layer. Among the plurality of build-up wiring layers (120-1, 120-2, 120-3), the remaining build-up wiring layers (120-2, 120-3) are each a plurality of build-up insulating layers (110-1, 110-2, 110). -3) may be disposed on or within the remaining build-up insulating layers 110-2 and 110-3. Among the plurality of build-up wiring layers (120-1, 120-2, and 120-3), the build-up wiring layer (120-1) disposed on the inner layer may include an electrolytic plating layer (or electrolytic copper), and only some of the fine circuits are included. A sputter layer and/or electroless plating layer (or chemical copper) may be included as a seed metal layer on a portion of the side surface. The remaining build-up wiring layers 120-2 and 120-3 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrical copper), respectively. Alternatively, it may include a metal foil (or copper foil) and an electrolytic plating layer (or electrolytic copper). Alternatively, it may include a metal foil (or copper foil), an electroless plating layer (or chemical copper), and an electrolytic plating layer (or electrolytic copper). A sputtering layer may be included instead of an electroless plating layer (or chemical copper), and both may be included if necessary.

Each of the plurality of build-up via layers 130-1, 130-2, and 130-3 may include metal. Metals include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and/or alloys thereof. It can be included. Preferably, it may include copper (Cu), but is not limited thereto. The plurality of build-up via layers 130-1, 130-2, and 130-3 may each include a filed via that fills the via hole, but a conformal via is disposed along the wall of the via hole. It may also include . The vias included in each of the plurality of build-up via layers 130-1, 130-2, and 130-3 may perform various functions depending on the design. For example, it may include ground vias, power vias, signal vias, etc. Among the plurality of build-up via layers (130-1, 130-2, 130-3), the build-up via layer (130-1) disposed on the inner layer has a cross-sectional view with the build-up via layer (130-2) disposed below. It may have a tapered shape in the same direction on the cross-section, and may have a tapered shape in the opposite direction on the cross-section as the build-up via layer 130-3 disposed on the upper side.

Among the plurality of build-up via layers (130-1, 130-2, 130-3), the build-up via layer (130-1) disposed on the inner layer is a plurality of build-up insulating layers (110-1, 110-2, 110). -3) It can penetrate the build-up insulating layer 110-1 disposed on the inner layer, and the build-up wiring layer disposed on the inner layer among the plurality of build-up wiring layers 120-1, 120-2, and 120-3 ( 120-1). Among the plurality of build-up via layers (130-1, 130-2, 130-3), the remaining build-up via layers (130-2, 130-3) include a plurality of build-up insulating layers (110-1, 110-2, It can penetrate the remaining build-up insulating layers (110-2, 110-3) among the plurality of build-up wiring layers (110-1, 120-2, 120-3), respectively. 120-2, 120-3) respectively. The plurality of build-up via layers 130-1, 130-2, and 130-3 may each include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). A sputtering layer may be included instead of an electroless plating layer (or chemical copper), and both may be included if necessary.

The first and second resist layers 141 and 142 may include liquid or film-type solder resist, but are not limited thereto, and other types of insulating materials may be used. A surface treatment layer may be formed on the pattern exposed through the first opening 141h and/or the second opening 142h, if necessary. Alternatively, metal bumps may be formed on the pattern exposed through the first opening 141h and/or the second opening 142h.

Other contents are substantially the same as those described for the above-mentioned printed circuit boards 100A, 100B, and 100C, and thus redundant description thereof will be omitted.

FIGS. 13A to 13C are process diagrams schematically showing an example of manufacturing the printed circuit board of FIG. 12.

Referring to the drawings, the method of manufacturing the printed circuit board 100D according to another example is after the step of forming the first insulating layer 111 in the method of manufacturing the printed circuit board 100B according to another example described above. It further includes forming a plurality of build-up insulating layers 110-2, a plurality of build-up wiring layers 120-2, and a plurality of build-up via layers 130-1 and 130-2. In addition, after the step of polishing at least a portion of each of the seed metal layer (m), the first plating layer (M1), and the first insulating layer 111, the remaining plurality of build-up insulating layers 110-3 and the plurality of build-up wiring layers It further includes forming (120-3) and a plurality of build-up via layers (130-3). For example, the manufacturing method of the printed circuit board 100D according to another example can form a multi-layer coreless substrate before and after the detach step in the manufacturing method of the printed circuit board 100B according to another example described above. Therefore, the structure of the printed circuit board 100B according to another example described above can be applied as an inner layer in the structure of a multilayer coreless board of the printed circuit board 100D according to another example.

Meanwhile, a method of manufacturing a printed circuit board (100D) according to another example involves polishing at least a portion of each of the seed metal layer (m), the first plating layer (M1), and the first insulating layer (111), followed by a plurality of build-ups. After forming the insulating layer 110-3, a plurality of build-up wiring layers 120-3, and a plurality of build-up via layers 130-3, a plurality of build-up insulating layers 110-1, 110-2, and 110 are formed. -3) may further include forming first and second resist layers 141 and 142 on both sides, respectively. In addition, the build-up wiring layers 120-2, 120 disposed on the outermost sides of the plurality of build-up wiring layers 120-1, 120-2, and 120-3 in each of the first and second resist layers 141 and 142. -3) It may further include forming first and second openings 141h and 142h to open at least a portion of each.

Hereinafter, a method of manufacturing a printed circuit board (100D) according to another example will be described in more detail with reference to the drawings.

Referring to FIG. 13A, first and second insulating layers 111 and 112 and first and second plating layers (M1, M2) and a seed metal layer (m) are formed. Next, a plurality of build-up insulating layers 110-2, a plurality of build-up wiring layers 120-2, and a plurality of build-up via layers 130-1 and 130-2 are formed through a build-up process. The plurality of build-up insulating layers 110-2 can be formed by laminating uncured insulating materials and then curing them, and the plurality of build-up wiring layers 120-2 and the plurality of build-up via layers 130-1, 130-2) can be formed by processing via holes in the first insulating layer 111 and the plurality of build-up insulating layers 110-2 and then using a plating process using SAP, MSAP, tenting, etc.

Referring to FIG. 13B, the detach substrate 210 is removed. For example, the detach substrate 210 can be removed by separating the detach core 211 from the detach layer 212. The remaining detach layer 212 may be removed first, or may be removed in a second polishing step described later. Next, on the side from which the detach substrate 210 was removed, at least a portion of each of the seed metal layer (m), the first plating layer (M1), and the first insulating layer (111) is polished. For example, at least the second insulating layer 112 and the second plating layer M2 may be polished until they are exposed. If necessary, a portion of each of the second insulating layer 112 and the second plating layer M2 may also be polished. Additionally, the remaining detach layer 212 may also be polished. Meanwhile, CMP can be used as the polishing process, but it is not limited to this, and other mechanical and/or chemical planarization processes can also be used. After polishing, a plurality of first circuit patterns 121, second circuit patterns 122, and pad patterns 123 may be formed respectively embedded in the insulating materials 111, 111P, and 112. The build-up insulating layer 110-1 disposed as the outermost layer among the plurality of build-up insulating layers 110-1 and 110-2 may include first and second insulating layers 111 and 112. The build-up wiring layer 120-1 disposed on the outermost layer among the plurality of build-up wiring layers 120-1 and 120-2 includes a plurality of first circuit patterns 121, second circuit patterns 122, and a pad pattern ( 123) may be included.

Referring to FIG. 13C, a plurality of build-up insulating layers 110-2, a plurality of build-up wiring layers 120-2, and a plurality of build-up via layers 130-1 and 130-2 are formed through the build-up process. On the opposite side, a plurality of remaining build-up insulating layers 110-3, a plurality of build-up wiring layers 120-3, and a plurality of build-up via layers 130-3 are formed. A plurality of build-up insulating layers 110-3 can be formed by laminating uncured insulating materials and then curing them, and a plurality of build-up wiring layers 120-3 and a plurality of build-up via layers 130-3. It can be formed by processing via holes in the plurality of build-up insulating layers 110-3 and then using a plating process using SAP, MSAP, tenting, etc. Next, first and second resist layers 141 and 142 are formed on both sides of the plurality of build-up insulating layers 110-1, 110-2, and 110-3, respectively. In addition, the build-up wiring layers 120-2, 120 disposed on the outermost sides of the plurality of build-up wiring layers 120-1, 120-2, and 120-3 in each of the first and second resist layers 141 and 142. -3) Form first and second openings 141h and 142h that open at least a portion of each. A surface treatment layer may be formed on the pattern exposed through the first opening 141h and/or the second opening 142h. Alternatively, metal bumps may be formed on the pattern exposed through the first opening 141h and/or the second opening 142h.

Through a series of processes, a printed circuit board (100D) according to another example described above can be formed, and other details include the above-described printed circuit boards (100A, 100B, 100C, 100D) and the above-described printed circuit board Since it is substantially the same as described in the manufacturing method of 100A, 100B, and 100C, overlapping description thereof will be omitted.

Figure 14 is a cross-sectional view schematically showing another example of a printed circuit board.

Referring to the drawings, a printed circuit board 500 according to another example includes a core-type first substrate portion 300 and a coreless-type second substrate portion 400 disposed on the first substrate portion 300. Includes. The core-type first substrate 300 includes a core insulating layer 311, a plurality of build-up insulating layers 312, 313, a plurality of core wiring layers 321, 322, and a plurality of build-up wiring layers 323, 324. It may include a core via layer 331 and a plurality of build-up via layers 332 and 333. The coreless type second substrate 400 may include a plurality of build-up insulating layers 411, a plurality of build-up wiring layers 421, and a plurality of build-up via layers 431. At least one of the plurality of build-up insulating layers 411 of the second substrate portion 400 is the first and second insulating layers 111 and 112 of the printed circuit board 100B according to another example described above and the insulating portion ( 111P) may be included. At least one of the plurality of build-up wiring layers 421 of the second substrate portion 400 includes the plurality of first circuit patterns 121 and second circuit patterns 122 of the printed circuit board 100B according to another example described above. and a pad pattern 123. For example, all of the plurality of build-up insulating layers 411 of the second substrate 400 may include first and second insulating layers 111 and 112 and an insulating portion 111P, and may include a plurality of build-up insulating layers 411 of the second substrate 400. The entire build-up wiring layer 421 may include a plurality of first circuit patterns 121, second circuit patterns 122, and pad patterns 123. For example, the structure of the printed circuit board 100B according to another example described above can be applied to all layers of the second substrate 400 in the structure of the multilayer package board of the printed circuit board 100D according to another example. You can. However, it is not limited to this, and may be applied only to some layers, if necessary.

Meanwhile, the printed circuit board 500 according to another example includes first and second outer pads P1 and P2 disposed on the outermost sides of the first and second substrate portions 300 and 400, respectively, and the first and second outer pads P1 and P2. It may further include two resist layers (350, 450). The first resist layer 350 may have a plurality of first openings 350h that expose at least a portion of each of the plurality of first outer pads P1 disposed on the outermost side of the first substrate portion 300. The second resist layer 450 may have one second opening 450h exposing at least a portion of each of the plurality of second outer pads P2 disposed on the outermost side of the second substrate portion 400.

Hereinafter, components of the printed circuit board 500 according to another example will be described in more detail with reference to the drawings.

The first substrate 300 may be a multilayer core type substrate. For example, the first substrate portion 300 penetrates the core insulating layer 311, a plurality of core wiring layers 321 and 322 disposed on both sides of the core insulating layer 311, and the core insulating layer 311, respectively. A core via layer 331 connecting the plurality of core wiring layers 321 and 322, a plurality of build-up insulating layers 312 and 313 respectively disposed on both sides of the core insulating layer 311, and a plurality of build-up insulating layers A plurality of build-up wiring layers (323, 324) respectively disposed on or within (312, 313) and a plurality of build-up wiring layers (323, 324) respectively penetrating at least one of the plurality of build-up insulating layers (312, 313). ) may include a plurality of build-up via layers 332 and 333, each connected to at least one of the following. However, the first substrate 300 may be replaced with a multi-layer coreless type substrate if necessary.

The core insulating layer 311 may include an insulating material. Insulating materials include thermosetting resins such as epoxy resins, thermoplastic resins such as polyimide, materials that are a mixture of these insulating resins with inorganic fillers such as silica, or glass fibers (Glass Fiber, Glass Cloth, Glass Fabric) together with inorganic fillers. A resin impregnated in the core material, for example, an insulating material of CCL (Copper Clad Laminate), may be used, but is not limited thereto. The core insulating layer 311 may be thicker than each of the plurality of build-up insulating layers 312 and 313, but is not limited thereto.

Each of the plurality of build-up insulating layers 312 and 313 may include an insulating material. Insulating materials include thermosetting resins such as epoxy resins, thermoplastic resins such as polyimide, materials in which these insulating resins are mixed with inorganic fillers such as silica, or resins impregnated with core materials such as glass fibers along with inorganic fillers, for example. Insulating materials such as ABF (Ajinomoto Build-up Film), prepreg, and RCC (Resin Coated Copper) may be used, but are not limited thereto. The number of layers of the plurality of build-up insulating layers 312 and 313 is not particularly limited and may be the same, but is not limited thereto.

Each of the plurality of core wiring layers 321 and 322 may include metal. Metals such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof can be used. It may include copper (Cu), but is not limited thereto. The plurality of core wiring layers 321 and 322 may each include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper), but are not limited thereto. A sputtering layer may be formed instead of an electroless plating layer, and both may be included. Additionally, copper foil may be further included. The plurality of core wiring layers 321 and 322 may perform various functions depending on the design of each layer. For example, it may include a ground pattern, power pattern, signal pattern, etc. These patterns may include line patterns, plain patterns, and/or pad patterns, respectively.

Each of the plurality of build-up wiring layers 323 and 324 may include metal. Metals such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof can be used. It may include copper (Cu), but is not limited thereto. The plurality of build-up wiring layers 323 and 324 may each include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper), but are not limited thereto. A sputtering layer may be formed instead of an electroless plating layer, and both may be included. Additionally, copper foil may be further included. The plurality of build-up wiring layers 323 and 324 may perform various functions depending on the design of each layer. For example, it may include a ground pattern, power pattern, signal pattern, etc. These patterns may include line patterns, plain patterns, and/or pad patterns, respectively.

The core via layer 331 may include a through via. The through via may include a metal layer formed on the wall of the through hole and a plug that fills the metal layer. The metal layer may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. It may include copper (Cu), but is not limited thereto. The plug may contain ink as an insulating material. The metal layer may include, but is not limited to, an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). A sputtering layer may be formed instead of the electroless plating layer, and both may be included. The through via layer 331 can perform various functions depending on the design. For example, it may include ground vias, power vias, signal vias, etc.

The plurality of build-up via layers 332 and 333 may include micro vias. Micro vias may be field vias that fill a via hole or conformal vias arranged along the wall of the via hole. Micro vias may be arranged as a stacked type and/or a staggered type. The plurality of build-up via layers 332 and 333 may each include a metal, and the metal may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), and nickel (Ni). ), lead (Pb), titanium (Ti), or alloys thereof, and preferably copper (Cu), but is not limited thereto. The plurality of build-up via layers 332 and 333 may each include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper), but are not limited thereto. A sputtering layer may be formed instead of an electroless plating layer, and both may be included. The plurality of build-up via layers 332 and 333 may perform various functions depending on the design of the corresponding layer. For example, it may include ground vias, power vias, signal vias, etc.

The second substrate portion 400 may be a coreless type multilayer build-up substrate including a microcircuit. For example, the second substrate 400 includes a plurality of build-up insulating layers 411, a plurality of build-up wiring layers 421 respectively disposed within the plurality of build-up insulating layers 411, and a plurality of build-up insulating layers. It may include a plurality of build-up via layers 431 that each penetrate at least one of the plurality of build-up wiring layers 411 and are respectively connected to at least one of the plurality of build-up wiring layers 421.

Each of the plurality of build-up insulating layers 411 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material containing an inorganic filler, an organic filler, and/or glass fiber (Glass Fiber, Glass Cloth, Glass Fabric) along with a resin. For example, the insulating material may be a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film) or PPG (Prepreg), but is not limited thereto, and other polymer materials may be used. Additionally, the insulating material may be a photosensitive insulating material such as PID (Photo Imageable Dielectric).

At least one of the plurality of build-up insulating layers 411 may include a plurality of insulating layers 111 and 112 and an insulating portion 111P. For example, the entire build-up insulating layer 411 may include a plurality of insulating layers 111 and 112 and an insulating portion 111P, respectively. The plurality of insulating layers 111 and 112 may include substantially the same insulating material or different insulating materials, and in either case, a boundary between the layers may exist. The insulating layer 111 and the insulating portion 111P may include substantially the same insulating material and may be integrated with each other without boundaries.

Each of the plurality of build-up wiring layers 421 may include metal. Metals include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and/or alloys thereof. It can be included. Preferably, it may include copper (Cu), but is not limited thereto. Each of the plurality of build-up wiring layers 421 may perform various functions depending on the design. For example, it may include signal patterns, power patterns, ground patterns, etc. Each of these patterns can have various forms such as lines, planes, and pads.

At least one of the plurality of build-up wiring layers 421 may include a plurality of first circuit patterns 121, second circuit patterns 122, and pad patterns 123. For example, the entire build-up wiring layer 421 may include a plurality of first circuit patterns 121, second circuit patterns 122, and pad patterns 123, respectively. Each of the plurality of build-up wiring layers 421 may include an electrolytic plating layer (or electrolytic copper), and only some of the fine circuits, such as the first circuit pattern 121, may have a sputter layer and/or an electroless plating layer ( or chemical copper) may be included as a seed metal layer.

Each of the plurality of build-up via layers 431 may include metal bumps 131 that fill the via holes. Each metal bump 131 may contain metal. Metals include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and/or alloys thereof. It can be included. Preferably, it may include copper (Cu), but is not limited thereto. A low melting point metal 132, such as solder, may be disposed on each metal bump 131. Each metal bump 131 can perform various functions depending on its design. For example, it may include a metal bump for ground, a metal bump for power, a metal bump for signal, etc.

The plurality of build-up via layers 431 may each penetrate the first insulating layer 111 among the plurality of build-up insulating layers 411 and may be connected to the pad pattern 123 among the plurality of build-up wiring layers 421. You can. For example, each metal bump 131 may be directly connected to the lower pad pattern 123. Additionally, each metal bump 131 may be connected to the upper pad pattern 123 and the low melting point metal 132.

Metal bumps 335 and low melting point metal 336 may also be formed in the outermost layer of the first substrate 300 connected to the second substrate 400 . The metal bump 335 and the low melting point metal 336 may be substantially the same as those described for the metal bump 131 and the low melting point metal 132.

The first and second resist layers 350 and 450 may include liquid or film-type solder resist, but are not limited thereto, and other types of insulating materials may be used. A first surface treatment layer may be disposed on each of the plurality of first outer pads P1 exposed through the plurality of first openings 350h. A second surface treatment layer may be disposed on each of the plurality of second outer pads P2 exposed through one second opening 450h.

The first and second outer pads P1 and P2 may each include metal. Metals include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and/or alloys thereof. It can be included. Preferably, it may include copper (Cu), but is not limited thereto. The first and second outer pads (P1, P2) can each perform various functions depending on their design. For example, it may include an outer pad for ground, an outer pad for power, an outer bump for signals, etc. The first and second outer pads P1 and P2 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper), respectively, but are not limited thereto. A sputtering layer may be formed instead of an electroless plating layer, and both may be included. Additionally, copper foil may be further included. The first and second outer pads P1 and P2 may each include a pattern portion, and at least a portion may further include a via portion.

The first and second surface treatment layers are not particularly limited as long as they are known in the art, and include, for example, electrolytic gold plating, electroless gold plating, OSP (Organic Solderability Preservative) or electroless tin plating, electroless silver plating, and electroless plating. It may be formed by nickel plating/substitution gold plating, DIG (Direct Immersion Gold) plating, HASL (Hot Air Solder Leveling), etc., but is not limited thereto.

Other contents are substantially the same as those described for the above-mentioned printed circuit boards 100A, 100B, 100C, and 100D, and redundant description thereof will be omitted.

Figures 15A to 15F are process charts schematically showing an example of manufacturing the printed circuit board of Figure 14.

Referring to the drawings, a method of manufacturing a printed circuit board 500 according to another example includes preparing a core type first substrate portion 300 and preparing a coreless type second substrate portion 400. , and collectively stacking the first and second substrate parts 300 and 400. The step of preparing the second substrate portion 400 includes metal bumps 131 penetrating the first insulating layer 111 and connected to the pad pattern 123 in the structure of the printed circuit board 100B according to another example described above. and a plurality of substrates on which a low melting point metal 132 disposed on the metal bump 131 is further formed. For example, in the method of manufacturing these substrates, after forming the first insulating layer 111 in the method of manufacturing the printed circuit board 100B according to another example described above, the first insulating layer 111 is 2 Forming an opening 111h exposing the plating layer M2, forming a metal bump 131 in the opening 111h, and forming a low melting point metal 132 on the metal bump 131. may further include. Therefore, the structure of the printed circuit board 100B according to another example described above can be applied to all layers of the second substrate portion 400 in the structure of the multilayer package board of the printed circuit board 100D according to another example. .

Meanwhile, a method of manufacturing a printed circuit board 500 according to another example includes forming first and second outer pads P1 and P2 on the first and second substrate parts 300 and 400, respectively, after the batch stacking step. and forming first and second resist layers 350 and 450. In addition, forming first and second openings 350h and 450h in the first and second resist layers 350 and 450, respectively, may be further included.

Hereinafter, a method of manufacturing a printed circuit board 500 according to another example will be described in more detail with reference to the drawings.

Referring to FIG. 15A, first and second insulating layers 111 and 112 and first and second plating layers (M1, M2) and a seed metal layer (m) are formed. Next, an opening 111h is formed in the first insulating layer 111 to expose the second plating layer M2. The opening 111h may be formed through a photolithography process if the first insulating layer 111 includes a photosensitive insulating material, and may be formed through a laser process if the first insulating layer 111 includes a non-photosensitive insulating material. .

Referring to FIG. 15B, a metal bump 131 is formed within the opening 111h, and a low melting point metal 132 is formed on the metal bump 131. The metal bump 131 may be formed by electrolytic plating, for example, electrolytic copper, but is not limited thereto. The low melting point metal 132 can be formed by various known methods such as coating and plating.

Referring to FIG. 15C, the detach substrate 210 is removed. For example, the detach substrate 210 can be removed by separating the detach core 211 from the detach layer 212. The remaining detach layer 212 may be removed first, or may be removed in a second polishing step described later. Next, on the side from which the detach substrate 210 was removed, at least a portion of each of the seed metal layer (m), the first plating layer (M1), and the first insulating layer (111) is polished. For example, the second insulating layer 112 and the second plating layer M2 may be polished until they are exposed. If necessary, a portion of each of the second insulating layer 112 and the second plating layer M2 may also be polished. Additionally, the remaining detach layer 212 may also be polished. Meanwhile, CMP can be used as the polishing process, but it is not limited to this, and other mechanical and/or chemical planarization processes can also be used. During the polishing process, the opposite side can be protected with a mask film 250. After polishing, a plurality of first circuit patterns 121, second circuit patterns 122, and pad patterns 123 may be formed respectively embedded in the insulating materials 111, 111P, and 112. Additionally, metal bumps 131 and low melting point metal 132 may be formed on the pad pattern 123.

Referring to FIGS. 15D and 15E, a double-sided build-up process is performed focusing on a core material such as CCL to prepare a core-type first substrate 300 with the above-described structure, and a first substrate 300 is placed on the first substrate 300. A second substrate portion 400 including a plurality of substrates manufactured through FIGS. 15A to 15C described above is placed, and then they are collectively stacked using cover films 610 and 620. Meanwhile, metal bumps 335 and low melting point metal 336 may also be formed in the outermost layer of the first substrate 300 connected to the second substrate 400. Through this batch stacking, a multilayer package substrate structure in which the core-type second substrate portion 400 is disposed on the core-type first substrate portion 300 can be formed.

Referring to FIG. 15F, first and second outer pads P1 and P2 and first and second resist layers 350 and 450 are formed on the outermost layers of the first and second substrate parts 300 and 400, respectively. In addition, first and second openings 350h and 450h are formed in the first and second resist layers 350 and 450, respectively, to expose at least a portion of the first and second outer pads P1 and P2, respectively. . The first and second outer pads (P1, P2) can be formed through a plating process using SAP, MSAP, tenting, etc. The first and second resist layers 350 and 450 can be formed by applying solder resist and then curing it, or by laminating film-type solder resist and then curing it. The first and second openings 350h and 450h may be formed through a photolithography process. If necessary, a first surface treatment layer may be formed on each of the plurality of first outer pads (P1) exposed through the plurality of first openings 350h, and each of the first surface treatment layers exposed through the single second opening 450h may be formed. A second surface treatment layer may be formed on each of the plurality of second outer pads (P2).

Through a series of processes, a printed circuit board 500 according to another example described above can be formed, and other details include the above-described printed circuit boards 100A, 100B, 100C, 100D, 500 and the above-described printing method. This method is substantially the same as that described in the manufacturing method of the circuit boards 100A, 100B, 100C, and 100D, so overlapping description thereof will be omitted.

In the present disclosure, the expression to cover may include not only the case of covering entirely but also the case of covering at least part of the case, and may also include the case of covering indirectly as well as the case of directly covering.

In the present disclosure, the expression to fill may include not only completely filling but also approximately filling, and may include, for example, cases where some voids or voids exist.

In the present disclosure, thickness, width, line width, etc. can be measured using a scanning microscope or optical microscope based on the polished or cut cross section of the printed circuit board. If the thickness, width, line width, etc. are not constant, the thickness, width, line width, etc. can be compared with the average value of the values measured at five arbitrary points.

In the present disclosure, the judgment can actually include process errors, position deviations, errors during measurement, etc. that occur during the manufacturing process. For example, having substantially the same line width may include not only being completely numerically identical, but also having approximately similar values within an error range. In addition, substantially coplanar may include not only the case of being completely on the same plane, but also the case of being approximately on the same plane.

In the present disclosure, the same insulating material may mean not only the exact same insulating material but also the same type of insulating material. Accordingly, the composition of the insulating materials is substantially the same, but their specific composition ratios may vary slightly.

In the present disclosure, the meaning of cross-section may mean the cross-sectional shape when the object is cut vertically, the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed from a side view. In addition, the meaning on a plane may mean a planar shape when the object is cut horizontally, or a planar shape when the object is viewed from a top-view or bottom-view.

In the present disclosure, lower, lower, bottom, etc. are used for convenience to mean a downward direction based on the cross section of the drawing, and upper, upper, upper, etc. are used to mean the opposite direction. However, this direction is defined for convenience of explanation, and the scope of the patent claims is not particularly limited by the description of this direction, and the concept of top/bottom can change at any time.

In the present disclosure, the meaning of connected is a concept that includes not only directly connected, but also indirectly connected through an adhesive layer or the like. In addition, the meaning of being electrically connected is a concept that includes both cases where it is physically connected and cases where it is not connected. In addition, expressions such as first, second, etc. are used to distinguish one component from another component and do not limit the order and/or importance of the components. In some cases, the first component may be named the second component, and similarly, the second component may be named the first component without departing from the scope of rights.

The expression 'example' used in the present disclosure does not mean identical embodiments, but is provided to emphasize and explain different unique features. However, the examples presented above do not exclude being implemented in combination with features of other examples. For example, even if a matter explained in a specific example is not explained in another example, it can be understood as an explanation related to the other example, as long as there is no explanation contrary to or contradictory to the matter in the other example.

The terminology used in this disclosure is used to describe examples only and is not intended to limit the disclosure. At this time, singular expressions include plural expressions, unless the context clearly indicates otherwise.

1000: Electronic devices
1010: Motherboard
1020: Chip related parts
1030: Network related parts
1040: Other parts
1050: Camera
1060: Antenna
1070: display
1080: Battery
1090: signal line
1100: Smartphone
1110: motherboard
1120: parts
1121: Parts package
1130: Camera module
1140: Speaker
100A, 100B, 100C, 100D: printed circuit board
110-1, 110-2, 110-3: Build-up insulating layer
111: first insulating layer
111P: insulation part
112: second insulating layer
120-1, 120-2, 120-3: Build-up wiring layer
121: First circuit pattern
122: Second circuit pattern
123: Pad pattern
130-1, 130-2, 130-3: Build-up via layer
131: Metal bump
132: low melting point metal
141: first resist layer
142: second resist layer
141h: first opening
142h: second opening
210: Detach substrate
211: Detach Core
212: Detach layer
220: first dry film
221: Multiple dry film patterns
230: second dry film
230h: Aperture pattern
240: Third dry film
240h: opening
250: mask film
m: seed metal layer
M1: first plating layer
M2: second plating layer
G1, G2, G3: space
500: printed circuit board
300: first substrate portion
311: core insulation layer
312, 313: build-up insulating layer
321, 322: Core wiring layer
323, 324: build-up wiring layer
331: Core via layer
332, 333: Build-up via layer
350: first resist layer
350h: first opening
400: second substrate portion
411: build-up insulating layer
421: Build-up wiring layer
431: Build-up via layer
450: second resist layer
450h: second opening
P1: 1st outer pad
P2: Second outer pad
610, 620: Cover film

Claims (34)

first insulating layer;
a plurality of first circuit patterns each disposed on the first insulating layer;
a second insulating layer disposed on the first insulating layer and covering a portion of a side surface of each of the plurality of first circuit patterns; and
an insulating portion disposed between at least one pair of adjacent first circuit patterns among the plurality of first circuit patterns and integrated with the first insulating layer; Including,
Printed circuit board.
According to claim 1,
The insulating portion is arranged such that a portion of the first insulating layer extends between the at least one pair of adjacent first circuit patterns,
Printed circuit board.
According to claim 1,
A boundary exists between the first insulating layer and the second insulating layer,
There is no boundary between the first insulating layer and the insulating part,
Printed circuit board.
According to claim 1,
The insulating portion is disposed between one side of each of the adjacent pairs of first circuit patterns, and the second insulating layer is located on an opposite side of the one side of each of the adjacent pairs of first circuit patterns. which covers the other side,
Printed circuit board.
According to claim 4,
A seed metal layer is disposed between one side of each of the at least one pair of adjacent first circuit patterns and the insulating portion,
Printed circuit board.
According to claim 5,
The seed metal layer is not disposed on the other side, upper surface, and lower surface of each of the at least one pair of adjacent first circuit patterns,
Printed circuit board.
According to claim 6,
The upper surface of each of the plurality of first circuit patterns, the upper surface of the second insulating layer, and the upper surface of the insulating portion are substantially coplanar with each other,
The lower surface of each of the plurality of first circuit patterns and the lower surface of the second insulating layer are substantially coplanar with each other.
Printed circuit board.
According to claim 4,
In cross-section, one of the at least one pair of adjacent first circuit patterns, the insulating portion, the other one of the at least one pair of adjacent first circuit patterns, and the second insulating layer are repeatedly arranged in this order. felled,
Printed circuit board.
According to claim 8,
In the repetitive arrangement on the cross-section, the line widths of one and the other of the at least one pair of adjacent first circuit patterns are respectively W1, the width of the insulating portion is W2, and the width of the second insulating layer is W3. When the line width or width is repeated in the order of W1, W2, W1, W3,
Printed circuit board.
According to claim 1,
The first and second insulating layers include different insulating materials,
Printed circuit board.
According to claim 1,
The first and second insulating layers include substantially the same insulating materials as each other,
Printed circuit board.
According to claim 4,
a second circuit pattern disposed on the first insulating layer and having a wider line width than each of the plurality of first circuit patterns in cross section; It further includes,
The insulating portion is disposed to be spaced apart from both sides of the second circuit pattern, and the second insulating layer covers both sides of the second circuit pattern.
Printed circuit board.
According to claim 12,
a pad pattern disposed on the first insulating layer; It further includes,
The insulating portion is disposed to be spaced apart from both sides of the pad pattern, and the second insulating layer covers both sides of the pad pattern.
Printed circuit board.
According to claim 13,
The printed circuit board includes a plurality of build-up insulating layers, a plurality of build-up wiring layers, and a plurality of build-up via layers,
At least one build-up insulating layer among the plurality of build-up insulating layers includes the first and second insulating layers and the insulating portion,
At least one build-up wiring layer among the plurality of build-up wiring layers includes the plurality of first circuit patterns, the second circuit patterns, and the pad pattern,
Printed circuit board.
According to claim 14,
The build-up wiring layer including the plurality of first circuit patterns, the second circuit pattern, and the pad pattern includes a seed metal layer disposed on one side of each of the plurality of first circuit patterns, and the plurality of first circuit patterns and the pad pattern. A seed metal layer is not disposed on the upper and lower surfaces of each of the second circuit pattern and the pad pattern,
Among the plurality of build-up wiring layers, except for the build-up wiring layer including the plurality of first circuit patterns, the second circuit pattern, and the pad pattern, the remaining build-up wiring layers have a seed metal layer disposed on the upper or lower surface of each circuit pattern. ,
Printed circuit board.
According to claim 14,
The build-up insulating layer including the first and second insulating layers and the insulating portion is disposed on an outermost layer among the plurality of build-up insulating layers,
The build-up wiring layer including the plurality of first circuit patterns, the second circuit pattern, and the pad pattern is disposed on the outermost layer of the plurality of wiring layers,
Printed circuit board.
According to claim 16,
The printed circuit board further includes a resist layer disposed on the build-up insulating layer disposed on an outermost layer among the plurality of build-up insulating layers,
The resist layer is in contact with the second insulating layer and the insulating portion, respectively.
Printed circuit board.
According to claim 14,
The build-up insulating layer including the first and second insulating layers and the insulating portion is disposed on an inner layer among the plurality of build-up insulating layers,
A build-up wiring layer including the plurality of first circuit patterns, the second circuit pattern, and the pad pattern is disposed on an inner layer of the plurality of wiring layers,
Printed circuit board.
According to claim 13,
The printed circuit board is a core-type first substrate portion, and a coreless type disposed on the first substrate portion and includes a plurality of build-up insulating layers, a plurality of build-up wiring layers, and a plurality of build-up via layers. 2 It includes a substrate part,
At least one build-up insulating layer among the plurality of build-up insulating layers includes the first and second insulating layers and the insulating portion,
At least one build-up wiring layer among the plurality of build-up wiring layers includes the plurality of first circuit patterns, the second circuit patterns, and the pad pattern,
Printed circuit board.
According to claim 19,
All layers of the plurality of build-up insulating layers include the first and second insulating layers and the insulating portion,
All layers of the plurality of build-up wiring layers include the plurality of first circuit patterns, the second circuit patterns, and the pad pattern,
Printed circuit board.
insulation material; and
a plurality of first circuit patterns each embedded in the insulating material; Includes,
A seed metal layer is disposed on one side facing each other of at least one pair of adjacent first circuit patterns among the plurality of first circuit patterns, but the seed metal layer is not disposed on the other side opposite to the one side,
Printed circuit board.
According to claim 21,
The seed metal layer is not disposed on the upper and lower surfaces of each of the at least one pair of adjacent first circuit patterns,
Printed circuit board.
According to claim 22,
a second circuit pattern embedded in the insulating material; and
a pad pattern embedded in the insulating material; It further includes,
The seed metal layer is not disposed on both sides and bottom of each of the second circuit pattern and the pad pattern,
Printed circuit board.
Forming a first dry film on a detach substrate;
patterning the first dry film to form a plurality of dry film patterns spaced apart from each other on the detach substrate;
forming a seed metal layer covering each of the plurality of dry film patterns on the detach substrate;
forming a first plating layer on the seed metal layer along the detach substrate and the plurality of dry film patterns;
forming a second insulating layer on the first plating layer, covering the first plating layer and filling the space between the first plating layers;
polishing at least a portion of each of the second insulating layer, the first plating layer, and the seed metal layer;
removing the plurality of dry film patterns remaining between the seed metal layers;
forming a first insulating layer on the detach substrate, covering the second insulating layer and the first plating layer and filling a space between the seed metal layers;
removing the detach substrate; and
polishing at least a portion of each of the seed metal layer, the first plating layer, and the first insulating layer; Including,
Manufacturing method of printed circuit board.
According to claim 24,
In the step of forming the plurality of dry film patterns, when the width on the cross section of each of the plurality of dry film patterns is n, the separation distance between the plurality of dry film patterns on the cross section substantially satisfies 3n,
Manufacturing method of printed circuit boards.
According to claim 25,
In the step of forming the first plating layer, the thickness or width on the cross section of the first plating layer substantially satisfies n,
Manufacturing method of printed circuit boards.
According to claim 24,
Polishing of each of the second insulating layer, the first plating layer, and the seed metal layer is performed until at least the plurality of dry film patterns are exposed on the side opposite to the side on which the detach substrate is disposed,
Polishing of each of the seed metal layer, the first plating layer, and the first insulating layer is performed until at least the second insulating layer is exposed on the side from which the detach substrate was removed.
Manufacturing method of printed circuit boards.
According to claim 24,
After forming the first plating layer,
removing portions of the first plating layer and the first seed metal layer disposed at both ends of each of the plurality of dry film patterns on a plane; Containing more,
Manufacturing method of printed circuit boards.
According to claim 24,
After forming the first plating layer,
forming a second dry film on the first plating layer;
patterning the second dry film to form a plurality of opening patterns exposing the first plating layer;
forming a second plating layer within the plurality of opening patterns; and
removing the second dry film; Containing more,
Manufacturing method of printed circuit board.
According to clause 29,
In forming the second insulating layer, the second insulating layer further covers the second plating layer and further fills the space between the second plating layers and the space between the first and second plating layers,
In the step of polishing at least a portion of each of the second insulating layer, the first plating layer, and the seed metal layer, at least a portion of the second plating layer is further polished,
In forming the first insulating layer, the first insulating layer further covers the second plating layer,
Manufacturing method of printed circuit boards.
According to claim 30,
After forming the first insulating layer,
forming a plurality of first build-up insulating layers, a plurality of first build-up wiring layers, and a plurality of first build-up via layers; Containing more,
Manufacturing method of printed circuit board.
According to claim 31,
After polishing at least a portion of each of the seed metal layer, the first plating layer, and the first insulating layer,
A plurality of second build-up insulating layers, a plurality of second build-up wiring layers, and a plurality of second build-up insulating layers on a side opposite to the side on which the plurality of first build-up insulating layers, the plurality of first build-up wiring layers, and the plurality of first build-up via layers are formed. forming a second build-up via layer; Containing more,
Manufacturing method of printed circuit board.
According to claim 30,
After forming the first insulating layer,
forming an opening in the first insulating layer to expose the second plating layer;
forming metal bumps within the opening; and
forming a low melting point metal on the metal bump; Containing more,
Manufacturing method of printed circuit board.
According to claim 33,
The method of manufacturing the printed circuit board includes preparing a core-type first substrate portion and a coreless-type second substrate portion and then stacking the first and second substrate portions in batches,
The second substrate unit includes a plurality of substrates formed through the above steps,
Manufacturing method of printed circuit boards.

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