KR20240066656A - Test Board And Test Apparatus Using The Same - Google Patents

Abstract

The purpose of the present invention is to provide a test board and a test device using the same that can generate a test pattern by selectively using vector pattern data stored in a vector pattern memory and auxiliary pattern data stored in an auxiliary pattern memory. To this end, the test board according to the present invention includes a receiving unit that receives vector pattern data and auxiliary pattern data; a vector pattern memory storing the vector pattern data and selection signals; an auxiliary pattern memory storing the auxiliary pattern data; a selection unit that selects the vector pattern data or the auxiliary pattern data according to a selection signal received from the vector pattern memory; and an output unit that generates test patterns using the pattern data received from the selection unit and outputs the test patterns to the device under test.

Description

Test Board And Test Apparatus Using The Same}

The present invention relates to a test board and a test device using the same.

Test equipment is used to test the performance of memory devices or semiconductor devices. The memory device or semiconductor device tested by the test device is referred to as the device under test.

The test board provided in the test device generates various test patterns and transmits them to the device under test, analyzes the performance of the device under test by analyzing the patterns and various signals received from the device under test, and provides the analysis results to the user. can be provided.

The test board can generate test patterns using pattern data stored in the vector pattern memory (VPM) of the test board.

Therefore, when the test patterns to be transmitted to the device under test are changed, the pattern data stored in the vector pattern memory (VPM) of the test board must be changed.

However, since the total capacity of the pattern data stored in the vector pattern memory (VPM) is very large, a lot of time is required to change all the pattern data stored in the vector pattern memory (VPM).

That is, when the pattern data stored in the vector pattern memory is changed, recompilation and reload of the vector pattern memory are required, which requires a lot of time.

In particular, even if only part of the pattern data stored in the vector pattern memory is changed, recompilation and reload of the entire vector pattern memory are required, so the device under test can be detected by a conventional test board and a test device using the same. It is difficult to conduct rapid testing for them.

The purpose of the present invention to solve the above-mentioned problems is to provide a test board that can generate a test pattern by selectively using vector pattern data stored in the vector pattern memory and auxiliary pattern data stored in the auxiliary pattern memory. and providing a test device using the same.

A test board according to the present invention for achieving the above-described purpose includes a receiving unit that receives vector pattern data and auxiliary pattern data; a vector pattern memory storing the vector pattern data and selection signals; an auxiliary pattern memory storing the auxiliary pattern data; a selection unit that selects the vector pattern data or the auxiliary pattern data according to a selection signal received from the vector pattern memory; and an output unit that generates test patterns using the pattern data received from the selection unit and outputs the test patterns to the device under test.

The receiving unit changes the raw pattern data received through an external system into the vector pattern data that can be used in the vector pattern memory through a compilation process and then transmits the vector pattern data to the vector pattern memory, or The vector pattern data received through a compilation process from an external system is transmitted to the vector pattern memory.

The auxiliary pattern data is used to generate test patterns containing correction information to be input to the device under test, or to generate test patterns to change the ID of the device under test.

The vector pattern memory includes: a data memory storing the vector pattern data; and storing selection signals to control the selection unit.

When the first selection signal is received from the selection signal memory at the k-th timing, the selection unit transmits the vector pattern data to the first to m-th pins connected to the output unit, and at the k-th timing. , when the second selection signal is received from the selection signal memory, the auxiliary pattern data is transmitted to the first to mth pins.

The vector pattern memory includes the first selection signal or the second selection signal to be transmitted to the selection unit at the k-th timing, and the first to m-th selection signals to be transmitted to the first to m-th pins at the k-th timing. It is matched with vector pattern data and stored.

The number of auxiliary pattern sets including the auxiliary pattern data to be transmitted to the first to mth pins corresponds to the number of second selection signals.

A test device according to the present invention for achieving the above-described object includes the test board; a high-fix board connected to the test board; a probe interface board connected to the hyfix board; and a pogo board that transmits the test patterns received from the test board through the hyfix board and the probe interface board to the device under test.

According to the present invention, vector pattern data is stored in a vector pattern memory that requires recompilation and reload when the stored data is changed, and the auxiliary pattern data to be used in place of some of the vector pattern data is an auxiliary pattern that can be quickly uploaded. It can be stored in memory, and vector pattern data and auxiliary pattern data can be selectively used to generate test patterns.

Therefore, according to the present invention, when a change in some of the test patterns is required, auxiliary pattern data can be quickly stored in the auxiliary memory. Accordingly, rapid testing of the device under test can be performed.

1 is an exemplary diagram showing a test system to which a test device according to the present invention is applied.
Figure 2 is an exemplary diagram showing the configuration of a test board according to the present invention.
Figure 3 is an example diagram showing pattern data generated from a test board according to the present invention.

Like reference numerals refer to substantially the same elements throughout the specification. In the following description, detailed descriptions of configurations and functions that are not related to the core configuration of the present invention and are known in the technical field of the present invention may be omitted. The meaning of terms described in this specification should be understood as follows.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. The present embodiments only serve to ensure that the disclosure of the present invention is complete and that common knowledge in the technical field to which the present invention pertains is not limited. It is provided to fully inform those who have the scope of the invention.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

When 'includes', 'has', 'consists of', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on the top', 'on the bottom', 'next to', etc., 'immediately' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

In the case of a description of a temporal relationship, for example, if a temporal relationship is described as 'after', 'successfully after', 'after', 'before', etc., 'immediately' or 'directly' Unless used, non-consecutive cases may also be included.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

"X-axis direction", "Y-axis direction" and "Z-axis direction" should not be interpreted as only a geometrical relationship in which the relationship between each other is vertical, but may mean that the configuration of the present invention has a wider direction within a functional range.

The term "at least one" should be understood to include all possible combinations from one or more related items. For example, "at least one of the first item, the second item, and the third item" means each of the first item, the second item, or the third item, as well as the first item, the second item, and the third item. It may mean a combination of all items that can be presented from two or more of them.

Each feature of the various embodiments of the present invention can be combined or combined with each other partially or entirely, and various technical interconnections and operations are possible, and each embodiment can be implemented independently of each other or together in a related relationship. It may be possible.

Hereinafter, embodiments of the present specification will be described in detail with reference to the attached drawings.

Figure 1 is an exemplary diagram showing a test system to which a test device according to the present invention is applied.

As shown in FIG. 1, the test system to which the present invention is applied includes an element under test 20 and a test device 10 that tests the element under test by transmitting a test pattern to the element under test.

The test device 10 may perform a function of testing the quality of a device under test (DUT).

The device under test (DUT) 20 may include a solid state drive (SSD), hard disk drive (HDD), double data rate (DDR), and system on chip (SoC). there is.

In particular, the test device 10 can be used to test SoCs that use high-speed signals. SoC may include Power Management Integrated Circuit (PMIC), Application Processor (AP), Display Driver Integrated Circuit (DDI), Power IC, CMOS Image sensor (CIS), etc. When the device under test 20 is an SoC, the device under test 20 may be configured in a wafer form.

As described above, in order for the test device 10 to test the quality of the device under test (DUT) 20, the test device 10 includes a test board 100, as shown in FIG. From the hyfix board 200 connected to the board, the probe interface board 300 connected to the hyfix board, and the test board, the test patterns received through the hyfix board and the probe interface board are sent to the device under test 20. It includes a pogo board 400 that transmits data.

First, the test board 100 transmits test patterns to the device under test 20, analyzes test signals received from the device under test 20, or transmits test patterns to the device under test 20 and then tests them. It can perform the function of analyzing test signals received from the target device.

The present invention relates to a test board that generates test patterns. Therefore, the test board 100 according to the present invention can only perform the function of generating test patterns and transmitting them to the device under test 20. In this case, the test generated by the device under test 20 by the test pattern Signals can be analyzed on another test board. However, the test board 100 according to the present invention may generate test patterns, transmit them to the device under test, and then directly analyze test signals received from the device under test using the test patterns.

The specific structure and function of the test board 100 according to the present invention will be described in detail below with reference to FIGS. 2 and 3.

Next, the Hyfix board 200 performs the function of connecting the test board 100 and the probe interface board 300.

A test board may be mounted on the hyfix board 200, and the hyfix board 200 may perform a function of supporting the probe interface board 300.

Next, the probe interface board 300 transmits test patterns to the device under test (DUT) and converts the test signals transmitted from the device under test 20 into signals that can be recognized by the test board 100. , can be transmitted to the test board 100.

Next, the pogo board 400 is mounted on the probe interface board, and the device under test 20 is connected to the pogo board 400.

That is, the pogo board 400 can directly contact the element under test 20, transmit test patterns to the element under test 20, and receive test signals from the element under test 20.

Finally, the external system 30 may transmit vector pattern data and auxiliary pattern data to the test board 100.

In particular, the external system may compile the input raw pattern data and then transmit the compiled vector pattern data to the test board 100.

That is, the external system can perform the function of converting raw pattern data input through the input unit of the external system into vector pattern data that can be used in the test board 100, and this process is called compilation.

However, this compilation process may also be performed on the test board 100.

That is, the external system can transmit raw pattern data input through the input unit to the test board 100, and the test board 100 performs a compilation process on the raw pattern data to convert the raw pattern data into vector pattern data. It can also be converted to .

To elaborate, the format of data used by a company that manufactures the device under test 20 when manufacturing the device under test may be different from the format of data used by the test device 10 . Therefore, for testing the device under test 20, raw pattern data provided by the manufacturer of the device under test may be difficult to use directly in the test device 10.

In this case, the external system 30 or the test board 100 may compile the raw pattern data to generate vector pattern data, and the vector pattern data may be used in the test device 10.

Therefore, when the test patterns used for testing the device under test 20 are changed, a compilation process is performed on the new raw pattern data, vector pattern data is generated, and the vector pattern data is stored on the test board 100. It is saved.

In addition, even if some of the test patterns are changed, the compilation process must be performed on all row pattern data, including some row pattern data that needs to be changed, and all vector pattern data for which the compilation process has been performed must be tested. It must be stored again on the board 100.

However, while the compilation process for the raw pattern data is performed, the operation of the test device 10 must be stopped or some of the functions of the test device 10 must be stopped. This causes a delay in the testing process, and can therefore cause significant damage to the company operating the test device 10.

To prevent this, the present invention stores vector pattern data in the vector pattern memory of the test board 100, and stores auxiliary pattern data corresponding to test patterns to be changed in the auxiliary pattern memory. Therefore, the present invention generates a test pattern to be changed by using the auxiliary pattern data stored in the auxiliary pattern memory instead of the vector pattern data stored in the vector pattern memory at the timing when the test pattern to be changed is required. can do.

Therefore, according to the present invention, when test patterns to be changed are generated, there is no need to perform a recompile process for all vector pattern data stored in the vector pattern memory.

Accordingly, rapid testing of numerous elements under test 20 can be performed.

In the process of testing the devices under test 20, reasons for changing some test patterns may vary depending on the test device and the device under test.

For example, after a primary test is performed on the element under test 20, information specific to the element under test 20, that is, information for correction, is provided in order to resolve defects or errors in the element under test 20. need to be entered. Correction information can also be called test patterns. In this case, if the entire vector pattern data must be changed for correction information, the problem described above may occur. However, according to the present invention, the auxiliary pattern data corresponding to the correction information can be managed separately from the vector pattern data. Therefore, when test patterns corresponding to the auxiliary pattern data are needed, the auxiliary pattern data instead of the vector pattern data Test patterns can be created using pattern data.

In addition, a unique ID for each of the elements under test 20 needs to be entered into the element under test. Therefore, whenever the element under test 20 is changed, the ID of the corresponding element under test 20 is changed. The test patterns corresponding to must be changed. In other words, IDs corresponding to devices under test can also be said to be test patterns. In this case, if the entire vector pattern data must be changed every time the device under test is changed for the ID required for each device under test, the problem described above may occur. However, according to the present invention, the auxiliary pattern data corresponding to the ID can be managed separately from the vector pattern data. Therefore, when the device under test is changed, the auxiliary pattern data is used instead of the vector pattern data to record the ID. Corresponding test patterns can be generated.

That is, as described above, the test patterns applied to the present invention are not only signals having a specific pattern, but also various information, for example, information for resolving defects or errors in the device under test 20. and may include IDs corresponding to the device 20 under test.

Figure 2 is an exemplary diagram showing the configuration of a test board according to the present invention. In FIG. 2 , for convenience of explanation, the test board 100 is shown as transmitting a test pattern directly to the element under test 20. However, as explained above, there is a connection between the test board 100 and the element under test. A hyfix board 200, an interface board 300, and a pogo board 400 may be further provided. In the following description, content that is the same or similar to that described with reference to FIG. 1 will be omitted or simply described.

As described above, the test device 10 according to the present invention includes a test board 100, a hyfix board 200, an interface board 300, and a pogo board according to the present invention, as shown in Figure 1. Includes 400.

Among these, as shown in FIG. 2, the test board 100 according to the present invention includes a receiving unit 110 that receives vector pattern data and auxiliary pattern data, and a vector pattern memory that stores vector pattern data and selection signals. (120), an auxiliary pattern memory 130 for storing auxiliary pattern data, a selection unit 140 and a selection unit for selecting vector pattern data or auxiliary pattern data according to a selection signal received from the vector pattern memory 120. It generates test patterns using the pattern data received from 140 and includes an output unit 150 that outputs the test patterns to the device under test 20.

First, as described above with reference to FIG. 1, the receiving unit 110 converts the raw pattern data received through the external system 30 to be used in the vector pattern memory 120 through a compile process. After changing the vector pattern data into usable vector pattern data, the vector pattern data can be transmitted to the vector pattern memory (120).

Additionally, the receiving unit 110 may transmit vector pattern data received through a compilation process from the external system 30 to the vector pattern memory 120.

Additionally, the receiver 110 may transmit auxiliary pattern data transmitted from the external system 30 to the auxiliary pattern memory 130.

Next, auxiliary pattern data is stored and managed in the auxiliary pattern memory 130.

As explained with reference to FIG. 1, the auxiliary pattern data is used to generate test patterns containing correction information to be input to the device under test 200, or to generate test patterns to change the ID of the device under test. It can be used.

Next, the vector pattern memory 120 includes a data memory 121 that stores vector pattern data and a selection signal memory 122 that stores selection signals to control the selection unit.

For example, in FIG. 2, PCO and PC1 represent output timing, and data stored in matching PCO represents vector pattern data that is simultaneously output at the timing of PCO.

Therefore, for example, at timing 0 (PC0), [111111 ? 11] vector pattern data is output to the selection unit 140, and at the fifth timing (PC5), [10XX01 ? 00] vector pattern data is output to the selection unit 140.

Additionally, in FIG. 2, selection signals are stored in the selection signal memory 122. The selection signal is shown as 'Mux Sel'. For example, the selection signal can be 0 or 1. In the following description, selection signal 0 is referred to as the first selection signal, and selection signal 1 is referred to as the second selection signal.

That is, in the selection signal memory 122, the first selection signal or the second selection signal may be matched and stored for each timing.

Next, when the selection unit 140 receives the first selection signal from the selection signal memory 122 at the kth timing, it is stored in the data memory through the first to mth pins connected to the output unit 150. Transmit vector pattern data.

In addition, when the second selection signal is received from the selection signal memory at the k-th timing, the selection unit 140 transmits the auxiliary pattern data stored in the auxiliary pattern memory 130 to the first to m-th pins ( k and m are natural numbers).

Accordingly, the output unit 150 may generate and output pattern data using vector pattern data at the k-th timing, or may generate and output pattern data using auxiliary pattern data at the k-th timing.

The number of first to mth pins, that is, m, may be equal to the number of data (111111 - 11) stored by matching the PCO of the data memory 121 shown in FIG. 2.

That is, at the 0th timing (PC0), m pieces of vector pattern data (111111 - 11) may be transmitted from the selection unit 140 to the output unit 150 through the first to mth pins. In this case, the data memory 121 and the selection unit 140 may also be provided with first to mth pins.

To elaborate, the vector pattern memory 120 contains the first selection signal or the second selection signal to be transmitted to the selection unit 140 at the k-th timing, and the first selection signal or the second selection signal to be transmitted to the first to m-th pins at the k-th timing. It is matched with the 1st to mth vector pattern data and stored.

In this case, the number of auxiliary pattern sets including the auxiliary pattern data to be transmitted to the first to mth pins may correspond to the number of second selection signals.

For example, while the vector pattern data stored in the data memory 121 is output sequentially from the 0th timing to the xth timing, if the auxiliary pattern data is output at n timings, the selection signal memory 122 The number of stored second selection signals may be n (x is a natural number, n is a natural number smaller than x). In this case, the number of auxiliary pattern sets including the auxiliary pattern data to be transmitted to the first to mth pins may also be n.

That is, the auxiliary pattern memory 130 may store auxiliary pattern data output n times.

Hereinafter, a method of operating a test device according to the present invention will be described with reference to FIGS. 1 to 3.

Figure 3 is an example diagram showing pattern data generated from a test board according to the present invention.

First, when raw pattern data is converted into vector pattern data through a compilation process, the vector pattern data is stored in the vector pattern memory 120. In this case, the second selection signal is matched and stored at a timing when auxiliary pattern data is required, and the first selection signal is matched and stored at a timing when auxiliary pattern data is not required. Saving the first selection signal and the second selection signal can be simply done without a compilation process.

That is, because the first selection signal and the second selection signal are simple control signals, they can be quickly and simply modified by the user during the test of the devices 20 under test.

Next, auxiliary pattern data to be output at a timing corresponding to the second selection signal is sequentially stored in the auxiliary pattern memory 130 through the receiving unit 110.

As described above, the storage process for auxiliary pattern data can also be simply performed without a compilation process.

In addition, even if a compilation process is required for the auxiliary pattern data, since the auxiliary pattern data are independent data from the vector pattern data used in the currently ongoing test, the compilation process can be performed independently for the auxiliary pattern data. . Accordingly, after an independent compilation process is performed on the auxiliary pattern data, the auxiliary pattern data may be stored in the auxiliary pattern memory 130. That is, even when the operation of storing auxiliary pattern data in the auxiliary pattern memory 130 is in progress, the test on the test board 20 can be continuously performed.

In addition, even if the test on the test board 20 is stopped while the auxiliary pattern data is stored in the auxiliary pattern memory 130, the compilation process for the auxiliary pattern data less than the number of vector pattern data is not performed on the entire vector pattern data. It can proceed more quickly than the compilation process for pattern data.

Therefore, according to the present invention, compared to the prior art, the period during which the test is stopped may be absent or may be reduced.

Next, while the test for the test target board 20 is in progress, the selection unit 140 selects the vector pattern data transmitted from the data memory 121 when the first selection signal is received from the selection signal memory 122. It is transmitted to the output unit 150 through the 1st to mth pins.

The output unit 150 generates test patterns using vector pattern data received through the first to mth pins, and the generated test patterns are connected to the Hyfix board 200, the interface board 300, and the Pogo board 400. It is transmitted to the device under test (20) through .

Accordingly, testing of the device under test 20 may be performed.

Lastly, while the test for the test target board 20 is in progress, when the selection unit 140 receives the second selection signal from the selection signal memory 122, the vector pattern data transmitted from the auxiliary pattern memory 130 are transmitted to the output unit 150 through the first to mth pins.

The output unit 150 generates test patterns using auxiliary pattern data received through the first to mth pins, and the generated test patterns are connected to the Hyfix board 200, the interface board 300, and the Pogo board 400. It is transmitted to the device under test (20) through .

Accordingly, testing of the device under test 20 may be performed.

For example, as shown in FIG. 3, when the second selection signal 1 is received at the second timing PC2, the selection unit 140 selects the auxiliary pattern data stored in the auxiliary pattern memory 130. The auxiliary pattern data (101111 - 11) matched to the second timing (PC2) may be output to the output unit 150.

To this end, the auxiliary pattern memory 130 stores auxiliary pattern data (101111 - 11) at the address (Ox00) corresponding to the second timing (PC2).

In addition, as shown in FIG. 3, when the second selection signal 1 is received at the third timing PC3, the selection unit 140 selects the first among the auxiliary pattern data stored in the auxiliary pattern memory 130. 3 The auxiliary pattern data (111000 - 11) matched to the timing (PC3) can be output to the output unit 150.

For this purpose, the auxiliary pattern memory 130 stores auxiliary pattern data (111000 - 11) at the address (Ox01) corresponding to the third timing (PC3).

Therefore, according to the present invention as described above, when a change to the test pattern is required, the test process can be continuously performed using the changed test pattern without a recompilation process for all vector pattern data. Accordingly, the test process can proceed quickly and more test target elements can be tested.

The embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of the present invention is indicated by the claims described below rather than the detailed description above, and all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention. do.

10: Test device 20: Device under test
100: test board 200: highfix board
300: Probe interface board 400: Pogo board

Claims (8)

A receiving unit that receives vector pattern data and auxiliary pattern data;
a vector pattern memory storing the vector pattern data and selection signals;
an auxiliary pattern memory storing the auxiliary pattern data;
a selection unit that selects the vector pattern data or the auxiliary pattern data according to a selection signal received from the vector pattern memory; and
A test board including an output unit that generates test patterns using the pattern data received from the selection unit and outputs the test patterns to the device under test. According to claim 1,
The receiving unit converts the raw pattern data received through an external system into the vector pattern data that can be used in the vector pattern memory through a compilation process and then transmits the vector pattern data to the vector pattern memory, or A test board that transmits the vector pattern data received through a compilation process from an external system to the vector pattern memory. According to claim 1,
The auxiliary pattern data is used to generate test patterns containing correction information to be input to the device under test, or to generate test patterns for changing the ID of the device under test. According to claim 1,
The vector pattern memory is,
a data memory storing the vector pattern data; and
A test board including a selection signal memory that stores selection signals to control the selection unit. According to claim 4,
The selection part is,
At the kth timing, when the first selection signal is received from the selection signal memory, the vector pattern data is transmitted to the first to mth pins connected to the output unit,
A test board that transmits the auxiliary pattern data to the first to mth pins when a second selection signal is received from the selection signal memory at the kth timing. According to claim 5,
In the vector pattern memory,
The first selection signal or the second selection signal to be transmitted to the selection unit at the k-th timing matches the first to m-th vector pattern data to be transmitted to the first to m-th pins at the k-th timing. A test board that is stored as a test board. According to claim 5,
The test board where the number of auxiliary pattern sets including the auxiliary pattern data to be transmitted to the first to mth pins corresponds to the number of the second selection signals. The test board according to any one of claims 1 to 7;
a high-fix board connected to the test board;
a probe interface board connected to the hyfix board; and
A test device comprising a pogo board for transmitting test patterns received from the test board through the Hyfix board and the probe interface board to a device under test.

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