KR20240054557A - Circuit board strip and semiconductor package - Google Patents

Abstract

The circuit board strip according to the embodiment includes a substrate portion; and a protective layer disposed on the substrate, wherein the protective layer includes a first region of the active area and a second region of a dummy region excluding the first region, and the second region of the protective layer includes the first region of the active region. It has a plurality of openings spaced apart from each other along the circumferential direction of the second area, and each of the plurality of openings has a width on one side adjacent to the first area smaller than a width on the other side opposite to the one side.

Description

Circuit board strip and semiconductor package {CIRCUIT BOARD STRIP AND SEMICONDUCTOR PACKAGE}

The embodiment relates to a circuit board strip and, in particular, to a circuit board strip and a semiconductor package that can solve molding defects that occur in the process of molding semiconductor devices in strip units.

A circuit board is a board that electrically connects or mechanically fixes certain electronic components, and is composed of an insulating layer such as phenol resin or epoxy resin and a copper foil layer that is attached to the insulating layer to form a predetermined wiring pattern.

Depending on the number of layers, circuit boards are largely divided into single-sided circuit boards with wiring formed on only one side of the insulating layer, double-sided circuit boards with wiring formed on both sides of the insulating layer, and multilayer circuit boards with wiring formed in multiple layers.

During the manufacturing process of the circuit board, warpage may occur as the circuit board undergoes heat treatment. As electronic products become smaller and thinner, circuit boards are also becoming thinner, and as thinning progresses, the defect rate due to bending becomes a problem. Here, the causes of warping are diverse, including differences in coefficient of thermal expansion (CTE) and elastic modulus between the insulating material and the metal circuit board.

Additionally, recently, in order to improve process productivity when manufacturing a circuit board package, a strip structure in which multiple circuit board units are formed as one is manufactured, and this is called a circuit board strip.

Specifically, circuit boards are generally manufactured on a panel basis. That is, multiple units that make up the circuit board form one circuit board strip, and these multiple circuit board strips come together to form one panel.

However, in the process of manufacturing circuit boards on a panel basis, bending of the circuit board strip occurs, which prevents the normal manufacturing process from being carried out.

Meanwhile, in the circuit board as described above, electronic devices are mounted in strip units, and a molding layer for molding the mounted electronic devices is formed. At this time, there are various methods of forming the molding layer, but recently, it has been formed using a compression molding method.

Compression molding is performed by filling and melting molding resin powder in the cavity of the lower mold (or filling and heating liquid molding resin) and then combining the upper mold and lower mold. At this time, a circuit board strip on which a semiconductor device is mounted is disposed in the upper mold, and the circuit board strip is contained in a molding resin formed in the cavity of the lower mold during the joining process, and a molding layer can be formed accordingly.

At this time, during the compression molding process, a problem occurs in which molding resin powder overflows to the outside of the lower mold and the upper mold, and as a result, molding workability is significantly reduced. For example, the circuit board strip has a thickness deviation for each region, and accordingly, a gap is formed between the lower mold and the upper mold due to the thickness deviation, and the molding resin powder overflows into the formed gap. Additionally, there is a problem that the lower mold or the upper mold is contaminated by the overflowing molding resin powder, and thus molding workability is deteriorated.

The embodiment provides a circuit board strip with a new structure and a semiconductor package manufactured based on the same.

Additionally, the embodiment provides a circuit board strip that can solve molding defects that occur in the process of molding semiconductor devices in units of circuit board strips and a semiconductor package manufactured based on the same.

Additionally, an embodiment provides a circuit board strip that can improve reliability by minimizing the occurrence of warping of the circuit board strip, and a semiconductor package manufactured based on the same.

The tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art in the technical field to which the proposed embodiment belongs from the description below. It will be understandable.

The circuit board strip according to the embodiment includes a substrate portion; and a protective layer disposed on the substrate, wherein the protective layer includes a first region of the active area and a second region of a dummy region excluding the first region, and the second region of the protective layer includes the first region of the active region. It has a plurality of openings spaced apart from each other along the circumferential direction of the second area, and each of the plurality of openings has a width on one side adjacent to the first area smaller than a width on the other side opposite to the one side.

Additionally, the protective layer may include: a first protective layer disposed on the substrate portion; and a second protective layer disposed under the substrate portion, wherein each of the first protective layer and the second protective layer includes the first and second regions, and the opening includes the first and second regions of the first protective layer. It includes a plurality of first openings provided in two areas and a plurality of second openings provided in a second area of the second protective layer.

Additionally, the second region of the first protective layer vertically overlaps the second region of the second protective layer.

Additionally, the aperture ratio of the second region of the first protective layer by the plurality of first openings is different from the aperture ratio of the second region of the second protective layer by the plurality of second openings.

In addition, at least one of the spacing between the plurality of first openings and the area of each of the plurality of first openings is one of the spacing between the plurality of second openings and the area of each of the plurality of second openings. It is different from at least one.

Additionally, the substrate portion includes an insulating layer; and a circuit pattern layer disposed on the insulating layer, wherein the first area of the first protective layer includes an open area vertically overlapping the circuit pattern layer.

Additionally, the circuit board strip may include a connection portion disposed on a circuit pattern layer vertically overlapping the open area; a semiconductor element disposed on the connection portion; and a first molding member disposed on the semiconductor device.

Additionally, at least a portion of the first molding member is disposed in the first opening in the second region of the first protective layer.

Additionally, the second region of the first protective layer includes a first sub-region and a second sub-region, and the opening ratio in the first sub-region of the first protective layer due to the plurality of first openings is It is different from the opening ratio in the second sub-region of the first protective layer due to the plurality of first openings.

Additionally, the density of the circuit pattern layer in contact with the first protective layer in the first sub-region is different from the density of the circuit pattern layer in contact with the first protective layer in the second sub-region.

Additionally, a semiconductor package may be provided by sawing a boundary area between the first and second regions of each of the first and second protective layers in the circuit board strip.

A circuit board strip according to an embodiment may include a substrate portion including a first area corresponding to an effective area and a second area corresponding to a dummy area. A first protective layer may be provided on the upper surface of the substrate and a second protective layer may be provided on the lower surface. Additionally, the first protective layer and the second protective layer may include first and second areas corresponding to the effective area and the dummy area, respectively. At this time, a plurality of first openings spaced apart from each other may be provided in the second region of the first protective layer. Additionally, a plurality of second openings spaced apart from each other may be provided in the second region of the second protective layer. The plurality of first openings and the plurality of second openings may function as a dam to prevent overflow of the molding member during a process of applying the molding member to the first region of the substrate portion. Through this, the embodiment can prevent overflow of the molding member and thus improve reliability.

Meanwhile, each of the first opening and the second opening may have a width on one side adjacent to the first area that is smaller than a width on the other side opposite to the one side. Through this, the embodiment can control the flow of the overflowing molding member while preventing the molding member from overflowing into the second area during the process of applying the molding member. Accordingly, the embodiment can prevent the mold from being contaminated by overflow of the molding member, and prevent excessive overflow of the molding member, thereby ensuring thickness uniformity of the molding member in the first area.

Additionally, the opening ratio of the second region of the first protective layer formed by the plurality of first openings may be different from the opening ratio of the second region of the second protective layer formed by the plurality of second openings. Through this, the embodiment can prevent the substrate from being bent by adjusting the aperture ratio according to the direction in which the substrate is bent, thereby further improving the reliability.

Additionally, the second region of the first protective layer may be divided into a first sub-region and a second sub-region. The first sub-region and the second sub-region may be determined by the density of the circuit pattern layer vertically overlapping therewith. Additionally, the aperture ratio of the plurality of first openings in the first sub-region may be different from the aperture ratio of the plurality of first openings in the second sub-region. Through this, the embodiment can solve the problem of warping caused by the difference in density of the circuit pattern layer, and thereby further improve mechanical and electrical reliability.

1 is a diagram showing a panel according to an embodiment.
FIG. 2 is a cross-sectional view taken along the AA′ direction of FIG. 1 according to an embodiment.
FIG. 3 is a cross-sectional view showing a state in which a semiconductor device is mounted on the strip of FIG. 2.
Figure 4 is a diagram showing a strip including a molding member of a comparative example.
Figure 5 is a diagram showing a strip according to an embodiment.
Figure 6 is a plan view showing the first opening of the first protective layer according to the first embodiment.
FIG. 7 is a cross-sectional view of the first opening of FIG. 6 according to various embodiments.
Figure 8 is a plan view showing a second opening of the second protective layer according to an embodiment.
Figure 9 is a plan view showing the first opening of the first protective layer according to the second embodiment.
Figure 10 is a plan view showing another first opening according to the third embodiment.

Hereinafter, embodiments disclosed in the present specification will be described in detail with reference to the attached drawings. However, identical or similar components will be assigned the same reference numbers regardless of reference numerals, and duplicate descriptions thereof will be omitted. The suffixes “module” and “part” for components used in the following description are given or used interchangeably only for the ease of preparing the specification, and do not have distinct meanings or roles in themselves. Additionally, in describing the embodiments disclosed in this specification, if it is determined that detailed descriptions of related known technologies may obscure the gist of the embodiments disclosed in this specification, the detailed descriptions will be omitted. In addition, the attached drawings are only for easy understanding of the embodiments disclosed in this specification, and the technical idea disclosed in this specification is not limited by the attached drawings, and all changes included in the spirit and technical scope of the present invention are not limited. , should be understood to include equivalents or substitutes.

Terms containing ordinal numbers, such as first, second, etc., may be used to describe various components, but the components are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another.

When a component is said to be "connected" or "connected" to another component, it is understood that it may be directly connected to or connected to the other component, but that other components may exist in between. It should be. On the other hand, when it is mentioned that a component is “directly connected” or “directly connected” to another component, it should be understood that there are no other components in between.

Singular expressions include plural expressions unless the context clearly dictates otherwise.

In this application, terms such as “comprise” or “have” are intended to designate the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but are not intended to indicate the presence of one or more other features. It should be understood that this does not exclude in advance the possibility of the existence or addition of elements, numbers, steps, operations, components, parts, or combinations thereof.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

1 is a diagram showing a panel according to an embodiment.

Referring to Figure 1, circuit boards are generally manufactured in panel units. Additionally, the element mounting process and molding process for circuit boards manufactured in panel units are manufactured in strip units constituting the panel. Then, when manufacturing is completed in strip units, the circuit boards are manufactured by dicing them unit by unit.

Specifically, the basic material for manufacturing a general circuit board may be a panel 100 in the form of a copper clad laminate (CCL).

The horizontal width of the panel 100 may be 415 mm to 430 mm. Additionally, the vertical width of the panel 100 may be 510 mm to 550 mm. Here, the width in the horizontal direction of the panel 100 may be the width in the minor axis direction, and the width in the vertical direction may be the width in the major axis direction.

At this time, the panel 100 may be divided into a plurality of strips 200. In other words, the panel 100 may be composed of a set of a plurality of strips 200. The plurality of strips 200 may be spaced apart from each other at regular intervals in the horizontal and vertical directions within the panel 100. For example, one panel 100 may be divided into 16 strips 200. That is, one panel 100 can be divided into two areas in the horizontal direction and eight areas in the vertical direction. And, each of the divided areas may constitute a strip 200.

Accordingly, the base material includes a first region (R1) where the plurality of strips 200 are disposed and a second region (R2) excluding the first region (R1). The second area R2 may be a peripheral area of the first area R1. For example, the second area R2 may be an outer area disposed on the outside of the panel 100. For example, the first area R1 may be referred to as an effective area where the strip 200 is disposed, and the second area R2 may be referred to as a dummy area excluding the effective area.

Meanwhile, each strip 200 may include a plurality of units 300. For example, one strip 200 may include 1,275 units 300, but is not limited thereto. For example, the number of units 300 included in one strip 200 may decrease or increase depending on process capacity.

At this time, each unit 300 may have a horizontal width of 3 mm and a vertical width of 2 mm. Meanwhile, each unit 300 may constitute one circuit board. In other words, one strip 200 includes 1,275 units 300, and the panel 100 includes 16 strips 200. Accordingly, one panel 100 may include 16 strips 200 and 20,400 units 300.

Meanwhile, one unit 300 may include a plurality of circuit pattern layers, a plurality of insulating layers, and a plurality of via holes (VH) of a certain size. Additionally, a metal material may be filled in the via hole (VH) to form a via.

At this time, about 150 via holes (VH) are formed in one unit 200. Accordingly, one panel 100 may include 20,400 units 300 in which about 150 via holes (VH) are formed. In conclusion, more than 3 million via holes (VH) are formed in one panel 100.

Additionally, in recent years, as circuit wiring has become more complex and highly integrated, the patterns constituting the circuit pattern layer have become finer, and the number of via holes (VH) is gradually increasing accordingly. Accordingly, as at least 3 million via holes (VH) are formed in one panel 100, the panel 100 or the strip 200 is formed until the formation of the 3 million or more via holes (VH) is completed. It is important to maintain the flatness of ). For example, the via hole shape may be formed through laser processing. At this time, during the laser processing, heat is applied to the panel 100, and as a result, the surface of the panel 100 rises to a maximum of 700°C. At this time, the panel 100 repeatedly experiences expansion and contraction, and as a result, a bending phenomenon that causes wrinkles to occur on the surface of the panel 100 or the strip 200 occurs. At this time, when a via hole is formed by laser processing while the panel 100 or the strip 200 is bent, the position or shape of the formed via hole may change. For example, if the laser process is performed while the panel 100 or the strip 200 is bent, reliability problems may occur, such as the position of the via hole being shifted or the shape of the via hole being distorted. . Therefore, it is necessary to maintain the flatness of the panel 100 or strip 200 by minimizing bending problems such as wrinkles that occur in the panel 100.

Meanwhile, in general, when the unit 300 constituting the circuit board is manufactured as a panel 100, a mounting process to mount a semiconductor element thereon and a molding process to protect the surface of the semiconductor element or unit 300 are performed. I do it.

For example, the unit 300 may include an open portion exposing an area where the device is mounted, and as the device is mounted in the open portion, a process of forming a molding layer that protects the device is performed.

At this time, the unit 300 and the strip 200 constituting the unit 300 may have different thicknesses for each region. For example, the panel 100 may have different thickness distributions for each region. For example, the units 300 do not have the same thickness throughout the entire area. For example, the unit 300 may have a first thickness in a specific area and a second thickness that is thicker than the first thickness in another area. In addition, during the molding process due to the thickness deviation of the unit 300, the molding resin overflows into the outer area of the unit 300, that is, the outer area of the strip 200. Additionally, when the molding resin overflows, it contaminates the mold in which the molding process is performed, resulting in workability problems.

Accordingly, in the embodiment, the flatness of the unit 300, the strip 200, and the panel 100 is maintained, and mold contamination due to overflow of mold resin occurring in the process of forming the molding layer is prevented. The goal is to provide a circuit board strip that can prevent this. At this time, in the embodiment, in the overall design of the circuit board strip, the bending occurrence is improved and the mold contamination is prevented by changing the design of the second region (R2) rather than the design of the first region (R1). do.

Hereinafter, a circuit board strip according to an embodiment will be described in detail.

Before explaining the circuit board strip of the present application, each unit 300 provided in the circuit board strip can be used as a substrate for manufacturing a semiconductor package. The substrate may refer to a package substrate that is coupled to the main board of an electronic product. In another embodiment, the substrate may mean an interposer coupled to the package substrate.

Meanwhile, semiconductor devices may be mounted on the unit 300. The semiconductor device may include active devices and/or passive devices. Active devices may be semiconductor chips in the form of integrated circuits (ICs) in which hundreds to millions of devices are integrated into one chip. Semiconductor devices may be logic chips, memory chips, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip is an application processor (AP) chip that includes at least one of a central processor (CPU), graphics processor (GPU), digital signal processor, cryptographic processor, microprocessor, microcontroller, or an analog-digital chip. It could be a converter, an application-specific IC (ASIC), or a set of chips containing a specific combination of the ones listed so far. The memory chip may be a stack memory such as HBM. Additionally, the memory chip may include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory.

Meanwhile, the product lines to which the semiconductor package of the embodiment is applied include Chip Scale Package (CSP), Flip Chip-Chip Scale Package (FC-CSP), Flip Chip Ball Grid Array (FC-BGA), Package On Package (POP), and SIP ( System In Package), but is not limited to this.

FIG. 2 is a cross-sectional view taken along the line A-A' of FIG. 1 according to an embodiment. Referring to FIG. 2, the strip 200 may have a multiple layer structure. The strip 200 includes a first area R1 including a plurality of units 300 and a second area R2 outside the strip 200. Additionally, the first region R1 and the second region R2 may be divided into an upper surface area corresponding to the upper surface of the strip 200 and a lower surface area corresponding to the lower surface. This will be explained in detail below. The first area R1 may be an effective area constituting the unit 300. Additionally, the second area R2 may be a dummy area excluding the first area. For example, when manufacturing a plurality of semiconductor packages using the strip 200, sawing may be performed based on the boundary line between the first area and the second area.

The strip 200 may include an insulating layer 410, a circuit pattern layer 420, a via electrode 430, a first protective layer 440, and a second protective layer 450.

The insulating layer 410 may be rigid or flexible. For example, the insulating layer 410 may include glass or plastic.

The insulating layer 410 may be rigid or flexible. For example, the insulating layer 410 may include glass or plastic. For example, the insulating layer 410 may include chemically strengthened/semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the insulating layer 410 may include reinforced or soft plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), and polycarbonate (PC). You can. For example, the insulating layer 410 may include sapphire. For example, the insulating layer 410 may include an optically isotropic film. For example, the insulating layer 410 may include Cyclic Olefin Copolymer (COC), Cyclic Olefin Polymer (COP), wide isotropic polycarbonate (PC), or wide isotropic polymethyl methacrylate (PMMA). . For example, the insulating layer 410 can use ABF (Ajinomoto Build-up Film), a product released by Ajinomoto, FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. This can be used.

Meanwhile, in FIG. 2, the insulating layer 410 is shown as having a one-layer structure, but it is not limited thereto. For example, the insulating layer 410 may have a two-layer or more layer structure. For example, the strip 200 may include units 300 constituting a multilayer circuit board, and accordingly, the insulating layer 410 may be composed of multiple layers.

A circuit pattern layer 420 may be disposed on the surface of the insulating layer 410. For example, the circuit pattern layer 420 may be disposed on the upper and lower surfaces of the insulating layer 410, respectively. The circuit pattern layer 420 may include a circuit pattern (or wiring) disposed on the surface of the insulating layer 410 to transmit an electrical signal. The circuit pattern layer 420 may be formed of a metal material. For example, the circuit pattern layer 420 is made of at least one selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). It may contain one metallic substance. In addition, the circuit pattern layer 420 is selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which have excellent bonding properties. It may include a paste or solder paste containing at least one metal material. Preferably, the circuit pattern layer 420 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

The circuit pattern layer 420 is manufactured using typical printed circuit board manufacturing processes such as the additive process, subtractive process, MSAP (Modified Semi Additive Process), and SAP (Semi Additive Process) process. This is possible, and detailed description is omitted here.

The circuit pattern layer 420 may be provided in the first region (R1) and the second region (R2), respectively. The circuit pattern layer 420 provided in the second region R2 may be referred to as a dummy pattern. The dummy pattern may function to ensure the rigidity of the strip 200 while ensuring a uniform thickness of the circuit pattern layer 420 provided in the first region R1.

Meanwhile, a via electrode 430 may be disposed within the insulating layer 410. The via electrode 430 may penetrate the upper and lower surfaces of the insulating layer 410. The via electrode 430 may electrically connect the circuit pattern layer disposed on the upper surface and the circuit pattern layer disposed on the lower surface of the insulating layer 410 to each other. The via electrode 430 can be formed by filling the inside of a via hole (not shown) penetrating the insulating layer 410 with a metal material.

Meanwhile, protective layers may be formed on the upper and lower surfaces of the insulating layer 410, respectively.

That is, the first protective layer 440 may be disposed on the upper surface of the insulating layer 410. Additionally, a second protective layer 450 may be disposed on the lower surface of the insulating layer 410. The first protective layer 440 and the second protective layer 450 may be formed of at least one layer using at least one of solder resist (SR), oxide, and Au. Preferably, the first protective layer 440 and the second protective layer 450 may be solder resist.

Meanwhile, the strip 200 as described above may include a first region (R1) and a second region (R2). At this time, the first region (R1) and the second region (R2) may be divided into an upper surface area corresponding to the upper part of the insulating layer 410 and a lower surface area corresponding to the lower part of the insulating layer 410. .

Each of the first protective layer 440 and the second protective layer 450 may be divided into a plurality of regions corresponding to the first region R1 and the second region R2.

For example, the first protective layer 440 may include a first area RT1 that is an effective area and a second area RT2 other than the first area RT1. The second area RT2 of the first protective layer 440 may mean a dummy area.

The first protective layer 440 may include an open area 441 provided in the first area RT1. The open area 441 of the first protective layer 440 may correspond to an area where the semiconductor device is mounted.

For example, the circuit pattern layer 420 includes a pad electrically connected to a terminal of the semiconductor device, and the first protective layer 440 includes an open area 441 that vertically overlaps the pad. can do. Accordingly, the pad of the circuit pattern layer 420 may be exposed to the outside of the strip 200 through the open area 441.

Meanwhile, the second protective layer 450 may include a first area RB1, which is an effective area, and a second area RB2 excluding the first area RB1. The first region RB1 of the second protective layer 440 may correspond to the first region RT1 of the first protective layer 440 . For example, the first region RB1 of the second protective layer 450 may vertically overlap the first region RT1 of the first protective layer 440 .

The second area RB2 of the second protective layer 450 may be a dummy area. The second region RB2 of the second protective layer 450 may correspond to the second region RT2 of the first protective layer 440. For example, the second region RB2 of the second protective layer 450 may vertically overlap the second region RT2 of the first protective layer 440.

Meanwhile, although it is shown in FIG. 2 that the first area RB1 of the second protective layer 450 does not have an open area, the present invention is not limited thereto. For example, the first region RB1 of the second protective layer 450 may be provided with an open area that vertically overlaps a pad on which an electronic device is mounted or coupled to an external substrate.

FIG. 3 is a cross-sectional view showing a state in which a semiconductor device is mounted on the strip of FIG. 2. Referring to FIG. 3, the first protective layer 440 of the circuit pattern layer 420 disposed on the upper surface of the insulating layer 410 is shown. The upper surface of the circuit pattern layer corresponding to the open area 441 may be exposed to the outside. Additionally, a semiconductor device 460 may be mounted on the exposed circuit pattern layer. Preferably, a connection portion 465 may be provided on a pad that vertically overlaps the open region 441 of the first region RT1 of the first protective layer 440, and the semiconductor device 460 may be It can be electrically coupled to the pad through the connection portion 465.

Meanwhile, the strip 200 may include a molding layer.

For example, a first molding member 470 for molding the semiconductor device 460 may be disposed on the first protective layer 440.

Additionally, a second molding member 480 may be provided under the second protective layer 450.

The first molding member 470 and the second molding member 480

The first molding member 470 and the second molding member 480 may be formed by a compression molding method. For example, the first molding member 470 and the second molding member 480 include a first process of filling the cavity of the lower mold with molding resin powder, a second process of placing the strip 200 in the upper mold, It can be formed through a third process of combining the upper mold and the lower mold and inserting the strip 200 into the cavity.

The first molding member 470 may be provided in the first region RT1 of the first protective layer 440. For example, the cavity of the lower mold may have a size corresponding to the first region RT1 of the first protective layer 440. Additionally, the second molding member 480 may be provided in the first region RB1 of the second protective layer 450.

Figure 4 is a diagram showing a strip including a molding member of a comparative example.

Referring to FIG. 4, the strip 200 has thickness variations for each region. Accordingly, when the upper mold and the lower mold are combined, a certain gap may be formed between the upper mold and the lower mold. Additionally, the molding resin filled in the cavity may overflow through the gap.

For example, as shown in Figure 4, in the comparative example, there is a thickness deviation in the strip 200, and the molding resin overflows through the gap caused by the thickness deviation. Accordingly, in the comparative example, the first defective area 470A may be provided in the first molding member 470 formed in the second area RT2 of the strip 200. Additionally, in the comparative example, a second defective area 480A may be provided in the second molding member 480 provided in the second area RB2 of the second protective layer 450 of the strip 200. Additionally, the first and second defective areas 470A and 480A contaminate the upper mold and the lower mold. Accordingly, in order to proceed with the process of forming the molding member, the contaminated upper mold and lower mold must be cleaned, which results in a problem of poor workability.

Figure 5 is a diagram showing a strip according to an embodiment.

Referring to FIG. 5 , the first protective layer 440 may include a plurality of first openings 442 provided in the second region RT2.

The first opening 442 may be provided in the second region RT2, which is the dummy region, of the first protective layer 440. Accordingly, among the circuit pattern layers 420 provided on the strip 200, the circuit pattern layer 420 with the second region RT2 vertically overlapping is exposed to the outside through the first opening 442. It can be.

Additionally, the second protective layer 450 may include a second opening 451. The second opening 451 may be provided in the second region RB2 of the second protective layer 450.

The first opening 442 of the first protective layer 440 may function as a dam to prevent the first molding member 470 from overflowing during the process of applying the first molding member 470. there is. For example, in the comparative example, the molding member is formed without including the first opening 442, and accordingly, the molding member may have a first defective area 470A due to overflow. At this time, the first defective area 470A protruded above the upper surface of the first protective layer 440 and contaminated the upper and lower molds. Differently, in the embodiment, when the first molding member 470 overflows, the defective area of the overflowing molding member 470 may fill the first opening 442 of the first protective layer 440. there is. Accordingly, contamination of the upper mold and the lower mold can be prevented. In other words, the first opening 442 of the first protective layer 440 functions as a dam to prevent the first molding member 470 from overflowing during the process of applying the first molding member 470. can do.

Correspondingly, the second opening 451 of the second protective layer 450 has a dam function to prevent the second molding member 480 from overflowing during the process of applying the second molding member 480. can do. That is, the second opening 451 of the second protective layer 450 in the embodiment may function as a dam to confine the second molding member 480 when it overflows, thereby forming the upper mold. Contamination of the upper and lower molds can be prevented.

FIG. 6 is a plan view showing the first opening of the first protective layer according to the first embodiment, FIG. 7 is a cross-sectional view of the first opening of FIG. 6 according to various embodiments, and FIG. 8 is a second protective layer according to the embodiment. This is a plan view showing the second opening of the floor.

In an embodiment, the insulating layer 410, the circuit pattern layer 420, and the via electrode 430 may be referred to as a substrate portion, and will hereinafter be described as a 'substrate portion'.

The substrate portion may be divided into a first region (R1) and a second region (R2). As described above, the first area R1 is a valid area and the second area R2 is a dummy area.

Accordingly, the first protective layer 440 may include a first area RT1 corresponding to the effective area and a second area RT2 corresponding to the dummy area. Additionally, an open area 441 for coupling to a semiconductor device may be provided in the first region RT1 of the first protective layer 440. Additionally, a first opening 442 may be provided in the second region RT2 of the first protective layer 440.

Additionally, the second protective layer 450 may include a first area RB1 corresponding to the effective area and a second area RB2 corresponding to the dummy area. A second opening 451 may be provided in the second region RB2 of the second protective layer 450.

Meanwhile, the second region RT2 of the first protective layer 440 may be provided to surround the first region RT1 of the first protective layer 440.

The second region RT2 of the first protective layer 440 may be provided with a first opening 442 along the circumferential direction of the second region RT2. At this time, the first opening 442 may include a plurality of dot-shaped openings spaced apart from each other along the circumferential direction, rather than a single connected opening. For example, the first opening 442 may include a plurality of first holes arranged along the circumferential direction of the second region RT2 of the first protective layer 440 and spaced apart from each other.

Meanwhile, the width of the first opening 442 of the first protective layer 440 may change as it moves away from the first region RT1.

For example, the first opening 442 of the first protective layer 440 may have a first width W1 on one side adjacent to the first region RT1. Additionally, the first opening 442 may have a second width W2 greater than the first width W1 on the other side opposite to the one side. That is, the width of the first opening 442 of the first protective layer 440 may become larger as the distance from the first region RT1 increases.

In the embodiment, the width of the first opening 442 on one side adjacent to the first region RT1 is relatively small. Through this, the embodiment can solve the problem of the first molding member 470 not being sufficiently applied in the first region RT1, and thereby improve the reliability of the first molding member 470. . Furthermore, the embodiment can secure thickness uniformity in the entire area of the first molding member 470 and thus improve product reliability. Additionally, the embodiment allows the width W2 of the first opening 442 to be relatively large on the other side that is relatively far away from the first region RT1. Through this, the embodiment can solve the problem of defects caused by the first molding member 470 overflowing to the outside. Through this, the embodiment can simplify the manufacturing process by preventing overflow of the first molding member 470, thereby improving product yield.

Meanwhile, the first opening 442 may have the overall width W2. However, when the first opening 442 has the width W2 as a whole, the waste of the molding member to be applied to the first region RT1 by the first opening 442 may increase, resulting in the The first molding member 470 in the first region RT1 may not have a sufficient thickness, or it may take a lot of time to form the first molding member 470 of a certain thickness in the first region RT1. Time and cost may be incurred.

Meanwhile, the first opening 442 can be divided into a plurality of groups. For example, the first opening 442 is a first group of first openings provided along the circumferential direction of the second region RT2 and including a plurality of first holes adjacent to the first region RT1. (442-1) and a second group of first openings 442-2 spaced apart from the first group of openings 442-1 and adjacent to the perimeter of the second region RT2. You can.

For example, the first group of first openings 442-1 includes a plurality of first holes arranged around the first region RT1 at a position adjacent to the circumference of the first region RT1. It can be included. Additionally, the first openings 442-2 of the second group may be provided adjacent to the periphery of the second region RT2 while being spaced apart from the first openings 442-1 of the first group.

For example, the first group of first openings 442-1 may include first holes spaced apart from each other in the first horizontal direction. And, the first openings 442-2 of the second group are spaced apart from the first openings 442-1 of the first group in a second horizontal direction perpendicular to the first horizontal direction. It may include a plurality of first holes spaced apart from each other.

Meanwhile, it has been described that the first opening 442 provided in the second region RT2 of the first protective layer 440 is a through hole penetrating the upper and lower surfaces of the first protective layer 440. It is not limited to this. For example, the first opening 442 provided in the second region RT2 of the first protective layer 440 is provided as a concave recess from the upper surface to the lower surface of the first protective layer 440. It could be.

Meanwhile, referring to FIG. 7 , the first opening 442 may have various shapes whose width increases in a direction away from the first region RT1.

For example, referring to (a) of FIG. 7 , the first opening 442 may have a T-shape whose width increases in a direction away from the first region RT1.

For example, referring to (b) of FIG. 7 , the first opening 442 may have a trapezoidal shape whose width increases in a direction away from the first region RT1.

For example, referring to (c) of FIG. 7 , the first opening 442 may have a semicircular shape whose width increases in a direction away from the first region RT1.

Meanwhile, referring to FIG. 8 , a plurality of second openings 451 may be provided in the second region RB2 of the second protective layer 450. Features corresponding to the plurality of second openings 451 may correspond to the first openings 442. Therefore, detailed description of the second opening 451 will be omitted.

Meanwhile, the spacing between the plurality of second openings 451 and/or the planar area of the plurality of second openings 451 are the spacing between the plurality of first openings 442 and/or the plurality of first openings 451. It may be different from the planar area of the opening 442.

Specifically, the opening ratio of the plurality of first openings 442 in the second region (RT2) of the first protective layer 440 is the aperture ratio of the plurality of first openings 442 in the second region (RB2) of the second protective layer 450. may be different from the opening ratio of the plurality of second openings 451. Through this, the embodiment can minimize the occurrence of bending of the strip 200.

In other words, various variables can be considered as a way to solve the bending of the general strip 200. For example, various variables such as changing the material of the insulating layer with a material that has strong properties against bending, changing the design of the circuit pattern layer, changing the thickness of the insulating layer, or changing the number of layers of the circuit board. can be considered. However, the specifications of the circuit board are usually determined according to the product. For example, the material, thickness, error range, and pattern design of each layer constituting the circuit board have already been determined by the design drawing corresponding to the product specifications, and thus can be changed to solve the occurrence of the bending. Items are relatively limited. Accordingly, in the embodiment, the occurrence of warpage can be improved by varying the volumes of the first protective layer 440 and the second protective layer 450 in the second region R2 corresponding to the dummy region.

For example, in the strip 200, the semiconductor 460 may be mounted on the upper surface of the substrate portion. Accordingly, the volume of the circuit pattern layer 420 on the upper surface of the substrate may be different from the volume of the circuit pattern layer 420 on the lower surface of the substrate. And, as a result, the strip 200 may be bent in a smile shape (a shape in which the left and right sides are bent downward around the center). Therefore, in the embodiment, the aperture ratio of the second region RT2 by the first opening 442 of the first protective layer 440 is greater than the aperture ratio of the second region RT2 by the second opening 451 of the first protective layer 440. It may be greater than the aperture ratio of the second region RB2. And, in the embodiment, the occurrence of bending of the strip 200 can be offset through the difference in aperture ratio between the first opening 442 and the second opening 451.

FIG. 9 is a plan view showing a first opening of the first protective layer according to the second embodiment, and FIG. 10 is a plan view showing another first opening according to the third embodiment.

Referring to FIG. 9, the first openings 442 of the first protective layer 440 may be provided in a plurality of groups, which include the first opening 442-1 of the first group and the second opening 442-1 of the first group described above. It may include a first opening 442-2 of the group. Meanwhile, in the first embodiment, the first group of first openings 442-1 and the second group of openings 442-2 are aligned and arranged in the second horizontal direction and spaced apart from each other.

Differently, according to the second embodiment, the first group of first openings 442-1 and the second group of first openings 442-2 are offset from each other or zigzag in the second horizontal direction, which are spaced apart from each other. It can be placed as .

Through this, the embodiment can minimize overflow of the first molding member 470 due to the first opening 442, and thereby further improve mechanical and physical reliability.

Meanwhile, in FIG. 9, a plurality of groups of first openings 442 provided in the first protective layer 440 are shown zigzagly arranged with each other, but a second opening (corresponding to the first opening 442) is shown in FIG. 451) could also be arranged in a zigzag manner.

Additionally, referring to FIG. 10, the first opening 442 may have different sizes for each region. For example, the first opening 442 may have different sizes depending on the density of the circuit pattern layer 420 that vertically overlaps it. Here, the vertically overlapping circuit pattern layer may mean a circuit pattern layer that substantially directly contacts the first protective layer 440.

Specifically, the second region RT2 of the first protective layer 440 includes a first sub-region that vertically overlaps the circuit pattern layer 420 having a relatively low density, and a relative density compared to the first sub-region. It may include a second sub-region that vertically overlaps the circuit pattern layer 420 having a high density.

At this time, when the first openings 442 provided in each of the first sub-region and the second sub-region have the same size, warping may occur due to a difference in density of the circuit pattern layer 420.

Accordingly, the embodiment may apply different sizes of the openings provided in the first sub-region and the second openings provided in the second sub-region.

For example, the first opening 442 may include a first opening 442a provided in the first sub-region and a first opening 442b provided in the second sub-region.

The first opening 442a provided in the first sub-region vertically overlaps the circuit pattern layer 420 having a relatively low density. Accordingly, the first opening 442a provided in the first sub-region may have a relatively larger size than other first openings.

Additionally, the first opening 442b provided in the second sub-region vertically overlaps the circuit pattern layer 420 having a relatively high density. Accordingly, the first opening 442b provided in the second sub-region may have a relatively smaller size than other first openings.

Through this, the embodiment can prevent the strip 200 from being greatly bent in a specific direction due to a difference in density of the circuit pattern layer 420, thereby further improving physical and electrical reliability.

A circuit board strip according to an embodiment may include a substrate portion including a first area corresponding to an effective area and a second area corresponding to a dummy area. A first protective layer may be provided on the upper surface of the substrate and a second protective layer may be provided on the lower surface. Additionally, the first protective layer and the second protective layer may include first and second areas corresponding to the effective area and the dummy area, respectively. At this time, a plurality of first openings spaced apart from each other may be provided in the second region of the first protective layer. Additionally, a plurality of second openings spaced apart from each other may be provided in the second region of the second protective layer. The plurality of first openings and the plurality of second openings may function as a dam to prevent overflow of the molding member during a process of applying the molding member to the first region of the substrate portion. Through this, the embodiment can prevent overflow of the molding member and thus improve reliability.

Meanwhile, each of the first opening and the second opening may have a width on one side adjacent to the first area that is smaller than a width on the other side opposite to the one side. Through this, the embodiment can control the flow of the overflowing molding member while preventing the molding member from overflowing into the second area during the process of applying the molding member. Accordingly, the embodiment can prevent the mold from being contaminated by overflow of the molding member, and prevent excessive overflow of the molding member, thereby ensuring thickness uniformity of the molding member in the first area.

Additionally, the opening ratio of the second region of the first protective layer formed by the plurality of first openings may be different from the opening ratio of the second region of the second protective layer formed by the plurality of second openings. Through this, the embodiment can prevent the substrate from being bent by adjusting the aperture ratio according to the direction in which the substrate is bent, thereby further improving the reliability.

Additionally, the second region of the first protective layer may be divided into a first sub-region and a second sub-region. The first sub-region and the second sub-region may be determined by the density of the circuit pattern layer vertically overlapping therewith. Additionally, the aperture ratio of the plurality of first openings in the first sub-region may be different from the aperture ratio of the plurality of first openings in the second sub-region. Through this, the embodiment can solve the problem of warping caused by the difference in density of the circuit pattern layer, and thereby further improve mechanical and electrical reliability.

Meanwhile, when a circuit board having the characteristics of the above-described invention is used in T devices such as smartphones, server computers, TVs, or home appliances, functions such as signal transmission or power supply can be stably performed. For example, when a circuit board having the characteristics of the present invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can prevent problems such as leakage current or electrical short circuits between terminals. Alternatively, the problem of electrical opening of the terminal supplying the semiconductor chip can be solved. Additionally, if it is responsible for the function of signal transmission, the noise problem can be solved. Through this, the circuit board having the characteristics of the above-described invention can maintain the stable function of IT devices or home appliances, so that the entire product and the circuit board to which the present invention is applied can achieve functional unity or technical interoperability with each other.

When a circuit board having the characteristics of the above-described invention is used in a transportation device such as a vehicle, it is possible to solve the problem of distortion of signals transmitted to the transportation device, or to safely protect the semiconductor chip that controls the transportation device from the outside and prevent leakage. The stability of the transport device can be further improved by solving the problem of electrical short-circuiting between currents or terminals, or the problem of electrical opening of the terminal supplying the semiconductor chip. Therefore, the transportation device and the circuit board to which the present invention is applied can achieve functional unity or technical interoperability with each other.

The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. illustrated in each embodiment can be combined or modified and implemented in other embodiments by a person with ordinary knowledge in the field to which the embodiments belong. Therefore, contents related to such combinations and modifications should be construed as being included in the scope of the present invention.

In addition, although the description has been made focusing on the embodiments above, this is only an example and does not limit the present invention, and those skilled in the art will understand the above examples without departing from the essential characteristics of the present embodiments. You will be able to see that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. And these variations and differences in application should be construed as being included in the scope of the present invention as defined in the appended claims.

Claims (11)

substrate part; and
It includes a protective layer disposed on the substrate portion,
The protective layer includes a first area of an active area and a second area of a dummy area excluding the first area,
The second region of the protective layer has a plurality of openings spaced apart from each other along a circumferential direction of the second region,
A circuit board strip, wherein each of the plurality of openings has a width on one side adjacent the first region less than a width on the other side opposite the one side. According to paragraph 1,
The protective layer is,
a first protective layer disposed on the substrate; and
Comprising a second protective layer disposed under the substrate portion,
Each of the first protective layer and the second protective layer includes the first and second regions,
The opening is,
a plurality of first openings provided in a second region of the first protective layer;
A circuit board strip comprising a plurality of second openings provided in a second region of the second protective layer. According to paragraph 2,
and wherein the second region of the first protective layer vertically overlaps the second region of the second protective layer. According to paragraph 2,
The aperture ratio of the second region of the first protective layer by the plurality of first openings is different from the aperture ratio of the second region of the second protective layer by the plurality of second openings. . According to clause 4,
At least one of the spacing between the plurality of first openings and the area of each of the plurality of first openings is,
A circuit board strip that is different from at least one of a spacing between the plurality of second openings and an area of each of the plurality of second openings. According to paragraph 2,
The substrate part,
insulating layer; and
It includes a circuit pattern layer disposed on the insulating layer,
The circuit board strip of claim 1, wherein the first region of the first protective layer includes an open region vertically overlapping the circuit pattern layer. According to clause 6,
a connection portion disposed on a circuit pattern layer vertically overlapping the open area;
a semiconductor element disposed on the connection portion; and
A circuit board strip comprising a first molding member disposed on the semiconductor device. In clause 7,
and wherein at least a portion of the first molding member is disposed in the first opening in the second region of the first protective layer. According to clause 6,
The second region of the first protective layer is,
Comprising a first sub-region and a second sub-region,
A circuit board, wherein the aperture ratio in the first sub-region of the first protective layer by the plurality of first openings is different from the aperture ratio in the second sub-region of the first protective layer by the plurality of first openings. strip. According to clause 9,
The density of the circuit pattern layer in contact with the first protective layer in the first sub-region is,
A circuit board strip, wherein the density of the circuit pattern layer in contact with the first protective layer in the second sub-region is different. A semiconductor package manufactured by sawing a boundary area between the first and second regions of each of the first and second protective layers in the circuit board strip included in claim 7.

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