KR20240051009A - Display device - Google Patents

Abstract

A display device is provided. A display device according to an embodiment includes a sub-pixel connected to a scan write line, a first data line, and a second data line. The sub-pixel includes a light-emitting device, a first pixel driver that generates a control current according to the first data voltage of the first data line, and a driving current applied to the light-emitting device according to the second data voltage of the second data line. It includes a second pixel driver that generates a second pixel driver, and a third pixel driver that applies the drive current to the light emitting device according to the control current of the first pixel driver. The first pixel driver connects a first transistor to generate the control current according to the first data voltage, and a first electrode of the first transistor according to a scan write signal of the scan write line. 1. It includes a second transistor that applies a data voltage, and a third transistor that connects the gate electrode of the first transistor and the second electrode according to the scan write signal of the scan write line. The third transistor includes a first sub-transistor and a second sub-transistor connected in series between the gate electrode of the first transistor and the second electrode. The channel of the first sub-transistor and the channel of the second sub-transistor overlap the lower gate electrode of the third transistor.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. The display device may be a flat panel display such as a liquid crystal display, a field emission display, or a light emitting display.

The light emitting display device may include an organic light emitting display device including an organic light emitting diode device as a light emitting device, or a light emitting diode display device including an inorganic light emitting diode device such as an LED (Light Emitting Diode) as a light emitting device.

Light emitting diode display devices are inspected to ensure they operate normally before shipping. At this time, the device identifier of the LED display device may be recognized during the inspection process.

The problem to be solved by the present invention is to provide a display device that can prevent the device identifier of a light emitting diode display device from being recognized in an inspection mode.

The problems of the present invention are not limited to the problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

A display device according to an embodiment to solve the above problem includes a sub-pixel connected to a scan write line, a first data line, and a second data line. The sub-pixel includes a light-emitting device, a first pixel driver that generates a control current according to the first data voltage of the first data line, and a driving current applied to the light-emitting device according to the second data voltage of the second data line. It includes a second pixel driver that generates a second pixel driver, and a third pixel driver that applies the drive current to the light emitting device according to the control current of the first pixel driver. The first pixel driver connects a first transistor to generate the control current according to the first data voltage, and a first electrode of the first transistor according to a scan write signal of the scan write line. 1. It includes a second transistor that applies a data voltage, and a third transistor that connects the gate electrode of the first transistor and the second electrode according to the scan write signal of the scan write line. The third transistor includes a first sub-transistor and a second sub-transistor connected in series between the gate electrode of the first transistor and the second electrode. The channel of the first sub-transistor and the channel of the second sub-transistor overlap the lower gate electrode of the third transistor.

A display device according to an embodiment to solve the above problem includes a sub-pixel connected to a scan write line, a first data line, and a second data line. The sub-pixel includes a light-emitting device, a first pixel driver that generates a control current according to the first data voltage of the first data line, and a driving current applied to the light-emitting device according to the second data voltage of the second data line. It includes a second pixel driver that generates a second pixel driver, and a third pixel driver that applies the drive current to the light emitting device according to the control current of the first pixel driver. The second pixel driver connects a first transistor to generate the driving current according to the second data voltage, and a first electrode of the first transistor according to a scan write signal of the scan write line. 2. It includes a second transistor that applies a data voltage, and a third transistor that connects the gate electrode of the first transistor and the second electrode according to the scan write signal of the scan write line. The third transistor includes a first sub-transistor and a second sub-transistor connected in series between the gate electrode of the first transistor and the second electrode. The channel of the first sub-transistor and the channel of the second sub-transistor overlap the lower gate electrode of the third transistor.

A tile-type display device according to an embodiment to solve the above problem includes a plurality of display devices and a joint disposed between the plurality of display devices. Among the plurality of display devices, one display device includes a sub-pixel connected to a scan write line, a first data line, and a second data line. The sub-pixel includes a light-emitting device, a first pixel driver that generates a control current according to the first data voltage of the first data line, and a driving current applied to the light-emitting device according to the second data voltage of the second data line. It includes a second pixel driver that generates a second pixel driver, and a third pixel driver that applies the drive current to the light emitting device according to the control current of the first pixel driver. The first pixel driver connects a first transistor to generate the control current according to the first data voltage, and a first electrode of the first transistor according to a scan write signal of the scan write line. 1. It includes a second transistor that applies a data voltage, and a third transistor that connects the gate electrode of the first transistor and the second electrode according to the scan write signal of the scan write line. The third transistor includes a first sub-transistor and a second sub-transistor connected in series between the gate electrode of the first transistor and the second electrode. The channel of the first sub-transistor and the channel of the second sub-transistor overlap the lower gate electrode of the third transistor.

Specific details of other embodiments are included in the detailed description and drawings.

According to the display device according to the embodiments and the tiled display device including the same, light from the outside is blocked by the lower gate electrode, thereby preventing light from entering the channel of the transistor. Therefore, the light leakage current of the transistor can be reduced and multiple device identifiers can be prevented from being recognized in the inspection mode.

Effects according to the embodiments are not limited to the content exemplified above, and further various effects are included in the present specification.

Figures 1 and 2 are perspective views showing a display device according to one embodiment.
FIG. 3 is a layout diagram showing first to third sub-pixels of a pixel of a display device according to an exemplary embodiment.
Figure 4 is a block diagram showing a display device according to an embodiment.
Figure 5 is an equivalent circuit diagram showing a first sub-pixel according to an embodiment.
FIG. 6 is an equivalent circuit diagram showing the operation of a first sub-pixel in an inspection mode according to an embodiment.
FIG. 7 shows images showing the back of a display device depending on the presence or absence of lighting in an inspection mode according to an embodiment.
Figure 8 is a graph showing light leakage current according to the gate-source voltage of the fourth transistor for each brightness of lighting.
9 is an equivalent circuit diagram showing a first sub-pixel according to another embodiment.
Figure 10 is a graph showing the threshold voltage of the fourth transistor depending on the presence or absence of a lower gate electrode according to another embodiment.
FIG. 11 is a graph showing the driving voltage range of the fourth transistor depending on the presence or absence of a lower gate electrode according to another embodiment.
FIG. 12 is a layout diagram showing a fourth transistor of a first sub-pixel according to another embodiment.
FIG. 13 is a layout diagram showing an 11th transistor of a first sub-pixel according to another embodiment.
Figure 14 is a layout diagram showing the 19th transistor of the first sub-pixel according to another embodiment.
FIG. 15 is a cross-sectional view showing an example of a display panel cut along line A-A' of FIG. 13 .
FIG. 16 is a cross-sectional view showing an example of a display panel cut along line B-B' of FIG. 14.
FIG. 17 is a cross-sectional view showing an example of a display panel cut along line C-C' of FIG. 15.
FIG. 18 is a cross-sectional view showing the Z region of FIG. 17 in detail.
Figure 19 is a graph showing the driving current according to the gate voltage of the fourth transistor for each thickness of the fourth lower gate electrode.
Figure 20 is an equivalent circuit diagram showing a first sub-pixel according to another embodiment.
FIG. 21 is a layout diagram showing a third transistor and a tenth transistor of a first sub-pixel according to another embodiment.
FIG. 22 is a cross-sectional view showing an example of a display panel cut along line DD′ of FIG. 21 .
FIG. 23 is a cross-sectional view showing an example of a display panel taken along line E-E' of FIG. 21.
Figure 24 is an equivalent circuit diagram showing a first sub-pixel according to another embodiment.
Figure 25 is a layout diagram showing the first transistor of the first sub-pixel according to another embodiment.
Figure 26 is a layout diagram showing the eighth transistor of the first sub-pixel according to another embodiment.
FIG. 27 is a cross-sectional view showing an example of a display panel cut along line F-F' of FIG. 25.
FIG. 28 is a cross-sectional view showing an example of a display panel cut along line G-G' of FIG. 25.
Figure 29 is an equivalent circuit diagram showing a first sub-pixel according to another embodiment.
Figure 30 is a graph showing the threshold voltage of the fourth transistor depending on the presence or absence of a lower gate electrode according to another embodiment.
Figure 31 is a graph showing the driving voltage range of the fourth transistor depending on the presence or absence of a lower gate electrode according to another embodiment.
Figure 32 is a layout diagram showing the fourth transistor of the first sub-pixel according to another embodiment.
Figure 33 is a layout diagram showing the 11th transistor of the first sub-pixel according to another embodiment.
FIG. 34 is a cross-sectional view showing the display panel cut along line H-H' of FIG. 32.
FIG. 35 is a cross-sectional view showing the display panel cut along line II′ of FIG. 33 .
Figure 36 is an equivalent circuit diagram showing a first sub-pixel according to another embodiment.
Figure 37 is a layout diagram showing the third transistor and the tenth transistor of the first sub-pixel according to another embodiment.
FIG. 38 is a cross-sectional view showing an example of a display panel cut along line J-J' of FIG. 37.
FIG. 39 is a cross-sectional view showing an example of a display panel cut along line K-K' of FIG. 37.
Figure 40 is an equivalent circuit diagram showing a first sub-pixel according to another embodiment.
Figure 41 is a layout diagram showing the first transistor of the first sub-pixel according to another embodiment.
Figure 42 is a layout diagram showing the eighth transistor of the first sub-pixel according to another embodiment.
FIG. 43 is a cross-sectional view showing an example of a display panel cut along line L-L' of FIG. 41.
FIG. 44 is a cross-sectional view showing an example of a display panel cut along line MM′ of FIG. 42 .
Figure 45 is a perspective view showing a tiled display device including a plurality of display devices according to an embodiment.
FIG. 46 is an enlarged layout diagram showing the Y area of FIG. 45 in detail.
FIG. 47 is a cross-sectional view showing an example of a tile-type display device cut along line N-N' of FIG. 46.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. The present embodiments only serve to ensure that the disclosure of the present invention is complete and that common knowledge in the technical field to which the present invention pertains is not limited. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

When an element or layer is referred to as “on” another element or layer, it includes instances where the element or layer is directly on top of or intervening with the other element. Like reference numerals refer to like elements throughout the specification. The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments are illustrative and the present invention is not limited to the details shown.

Although first, second, etc. are used to describe various components, these components are of course not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be a second component within the technical spirit of the present invention.

Each feature of the various embodiments of the present invention can be combined or combined with each other partially or entirely, and various technical interconnections and operations are possible, and each embodiment can be implemented independently of each other or together in a related relationship. It may be possible.

Hereinafter, specific embodiments will be described with reference to the attached drawings.

Figures 1 and 2 are perspective views showing a display device according to one embodiment.

Referring to FIGS. 1 and 2, the display device 10 according to one embodiment is a device that displays moving images or still images, and may be used in a mobile phone, a smart phone, or a tablet personal computer. ), and portable electronic devices such as smart watches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation, UMPCs (Ultra Mobile PCs), etc. It can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT).

The display device 10 according to an embodiment may include a display panel 100, a circuit board 200, and a source driving circuit 300.

The display panel 100 includes a substrate (SUB), first rear fan-out wires (BFL1), second rear fan-out wires (BFL2), a plurality of pixels (PX), and a plurality of first side wires (SIL1). , a plurality of second side interconnections (SIL2), and a plurality of device identifiers (DID).

The substrate SUB may include a first surface FS, a second surface BS, a plurality of chamfered surfaces CS1 to CS8, and a plurality of side surfaces SS1 to SS8.

The first surface FS may be the front surface of the substrate SUB. The first surface FS may have a rectangular shape with a long side in the first direction DR1 and a short side in the second direction DR2.

The second side BS may be a side facing the first side FS. The second surface BS may be the back surface of the substrate SUB. The second surface BS may have a rectangular shape with a long side in the first direction DR1 and a short side in the second direction DR2. The second side BS may be a side facing the first side FS.

The plurality of chamfered surfaces CS1 to CS8 are formed on the first surface (SIL) to prevent chipping defects from occurring in the plurality of first side wires (SIL) and the plurality of second side wires (SIL2). It refers to the slanted surfaces disposed between FS) and the plurality of side surfaces (SS1 to SS8) and between the second surface (BS) and the plurality of side surfaces (SS1 to SS8). Due to the plurality of chamfered surfaces CS1 to CS8, the bending angle of each of the plurality of first side wirings SIL1 and the plurality of second side wirings SIL2 may be gentle, so that the plurality of first side wirings SIL1 and the plurality of second side wirings SIL2 may have gentle bending angles. It is possible to prevent chipping or cracks from occurring in the (SIL1) and the plurality of second side wirings (SIL2).

The first chamfered surface CS1 may extend from the first side, for example, the lower side, of the first surface FS. The second chamfered surface CS2 may extend from the second side, for example, the left side, of the first surface FS. The third chamfered surface CS3 may extend from the third side, for example, the upper side, of the first surface FS. The fourth chamfered surface CS4 may extend from the fourth side, for example, the right side, of the first surface FS. The interior angle formed by the first surface (FS) and the first chamfer surface (CS1), the interior angle formed by the first surface (FS) and the second chamfer surface (CS2), the first surface (FS) and the third chamfer surface (CS3) The internal angle formed by this and the internal angle formed by the first surface FS and the fourth chamfered surface CS4 may be greater than 90 degrees.

The fifth chamfered surface CS5 may extend from the first side, for example, the lower side, of the second surface BS. The sixth chamfered surface CS6 may extend from the second side, for example, the left side, of the second surface BS. The seventh chamfered surface CS7 may extend from the third side, for example, the upper side, of the second surface BS. The eighth chamfered surface CS8 may extend from the fourth side, for example, the right side, of the second surface BS. The interior angle formed by the second surface (BS) and the fifth chamfer surface (CS5), the interior angle formed by the second surface (BS) and the sixth chamfer surface (CS6), the second surface (BS) and the seventh chamfer surface (CS7) The interior angle formed by this and the interior angle formed by the second surface BS and the eighth chamfer surface CS8 may be greater than 90 degrees.

The first side surface (SS1) may extend from the first chamfered surface (CS1). The first chamfered surface CS1 may be disposed between the first surface FS and the first side surface SS1. The first side surface SS1 may be a lower side of the substrate SUB.

The second side surface (SS2) may extend from the second chamfered surface (CS2). The second chamfered surface CS2 may be disposed between the first surface FS and the second side surface SS2. The second side surface SS2 may be the left side of the substrate SUB.

The third side surface (SS3) may extend from the third chamfered surface (CS3). The third chamfered surface CS3 may be disposed between the first surface FS and the third side surface SS3. The third side surface SS3 may be an upper side of the substrate SUB.

The fourth side surface (SS4) may extend from the fourth chamfered surface (CS4). The fourth chamfered surface CS4 may be disposed between the first surface FS and the fourth side surface SS4. The fourth side surface SS4 may be the right side of the substrate SUB.

A plurality of pixels PX may be disposed on the first surface FS of the substrate SUB to display an image. The plurality of pixels PX may be arranged in a matrix form in the first direction DR1 and the second direction DR2. A description of the plurality of pixels PX will be provided later in conjunction with FIG. 3 .

The plurality of first side wires SIL1 include at least any two of the first surface FS, the second surface BS, the plurality of chamfered surfaces CS1 to CS8, and the plurality of side surfaces SS1 to CS8. SS4) may be placed on at least one side. For example, the plurality of first side wires SIL1 include first pads (not shown) disposed on the first side of the first side FS and the first rear fan out wire (not shown) on the second side BS. In order to connect the BFL1), it may be disposed on the first surface (FS), the second surface (BS), the first chamfer surface (CS1), the fifth chamfer surface (CS5), and the first side surface (SS1) .

The plurality of second side wirings SIL2 include at least any two of the first surface FS, the second surface BS, the plurality of chamfered surfaces CS1 to CS8, and the plurality of side surfaces SS1 to CS8. SS4) may be placed on at least one side. For example, the plurality of second side wires SIL2 may include second pads (not shown) disposed on the second side of the first side FS, which is opposite to the first side, and the second pads (not shown) of the second side BS. 2 To connect the rear fan out wires (BFL2), the first side (FS), the second side (BS), the third chamfered surface (CS3), the seventh chamfered surface (CS7), and the third side (SS3) It can be placed on top.

Each of the plurality of first side wires SIL1 connects the first pads (not shown) arranged on the first side FS and the first rear fan out wire BFL1 arranged on the second side BS. It plays a role. Each of the plurality of second side wires SIL2 connects the second pads (not shown) arranged on the first side FS and the second rear fan out wire BFL2 arranged on the second side BS. It plays a role. First pads (not shown) and second pads (not shown) may correspond to front pads. The first pads (not shown) may be connected to data lines connected to the pixels PX of the substrate SUB. Some of the second pads (not shown) are connected to the first power wiring disposed on the first side FS of the substrate SUB, and other portions are disposed on the first side FS of the substrate SUB. Can be connected to global power wiring.

Each of the plurality of device identifiers (DIDs) may be an identifier such as an identification number assigned to each display device 10 to distinguish the display device 10. A plurality of device identifiers (DID) may be disposed on the second side BS of the substrate SUB. When viewed on a plane, the plurality of device identifiers (DIDs) include first rear fan out wires (BFL1), second rear fan out wires (BFL2), a plurality of first side wires (SIL1), and a plurality of It may be disposed away from the second side wiring SIL2. Additionally, the device identifiers (DIDs) may be arranged away from the plurality of first circuit boards 200 and the second circuit board 400 when viewed in a plan view. That is, a plurality of device identifiers (DIDs) may be electrically floating.

Some of the plurality of device identifiers (DID) may be disposed adjacent to the second chamfered surface CS2, and other portions may be disposed adjacent to the fourth chamfered surface CS4. Some of the plurality of device identifiers (DIDs) may be disposed closer to the first chamfered surface (CS1) than others. Additionally, other portions of the plurality of device identifiers (DIDs) may be disposed closer to the third chamfered surface CS3 than the portions of the plurality of device identifiers (DIDs).

The plurality of device identifiers DID may be rear metal layers formed of the same material and through the same process as the first rear fan-out wires BFL1 and the second rear fan-out wires BFL2. For example, the back metal layer is one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It can be formed as a single layer or multiple layers made of these alloys.

A plurality of first circuit boards 200 may be disposed on the second side BS of the substrate SUB. Each of the plurality of first circuit boards 200 has a first back fan-out wiring ( It can be connected to BFL1). The plurality of first circuit boards 200 may be electrically connected to the plurality of first side wires SIL1 through the first rear fan out wires BFL1. The plurality of first circuit boards 200 may be a flexible printed circuit board, a printed circuit board, or a flexible film.

The second circuit board 400 may be disposed on the second side BS of the substrate SUB. The second circuit board 400 may be connected to the second rear fan out wires BFL2 disposed on the second surface BS of the substrate SUB using a conductive adhesive member. The second circuit board 400 may be electrically connected to a plurality of second side wires SIL2 through second rear fan out wires BFL2. The second circuit board 400 may be a flexible printed circuit board, a printed circuit board, or a flexible film.

Each of the source driving circuits 300 generates data voltages and supplies them to the data lines through the first circuit board 200, the first rear fan out lines BFL1, and the plurality of first side lines SIL1. You can. Each of the source driving circuits 300 may be formed as an integrated circuit (IC) and attached to the corresponding circuit board 200. Alternatively, the source driving circuit 300 may be directly attached to the second surface BS of the substrate SUB using a chip on glass (COG) method.

Each of the source driving circuits 300 generates data voltages and supplies them to the data lines through the first circuit board 200, the first rear fan out lines BFL1, and the plurality of first side lines SIL1. You can. Each of the source driving circuits 300 may be formed as an integrated circuit (IC) and attached to the corresponding circuit board 200. Alternatively, each of the source driving circuits 300 may be directly attached to the second surface BS of the substrate SUB using a chip on glass (COG) method.

The power supply circuit 500 generates predetermined voltages and supplies them to the predetermined voltage wires through the second circuit board 400, the second rear fan out wires (BFL2), and the plurality of second side wires (SIL2). can be supplied. For example, the power supply circuit 500 generates a first power voltage and supplies the voltage through the second circuit board 400, the second rear fan out wires (BFL2), and the plurality of second side wires (SIL2). 1 Can be supplied to power wiring. In addition, the power supply circuit 500 generates a global power voltage (GV) to generate a global power voltage (GV) through the second circuit board 400, the second rear fan out wires (BFL2), and the plurality of second side wires (SIL2). It can be supplied to power wiring. The power supply circuit 500 may be formed as an integrated circuit (IC) and attached to the second circuit board 400. Alternatively, the power supply circuit 500 may be directly attached to the second surface BS of the substrate SUB using a chip on glass (COG) method.

1 and 2 , by using a plurality of first side wires SIL1 and a plurality of second side wires SIL2, the flexible film bent along the side of the substrate SUB can be eliminated. Because of this, a bezel-less display device can be implemented.

FIG. 3 is a layout diagram showing first to third sub-pixels of a pixel according to an exemplary embodiment.

Referring to FIG. 3, each pixel PX may include a plurality of sub-pixels RP, GP, and BP. In FIG. 3, each of the pixels PX includes three sub-pixels (RP, GP, BP), that is, a first sub-pixel (RP), a second sub-pixel (GP), and a third sub-pixel (BP). Although this has been exemplified, the embodiments of the present specification are not limited thereto. The first sub-pixel (RP), the second sub-pixel (GP), and the third sub-pixel (BP) each have one of the PWM data lines (DL), the first to third data lines (RDL, GDL, BDL) and at least one of scan wires (GWL, GIL, GCL, SWPL, PAEL, PWEL).

Each of the first sub-pixel (RP), the second sub-pixel (GP), and the third sub-pixel (BP) may have a rectangular, square, or diamond planar shape. For example, the first sub-pixel (RP), the second sub-pixel (GP), and the third sub-pixel (BP) each have a short side in the first direction (DR1) and a short side in the second direction (DR2) as shown in FIG. 3. It may have a rectangular plan shape with long sides. Alternatively, each of the first sub-pixel (RP), the second sub-pixel (GP), and the third sub-pixel (BP) includes sides having the same length in the first direction (DR1) and the second direction (DR2). It may have a square or rhombus planar shape.

As shown in FIG. 3 , the first sub-pixel RP, the second sub-pixel GP, and the third sub-pixel BP may be arranged in the first direction DR1. Alternatively, one of the second sub-pixel GP and the third sub-pixel BP and the first sub-pixel RP are arranged in the first direction DR1, and the other one and the first sub-pixel RP are arranged in the first direction DR1. It may be arranged in the second direction DR2. For example, the first sub-pixel (RP) and the second sub-pixel (GP) are arranged in the first direction (DR1), and the first sub-pixel (RP) and the third sub-pixel (BP) are arranged in the second direction ( DR2). Alternatively, one of the first sub-pixel RP and the third sub-pixel BP and the second sub-pixel GP are arranged in the first direction DR1, and the other one and the second sub-pixel GP are arranged in the first direction DR1. It may be arranged in the second direction DR2. Alternatively, one of the first sub-pixel RP and the second sub-pixel GP and the third sub-pixel BP are arranged in the first direction DR1, and the other one and the third sub-pixel BP are arranged in the first direction DR1. It may be arranged in the second direction DR2.

The first sub-pixel (RP) may emit first light, the second sub-pixel (GP) may emit second light, and the third sub-pixel (BP) may emit third light. Here, the first light may be light in a red wavelength band, the second light may be light in a green wavelength band, and the third light may be light in a blue wavelength band. The red wavelength band is a wavelength band of approximately 600 nm to 750 nm, the green wavelength band is a wavelength band of approximately 480 nm to 560 nm, and the blue wavelength band may be a wavelength band of approximately 370 nm to 460 nm, but in the present specification The examples are not limited thereto.

Each of the first sub-pixel (RP), the second sub-pixel (GP), and the third sub-pixel (BP) is a light-emitting device that emits light and may include an inorganic light-emitting device having an inorganic semiconductor. For example, the inorganic light emitting device may be a flip chip type micro LED (Light Emitting Diode), but embodiments of the present specification are not limited thereto.

As shown in FIG. 3, the area of the first sub-pixel (RP), the area of the second sub-pixel (GP), and the area of the third sub-pixel (BP) may be substantially the same, but the embodiments of the present specification are limited to this. It doesn't work. At least one of the area of the first sub-pixel (RP), the area of the second sub-pixel (GP), and the area of the third sub-pixel (BP) may be different from the other one. Alternatively, among the area of the first sub-pixel (RP), the area of the second sub-pixel (GP), and the area of the third sub-pixel (BP), any two may be substantially the same and the other may be different from the above two. You can. Alternatively, the area of the first sub-pixel (RP), the area of the second sub-pixel (GP), and the area of the third sub-pixel (BP) may be different from each other.

Figure 4 is a block diagram showing a display device according to an embodiment.

Referring to FIG. 4 , the display device 10 includes a display panel 100, a scan driving circuit 110, a data driving circuit 300G, a timing control circuit 600, and a power supply circuit 500.

The display area (DA) of the display panel 100 includes sub-pixels (RP, GP, BP) that display images, scan write lines (GWL) connected to the sub-pixels (RP, GP, BP), and scan initialization. Wires (GIL), scan control wires (GCL), sweep signal wires (SWL), PWM light emission wires (PWEL), PAM light emission wires (PAEL), PWM data wires (DL), first data wire (RDL), second data lines (GDL), and third data lines (BDL).

Scan write lines (GWL), scan initialization lines (GIL), scan control lines (GCL), sweep signal lines (SWL), PWM light emitting lines (PWEL), and PAM light emitting lines (PAEL) are first It may extend in a direction (X-axis direction) and be arranged in a second direction (Y-axis direction) that intersects the first direction (X-axis direction). The PWM data lines (DL), first data lines (RDL), second data lines (GDL), and third data lines (BDL) extend in the second direction (Y-axis direction) and extend in the first direction. It can be arranged in (X-axis direction). The first data lines (RDL) may be electrically connected to each other, the second data lines (GDL) may be electrically connected to each other, and the third data lines (BDL) may be electrically connected to each other.

The sub-pixels (RP, GP, BP) include a first sub-pixel (RP) emitting the first light, a second sub-pixel (GP) emitting the second light, and a third sub-pixel (GP) emitting the third light. It may include sub-pixels (BP). The first light refers to the light in the red wavelength band, the second light refers to the light in the green wavelength band, and the third light refers to the light in the blue wavelength band. For example, the main peak wavelength of the first light is located at approximately 600 nm to 750 nm, the main peak wavelength of the second light is located at approximately 480 nm to 560 nm, and the main peak wavelength of the third light is approximately 370 nm to 460 nm. It can be located in .

Each of the sub-pixels (RP, GP, BP) has one of the scan write lines (GWL), one of the scan initialization lines (GIL), one of the scan control lines (GCL), and a sweep signal line (SWL). ), any one of the PWM light emitting wires (PWEL), and any one of the PAM light emitting wires (PAEL). Additionally, each of the first sub-pixels RP may be connected to one of the PWM data lines DL and one of the first data lines RDL. Additionally, each of the second sub-pixels (GP) may be connected to one of the PWM data lines (DL) and one of the second data lines (GDL). Additionally, each of the third sub-pixels BP may be connected to one of the PWM data lines DL and one of the third data lines BDL.

The non-display area NDA of the display panel 100 may include a scan driving circuit 110, a first demux unit DMX1, and a second demux unit DMX2.

The scan driving circuit 110 includes scan write lines (GWL), scan initialization lines (GIL), scan control lines (GCL), sweep signal lines (SPWL), PWM light emission lines (PWEL), and PAM light emission lines. A scan driving circuit 110 may be disposed to apply signals to the wires (PAEL). Although FIG. 1 illustrates that the scan driving circuit 110 is disposed at one edge of the display panel 100, the present invention is not limited thereto. The scan driving circuit 110 may be disposed on both edges of the display panel 100 .

The scan driving circuit 110 may include a first scan signal driving circuit 111, a second scan signal driving circuit 112, a sweep signal driving circuit 113, and a light emitting signal driving circuit 114.

The first scan signal driving circuit 111 may receive the first scan driving control signal GDCS1 from the timing control circuit 600. The first scan signal driving circuit 111 outputs scan initialization signals to the scan initialization lines (GIL) and scan write signals to the scan write lines (GWL) according to the first scan driving control signal (GDCS1). You can. That is, the first scan signal driving circuit 111 may output two scan signals, that is, scan initialization signals and scan write signals.

The second scan signal driving circuit 112 may receive the second scan driving control signal GDCS2 from the timing control circuit 600. The second scan signal driving circuit 112 may output scan control signals to the scan control lines (GCL) according to the second scan driving control signal (GDCS2).

The sweep signal driving circuit 113 may receive the first emission control signal (ECS1) and the sweep control signal (SPCS) from the timing control circuit 600. The sweep signal driving circuit 113 may output PWM emission signals to the PWM emission wires (PWEL) and sweep signals to the sweep signal wires (SWPL) according to the first emission control signal (ECS1). That is, the sweep signal driving circuit 113 can output PWM emission signals and sweep signals together.

The emission signal driving circuit 114 may receive the second emission control signal ECS2 from the timing control circuit 600. The light emission signal driving circuit 114 may output PAM light emission signals to the PAM light emission lines (PAEL) according to the second light emission control signal ECS2.

The first demux unit (DMX1) switches the connection between each PWM data wire (DL) and the global power wire (GVL). In addition, the first demux unit (DMX1) switches the connection between each first data line (RDL) and the first data voltage line (RPL), and switches the connection between each second data line (GDL) and the second data voltage line. The connection between the wires (GPL) is switched, and the connection between each third data line (BDL) and the third data voltage line (BPL) is switched.

The second demux unit DMX2 may be disposed between the fan out wires FL and the PWM data wires DL. The second demux unit (DMX2) divides the PWM data voltages applied to each fan-out wire (FL) into Q (Q is an integer of 2 or more) PWM data wires (DL) or Q first to third data wires. It can be distributed to fields (RDL, GDL, BDL).

The first demux unit DMX1 may be disposed adjacent to the second pads PD2, and the second demux unit DMX2 may be disposed adjacent to the first pads PD1. That is, the first demux unit DMX1 may be disposed adjacent to one side of the display panel 100, for example, below the display panel 100. The second demux unit DMX2 may be disposed adjacent to the other side of the display panel 100, for example, on the upper side of the display panel 100.

The timing control circuit 600 receives digital video data (DATA) and timing signals (TSS). The timing control circuit 600 includes a first scan drive control signal (GDCS1), a second scan drive control signal (GDSC2), and a first scan drive control signal (GDCS1) for controlling the operation timing of the scan drive circuit 110 according to the timing signals (TSS). An emission control signal (ECS1), a second emission control signal (ECS2), and a sweep control signal (SWCS) may be generated. Additionally, the timing control circuit 600 may generate a source control signal (DCS) for controlling the operation timing of the data driving circuit 300G.

The timing control circuit 600 includes a first scan drive control signal (GDCS1), a second scan drive control signal (GDSC2), a first emission control signal (ECS1), a second emission control signal (ECS2), and a sweep control signal ( SWCS) is output to the scan driving circuit 110. The timing control circuit 600 outputs digital video data (DATA) and a PWM control signal (DCS) to the data driving circuit 300G.

The data driving circuit 300G may include a plurality of source driving circuits 300. The data driving circuit 300G converts digital video data (DATA) into analog PWM data voltages and outputs them to the fan-out wires (FL).

The power supply circuit 500 generates a first data voltage and outputs it to the first data voltage line (RPL), generates a second data voltage and outputs it to the second data voltage line (GPL), and generates a third data voltage. It can be generated and output to the third data voltage line (BPL). The power supply circuit 500 may generate a global power voltage (GV) and output it to the global power line (GVL).

Additionally, the power supply circuit 500 may generate a plurality of power voltages and output them to the display panel 100 . For example, the power supply circuit 500 includes a first power voltage (VDD1), a second power voltage (VDD2), a third power voltage (VSS), an initialization voltage (VINT), a gate-on voltage (VGL), and a gate Off voltage (VGH) can be output to the display panel 100. The first power voltage VDD1 and the second power voltage VDD2 may be high-potential driving voltages for driving the light-emitting devices of each of the sub-pixels RP, GP, and BP. The third power voltage VSS may be a low-potential driving voltage for driving the light emitting device of each of the sub-pixels RP, GP, and BP. The initialization voltage (VINT) and gate-off voltage (VGH) are applied to each of the sub-pixels (RP, GP, BP), and the gate-on voltage (VGL) and gate-off voltage (VGH) are applied to the scan driving circuit 110. It can be.

Figure 5 is a circuit diagram showing a first sub-pixel according to one embodiment.

Referring to FIG. 5, the first sub-pixel RP according to one embodiment includes a k-th scan write line (GWLk), a k-th scan initialization line (GILk), a k-th scan control line (GCLk), and a k-th sweep signal. It can be connected to the wiring (SWPLk), the kth PWM light emitting wiring (PWELk), and the kth PAM light emitting wiring (PAELk). Additionally, the first sub-pixel RP may be connected to the jth PWM data line DLj and the first data line RDL. In addition, the first sub-pixel (RP) includes a first power line (VDL1) to which the first power voltage (VDD1) is applied, a second power line (VDL2) to which the second power voltage (VDD2) is applied, and a third power supply voltage. It may be connected to a third power line (VSL) to which (VSS) is applied, an initialization voltage line (VIL) to which the initialization voltage (VINT) is applied, and a gate-off voltage line (VGHL) to which the gate-off voltage (VGH) is applied. . Meanwhile, for convenience of explanation, the jth PWM data line DLj may be referred to as a first data line, and the first data line RDL may be referred to as a second data line.

The first sub-pixel (RP) may include a light emitting element (EL), a first pixel driver (PDU1), a second pixel driver (PDU2), and a third pixel driver (PDU3).

The light emitting element EL emits light according to the driving current generated by the second pixel driver PDU2. The light emitting element EL may be disposed between the 17th transistor T17 and the third power line VSL. The first electrode of the light emitting element EL may be connected to the second electrode of the 17th transistor T17, and the second electrode may be connected to the third power line VSL. The first electrode of the light emitting element EL may be an anode electrode, and the second electrode may be a cathode electrode. The light emitting device EL may be an inorganic light emitting device including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. For example, the light emitting element (EL) may be a micro light emitting diode made of an inorganic semiconductor, but is not limited thereto.

The first pixel driver PDU1 controls the voltage of the third node N3 of the third pixel driver PDU3 by generating a control current according to the j PWM data voltage of the j PWM data line DLj. Since the pulse width of the driving current flowing through the light-emitting device EL can be adjusted by the control current of the first pixel driver PDU1, the first pixel driver PDU1 modulates the pulse width of the driving current flowing through the light-emitting device EL. It may be a pulse width modulation unit (PWM unit) that performs (pulse width modulation).

The first pixel driver PDU1 may include first to seventh transistors T1 to T7 and a first capacitor C1.

The first transistor T1 controls the control current flowing between the first electrode and the second electrode according to the PWM data voltage applied to the gate electrode.

The second transistor T2 is turned on by the kth scan write signal of the kth scan write line GWLk, and the PWM data voltage of the jth PWM data line DLj is applied to the first electrode of the first transistor T1. supply to. The gate electrode of the second transistor T2 is connected to the kth scan write line GWLk, the first electrode is connected to the jth PWM data line DLj, and the second electrode is connected to the kth scan write line GWLk. Can be connected to 1 electrode.

The third transistor T3 is turned on by the kth scan initialization signal of the kth scan initialization line GILk and connects the initialization voltage line VIL to the gate electrode of the first transistor T1. Because of this, the gate electrode of the first transistor (T1) may be discharged to the initialization voltage (VINT) of the initialization voltage line (VIL) while the third transistor (T3) is turned on. At this time, the gate-on voltage (VGL) of the kth scan initialization signal may be different from the initialization voltage (VINT) of the initialization voltage line (VIL). In particular, since the difference voltage between the gate-on voltage (VGL) and the initialization voltage (VINT) is greater than the threshold voltage of the third transistor (T3), even after the initialization voltage (VINT) is applied to the gate electrode of the first transistor (T1) The third transistor T3 can be stably turned on. Accordingly, when the third transistor T3 is turned on, the initialization voltage VINT can be stably applied to the gate electrode of the first transistor T1 regardless of the threshold voltage of the third transistor T3.

The third transistor T3 may include a plurality of transistors connected in series. For example, the third transistor T3 may include a first sub-transistor T31 and a second sub-transistor T32. As a result, the voltage of the gate electrode of the first transistor T1 can be prevented from leaking through the third transistor T3. The gate electrode of the first sub-transistor T31 is connected to the kth scan initialization line GILk, the first electrode is connected to the gate electrode of the first transistor T1, and the second electrode is connected to the second sub-transistor T32. ) can be connected to the first electrode. The gate electrode of the second sub-transistor T32 is connected to the k-th scan initialization line GILk, the first electrode is connected to the second electrode of the first sub-transistor T31, and the second electrode is connected to the initialization voltage line (GILk). VIL) can be connected.

The fourth transistor T4 is turned on by the kth scan write signal of the kth scan write line GWLk and connects the gate electrode and the second electrode of the first transistor T1. Because of this, the first transistor T1 can operate as a diode while the fourth transistor T4 is turned on.

The fourth transistor T4 may include a plurality of transistors connected in series. For example, the fourth transistor T4 may include a third sub-transistor T41 and a fourth sub-transistor T42. As a result, the voltage of the gate electrode of the first transistor T1 can be prevented from leaking through the fourth transistor T4. The gate electrode of the third sub-transistor T41 is connected to the k-th scan write line GWLk, the first electrode is connected to the second electrode of the first transistor T1, and the second electrode is connected to the fourth sub-transistor ( It may be connected to the first electrode of T42). The gate electrode of the fourth sub-transistor T42 is connected to the k-th scan write line GWLk, the first electrode is connected to the second electrode of the third sub-transistor T41, and the second electrode is connected to the first transistor ( It can be connected to the gate electrode of T1).

The fifth transistor T5 is turned on by the kth PWM light emission signal of the kth PWM light emission line PWELk and connects the first electrode of the first transistor T1 to the first power line VDL1. The gate electrode of the fifth transistor (T5) is connected to the kth PWM light emitting line (PWELk), the first electrode is connected to the first power line (VDL1), and the second electrode is connected to the first power line (VDL1) of the first transistor (T1). Can be connected to an electrode.

The sixth transistor T6 is turned on by the kth PWM light emission signal of the kth PWM light emission line PWELk to connect the second electrode of the first transistor T1 to the third node (PDU3) of the third pixel driver PDU3. Connect to N3). The gate electrode of the sixth transistor (T6) is connected to the kth PWM light emitting wiring (PWELk), the first electrode is connected to the second electrode of the first transistor (T1), and the second electrode is connected to the third pixel driver (PDU3). ) can be connected to the third node (N3).

The seventh transistor (T7) is turned on by the kth scan control signal of the kth scan control line (GCLk) to reduce the gate-off voltage (VGH) of the gate-off voltage line (VGHL) to the kth sweep signal line (SWPLk). It can be supplied to the first node (N1) connected to . As a result, the period during which the initialization voltage (VINT) is applied to the gate electrode of the first transistor (T1), the PWM data voltage of the j-th PWM data line (DLj), and the threshold voltage (Vth1) of the first transistor (T1) are programmed. During this period, the voltage change of the gate electrode of the first transistor T1 can be prevented from being reflected in the k-th sweep signal of the k-th sweep signal line SWPLk by the first capacitor C1. The gate electrode of the seventh transistor T7 may be connected to the kth scan control line GCLk, the first electrode may be connected to the gate-off voltage line VGHL, and the second electrode may be connected to the first node N1. there is.

The first capacitor C1 may be disposed between the gate electrode of the first transistor T1 and the first node N1. One electrode of the first capacitor C1 may be connected to the gate electrode of the first transistor T1, and the other electrode may be connected to the first node N1.

The first node N1 may be a contact point of the k sweep signal line SWPLk, the second electrode of the seventh transistor T7, and the other electrode of the first capacitor C1.

The second pixel driver PDU2 generates a driving current applied to the light emitting element EL according to the first PWM data voltage of the first data line RDL. The second pixel driver PDU2 may be a pulse amplitude modulation unit (PAM unit) that performs pulse amplitude modulation. The second pixel driver PDU2 may be a constant current generator that generates a constant driving current according to the first PWM data voltage.

Additionally, the second pixel driver PDU2 of each of the first sub-pixels RP may receive the same first PWM data voltage and generate the same driving current regardless of the luminance of the first sub-pixel RP. Likewise, the second pixel driver PDU2 of each of the second sub-pixels GP may receive the same second PWM data voltage and generate the same driving current regardless of the luminance of the second sub-pixel GP. The third pixel driver PDU3 of each of the third sub-pixels BP may receive the same third PWM data voltage and generate the same driving current regardless of the luminance of the third sub-pixel BP.

The second pixel driver PDU2 may include the 8th to 14th transistors T8 to T14 and the second capacitor C2.

The eighth transistor T8 controls the driving current flowing to the light emitting element EL according to the voltage applied to the gate electrode.

The ninth transistor T9 is turned on by the kth scan write signal of the kth scan write line GWLk, and the first PWM data voltage of the first data line RDL is converted to the first PWM data voltage of the eighth transistor T8. supply to the electrode. The gate electrode of the eighth transistor T8 is connected to the kth scan write line GWLk, the first electrode is connected to the first data line RDL, and the second electrode is connected to the first electrode of the eighth transistor T1. Can be connected to an electrode.

The tenth transistor T10 is turned on by the kth scan initialization signal of the kth scan initialization line GILk and connects the initialization voltage line VIL to the gate electrode of the eighth transistor T8. For this reason, while the tenth transistor T10 is turned on, the gate electrode of the eighth transistor T8 may be discharged to the initialization voltage VINT of the initialization voltage line VIL. At this time, the gate-on voltage (VGL) of the kth scan initialization signal may be different from the initialization voltage (VINT) of the initialization voltage line (VIL). In particular, since the difference voltage between the gate-on voltage (VGL) and the initialization voltage (VINT) is greater than the threshold voltage of the tenth transistor (T10), even after the initialization voltage (VINT) is applied to the gate electrode of the eighth transistor (T8) The tenth transistor T10 can be stably turned on. Accordingly, when the tenth transistor T10 is turned on, the initialization voltage VINT can be stably applied to the gate electrode of the eighth transistor T8 regardless of the threshold voltage of the tenth transistor T10.

The tenth transistor T10 may include a plurality of transistors connected in series. For example, the tenth transistor T10 may include a fifth sub-transistor T101 and a sixth sub-transistor T102. As a result, the voltage of the gate electrode of the eighth transistor T8 can be prevented from leaking through the tenth transistor T10. The gate electrode of the fifth sub-transistor (T101) is connected to the k-th scan initialization line (GILk), the first electrode is connected to the gate electrode of the eighth transistor (T8), and the second electrode is connected to the sixth sub-transistor (T102). ) can be connected to the first electrode. The gate electrode of the sixth sub-transistor T102 is connected to the k-th scan initialization line (GILk), the first electrode is connected to the second electrode of the fifth sub-transistor T101, and the second electrode is connected to the initialization voltage line (GILk). VIL) can be connected.

The eleventh transistor T11 is turned on by the kth scan write signal of the kth scan write line GWLk and connects the gate electrode and the second electrode of the eighth transistor T8. Because of this, the eighth transistor T8 can operate as a diode while the eleventh transistor T11 is turned on.

The eleventh transistor T11 may include a plurality of transistors connected in series. For example, the 11th transistor T11 may include the 7th sub-transistor T111 and the 8th sub-transistor T112. As a result, the voltage of the gate electrode of the eighth transistor T8 can be prevented from leaking through the eleventh transistor T11. The gate electrode of the seventh sub-transistor T111 is connected to the k-th scan write line GWLk, the first electrode is connected to the second electrode of the eighth transistor T8, and the second electrode is connected to the eighth sub-transistor ( It may be connected to the first electrode of T112). The gate electrode of the eighth sub-transistor T112 is connected to the k-th scan write line GWLk, the first electrode is connected to the second electrode of the seventh sub-transistor T111, and the second electrode is connected to the eighth transistor ( It can be connected to the gate electrode of T8).

The twelfth transistor T12 is turned on by the kth PWM light emission signal of the kth PWM light emission line PWELk and connects the first electrode of the eighth transistor T8 to the second power line VDL2. The gate electrode of the twelfth transistor T12 is connected to the kth PWM light emitting line PWELk, the first electrode is connected to the first power line VDL1, and the second electrode is connected to the first electrode of the eighth transistor T8. Can be connected to an electrode.

The thirteenth transistor T13 is turned on by the kth scan control signal of the kth scan control line GCLk and connects the first power line VDL1 to the second node N2. The gate electrode of the thirteenth transistor T13 may be connected to the kth scan control line GCLk, the first electrode may be connected to the first power line VDL1, and the second electrode may be connected to the second node N2. there is.

The fourteenth transistor T14 is turned on by the kth PWM light emission signal of the kth PWM light emission line PWELk and connects the second power line VDL2 to the second node N2. Because of this, when the fourteenth transistor T14 is turned on, the second power voltage VDD2 of the second power line VDL2 may be supplied to the second node N2. The gate electrode of the fourteenth transistor T14 may be connected to the kth PWM light emitting line PWELk, the first electrode may be connected to the second power line VDL2, and the second electrode may be connected to the second node N2. there is.

The second capacitor C2 may be disposed between the gate electrode of the eighth transistor T8 and the second node N2. One electrode of the second capacitor C2 may be connected to the gate electrode of the eighth transistor T8, and the other electrode may be connected to the second node N2.

The second node N2 may be a contact point of the second electrode of the 13th transistor T13, the second electrode of the 14th transistor T14, and the other electrode of the second capacitor C2.

The third pixel driver PDU3 adjusts the period during which the driving current is applied to the light emitting element EL according to the voltage of the third node N3.

The third pixel driver PDU3 may include 15th to 19th transistors T15 to T19 and a third capacitor C3.

The fifteenth transistor T15 is turned on or turned off depending on the voltage of the third node N3. When the 15th transistor (T15) is turned on, the driving current of the 8th transistor (T8) is supplied to the light emitting element (EL), and when the 15th transistor (T15) is turned off, the 8th transistor (T8) The driving current may not be supplied to the light emitting element EL. Therefore, the turn-on period of the fifteenth transistor T15 may be substantially the same as the light emission period of the light emitting element EL. The gate electrode of the fifteenth transistor T15 is connected to the third node N3, the first electrode is connected to the second electrode of the eighth transistor T8, and the second electrode is connected to the second electrode of the seventeenth transistor T17. Can be connected to 1 electrode.

The sixteenth transistor T16 is turned on by the kth scan control signal of the kth scan control line GCLk and connects the initialization voltage line VIL to the third node N3. Because of this, the third node N3 may be discharged to the initialization voltage of the initialization voltage line VIL while the 16th transistor T16 is turned on.

The sixteenth transistor T16 may include a plurality of transistors connected in series. For example, the 16th transistor T16 may include a 9th sub-transistor T161 and a 10th sub-transistor T162. As a result, the voltage of the third node N3 can be prevented from leaking through the 16th transistor T16. The gate electrode of the ninth sub-transistor T161 is connected to the k-th scan control line GCLk, the first electrode is connected to the third node N3, and the second electrode is connected to the k-th scan control line GCLk. Can be connected to 1 electrode. The gate electrode of the tenth sub-transistor (T162) is connected to the k-th scan control line (GCLk), the first electrode is connected to the second electrode of the ninth sub-transistor (T161), and the second electrode is connected to the initialization voltage line ( VIL) can be connected.

The 17th transistor T17 is turned on by the kth PAM light emission signal of the kth PAM light emission line PAELk, and connects the second electrode of the 15th transistor T15 to the first electrode of the light emitting element EL. . The gate electrode of the 17th transistor T17 is connected to the kth PAM light emitting wiring PAELk, the first electrode is connected to the second electrode of the 15th transistor T15, and the second electrode is connected to the light emitting element EL. It can be connected to the first electrode.

The eighteenth transistor T18 is turned on by the kth scan control signal of the kth scan control line GCLk and connects the initialization voltage line VIL to the first electrode of the light emitting element EL. Because of this, the first electrode of the light emitting device EL may be discharged to the initialization voltage of the initialization voltage line VIL during the period in which the 18th transistor T18 is turned on. The gate electrode of the 18th transistor T18 is connected to the kth scan control line GCLk, the first electrode is connected to the first electrode of the light emitting element EL, and the second electrode is connected to the initialization voltage line VIL. can be connected

The 19th transistor T19 is turned on by the test signal of the test signal line TSTL and connects the first electrode of the light emitting device EL to the third power line VSL. The gate electrode of the 19th transistor T19 is connected to the test signal line TSTL, the first electrode is connected to the first electrode of the light emitting element EL, and the second electrode is connected to the third power line VSL. You can.

The third capacitor C3 may be disposed between the third node N3 and the initialization voltage line VIL. One electrode of the third capacitor C3 may be connected to the third node N3, and the other electrode may be connected to the initialization voltage line VIL.

The third node N3 includes the second electrode of the sixth transistor T6, the gate electrode of the fifteenth transistor T15, the first electrode of the ninth sub-transistor T161, and one electrode of the third capacitor C3. It may be a contact point of .

One of the first and second electrodes of each of the first to nineteenth transistors T1 to T19 may be a source electrode, and the other may be a drain electrode. The active layer of each of the first to 19th transistors T1 to T19 may be formed of any one of poly silicon, amorphous silicon, and oxide semiconductor. When the active layer of each of the first to nineteenth transistors T1 to T19 is polysilicon, it may be formed through a low temperature poly silicon (LTPS) process.

In addition, in FIG. 2, the description focuses on the fact that each of the first to 19th transistors T1 to T19 is formed of a P-type MOSFET, but the embodiments of the present specification are not limited thereto. For example, each of the first to 19th transistors T1 to T19 may be formed as an N-type MOSFET.

Alternatively, in order to block the leakage current and increase the black expression ability of the light emitting device (EL), the first sub-transistor (T31) and the second sub-transistor (T32) of the third transistor (T3) in the first sub-pixel (RP) , the third sub-transistor (T41) and fourth sub-transistor (T42) of the fourth transistor (T4), the fifth sub-transistor (T101) and the sixth sub-transistor (T102) of the tenth transistor (T10), and the eleventh sub-transistor (T102) of the fourth transistor (T4). The seventh sub-transistor T111 and the eighth sub-transistor T112 of the transistor T11 may be formed of an N-type MOSFET. In this case, the gate electrode of the third sub-transistor T41 of the fourth transistor T4, the gate electrode of the fourth sub-transistor T42, and the gate electrode of the seventh sub-transistor T111 of the eleventh transistor T11. and the gate electrode of the eighth sub-transistor T112 may be connected to the kth control signal GNLk. The kth scan initialization signal (GILk) and the kth control signal (GNLk) may have pulses generated by the gate-off voltage (VGH). In addition, the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3, the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4, and the tenth sub-transistor T42 of the third transistor T3. The active layers of the fifth sub-transistor T101 and sixth sub-transistor T102 of the transistor T10, and the seventh sub-transistor T111 and eighth sub-transistor T112 of the eleventh transistor T11 are oxide semiconductors. and the remaining transistors may be formed of polysilicon.

Alternatively, one of the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3 may be formed as an N-type MOSFET, and the other may be formed as a P-type MOSFET. In this case, among the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3, the transistor formed as an N-type MOSFET is made of an oxide semiconductor, and the transistor formed as a P-type MOSFET is made of polysilicon. can be formed.

Alternatively, one of the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4 may be formed as an N-type MOSFET, and the other may be formed as a P-type MOSFET. In this case, among the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4, the transistor formed as an N-type MOSFET is made of an oxide semiconductor, and the transistor formed as a P-type MOSFET is made of polysilicon. can be formed.

Alternatively, one of the fifth sub-transistor T101 and the sixth sub-transistor T102 of the tenth transistor T10 may be formed of an N-type MOSFET, and the other may be formed of a P-type MOSFET. In this case, among the fifth sub-transistor T101 and the sixth sub-transistor T102 of the tenth transistor T10, the transistor formed as an N-type MOSFET is formed of an oxide semiconductor, and the transistor formed as a P-type MOSFET is made of polysilicon. can be formed.

Alternatively, one of the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11 may be formed as an N-type MOSFET, and the other may be formed as a P-type MOSFET. In this case, among the seventh sub-transistor T111 and the eighth sub-transistor T112 of the eleventh transistor T11, the transistor formed of an N-type MOSFET is formed of an oxide semiconductor, and the transistor formed of a P-type MOSFET is formed of polysilicon. can be formed.

Meanwhile, the second sub-pixel (GP) and the third sub-pixel (BP) according to one embodiment may be substantially the same as the first sub-pixel (RP) described in connection with FIG. 2 . Therefore, description of the second sub-pixel (GP) and third sub-pixel (BP) according to one embodiment is omitted.

FIG. 6 is an equivalent circuit diagram showing the operation of a first sub-pixel in an inspection mode according to an embodiment.

Referring to FIG. 6, the inspection mode is a short-circuit or open (or disconnection) path of the current flowing through the first transistor (T1), third transistor (T3), and fourth transistor (T4) of the first pixel driver (PDU1). ) is a mode to check. In the inspection mode, the first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), and the seventh transistor (T7) of the first pixel driver (PDU1) are turned on. and the fifth transistor T5 and sixth transistor T6 of the first pixel driver PDU1 may be turned off.

Due to the turn-on of the first transistor (T1), second transistor (T2), third transistor (T3), and fourth transistor (T4) in the test mode, the j-th data line in the first pixel driver (PDU1) Current may flow from (DLj) to the initialization voltage line (VIL) through the second transistor (T2), the first transistor (T1), the third transistor (T3), and the fourth transistor (T4). As the current is detected, the path of the current flowing through the first transistor T1, third transistor T3, and fourth transistor T4 of the first pixel driver PDU1 is short-circuited or opened (or disconnected). can be inspected.

For example, when the current value is 0, the path of the current flowing through the first transistor T1, third transistor T3, and fourth transistor T4 of the first pixel driver PDU1 is open (or It can be determined that a disconnection has occurred. In addition, when the current value is greater than the first threshold value, the path of the current flowing through the first transistor T1, third transistor T3, and fourth transistor T4 of the first pixel driver PDU1 is short-circuited. It can be determined that this has occurred. That is, when the current value is greater than 0 and less than the first threshold, the path of the current flowing through the first transistor T1, third transistor T3, and fourth transistor T4 of the first pixel driver PDU1. It can be determined that there is no short circuit or open (or disconnection) in .

FIG. 7 shows current pattern images of a display device depending on the presence or absence of lighting in an inspection mode according to an embodiment. Figure 7 (a) is a current pattern image of the display device when there is lighting, and Figure 7 (b) is a current pattern image of the display device when there is no lighting.

Referring to FIG. 7, a plurality of devices are electrically floating according to the current flowing through the first transistor (T1), third transistor (T3), and fourth transistor (T4) of the first pixel driver (PDU1) according to the test mode. Device identifiers (DIDs) may be recognized. Specifically, when there is lighting as shown in (a) of FIG. 7, a plurality of device identifiers (DIDs) can be better seen compared to when there is no lighting as shown in (b) of FIG. 7.

Figure 8 is a graph showing the current according to the voltage between the gate and source of the fourth transistor for each brightness of lighting.

In FIG. 8, the gate-source voltage of the fourth transistor T4 is shown on the X-axis, and the current Isd flowing from the first electrode to the second electrode of the fourth transistor T4 is shown on the Y-axis.

Referring to FIG. 8, the off current of the fourth transistor T4 increases as the luminance of the lighting increases. That is, the light leakage current of the fourth transistor T4 is proportional to the brightness of the lighting. Therefore, due to an increase in the light leakage current of the fourth transistor T4, a plurality of device identifiers (DIDs) may be identified as shown in (a) of FIG. 7. Therefore, there is a need to reduce the light leakage current of the fourth transistor T4.

Likewise, when the optical leakage current of the first transistor T1 and the third transistor T3 located in the current path in the test mode increases, a plurality of device identifiers (DIDs) are identified as shown in (a) of FIG. 7. This may happen. Therefore, it is necessary to reduce the light leakage current of not only the fourth transistor T4 but also the first transistor T1 and the third transistor T3.

9 is an equivalent circuit diagram showing a first sub-pixel according to another embodiment.

9 , the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4 include a lower gate electrode, and the seventh sub-transistor T111 of the eleventh transistor T11 includes a lower gate electrode. It is different from the embodiment of FIG. 5 in that the eighth sub-transistor T112 includes a lower gate electrode. In FIG. 9 , the description will focus on differences from the embodiment of FIG. 5 .

Referring to FIG. 9 , the lower gate electrode of the third sub-transistor T41 of the fourth transistor T4 and the lower gate electrode of the fourth sub-transistor T42 may be electrically connected to each other. For example, the lower gate electrode of the third sub-transistor T41 of the fourth transistor T4 and the lower gate electrode of the fourth sub-transistor T42 may be connected to the kth scan write line GWLk. In this case, the lower gate electrode of the third sub-transistor T41 of the fourth transistor T4 and the lower gate electrode of the fourth sub-transistor T42 are connected to the gate of the third sub-transistor T41 of the fourth transistor T4. It may be connected to the electrode (or upper gate electrode) and the gate electrode (or upper gate electrode) of the fourth sub-transistor T42. Therefore, the lower gate electrode of the third sub-transistor T41 of the fourth transistor T4 and the lower gate electrode of the fourth sub-transistor T42 are the gate electrodes of the third sub-transistor T41 of the fourth transistor T4. (or upper gate electrode) and may have the same potential as the gate electrode (or upper gate electrode) of the fourth sub-transistor T42. That is, the voltage of the lower gate electrode and the gate electrode (or upper gate electrode) of the third sub-transistor T41 are synchronized, and the voltage of the lower gate electrode and the gate electrode (or upper gate electrode) of the fourth sub-transistor T42 are synchronized. The voltage of the electrodes can be synchronized.

The lower gate electrode of the seventh sub-transistor T111 of the eleventh transistor T11 and the lower gate electrode of the eighth sub-transistor T112 may be electrically connected to each other. For example, the lower gate electrode of the seventh sub-transistor T111 of the eleventh transistor T11 and the lower gate electrode of the eighth sub-transistor T112 may be connected to the kth scan write line GWLk. In this case, the lower gate electrode of the seventh sub-transistor T111 of the 11th transistor T11 and the lower gate electrode of the 8th sub-transistor T112 are the gates of the 7th sub-transistor T111 of the 11th transistor T11. It may be connected to the electrode (or upper gate electrode) and the gate electrode (or upper gate electrode) of the eighth sub-transistor T112. Therefore, the lower gate electrode of the seventh sub-transistor T111 of the 11th transistor T11 and the lower gate electrode of the 8th sub-transistor T112 are the gate electrodes of the 7th sub-transistor T111 of the 11th transistor T11. (or upper gate electrode) and may have the same potential as the gate electrode (or upper gate electrode) of the eighth sub-transistor T112. That is, the voltage of the lower gate electrode and the gate electrode (or upper gate electrode) of the seventh sub-transistor T111 are synchronized, and the voltage of the lower gate electrode and the gate electrode (or upper gate electrode) of the eighth sub-transistor T112 are synchronized. The voltage of the electrodes can be synchronized.

Figure 10 is a graph showing the threshold voltage of the fourth transistor depending on the presence or absence of a lower gate electrode according to another embodiment. FIG. 11 is a graph showing the driving voltage range of the fourth transistor T4 depending on the presence or absence of a lower gate electrode according to another embodiment.

10 and 11, the presence or absence of a lower gate electrode is indicated on the X-axis. In FIG. 10, the Y-axis shows the threshold voltage of the fourth transistor T4, and in FIG. 11, the Y-axis shows the driving voltage range of the fourth transistor T4.

10 and 11, when the lower gate electrode of the fourth transistor T4 is electrically connected to the upper gate electrode (GATE-SYNC), the threshold voltage (Vth) of the fourth transistor (T4) is the fourth transistor ( When T4) does not include a lower gate electrode (NORAML), the threshold voltage (Vth) of the fourth transistor (T4) may be shifted more positively. In addition, when the lower gate electrode of the fourth transistor (T4) is electrically connected to the upper gate electrode (GATE-SYNC), the driving voltage range (DR range) of the fourth transistor (T4) is When no electrode is included (NORMAL), it may be lower than the driving voltage range (DR range) of the fourth transistor (T4). However, when the lower gate electrode of the fourth transistor (T4) is electrically connected to the upper gate electrode (GATE-SYNC), the width of the driving voltage range (DR range) of the fourth transistor (T4) is When the lower gate electrode is not included, the width of the driving voltage range (DR range) of the fourth transistor T4 may be similar.

10 and 11, when the lower gate electrode of the fourth transistor T4 is electrically connected to the upper gate electrode (GATE-SYNC), the lower gate electrode of the third sub-transistor T41 of the fourth transistor T4 is electrically connected to the upper gate electrode. It is connected to the gate electrode (or upper gate electrode) of the third sub-transistor T41, and the lower gate electrode of the fourth sub-transistor T42 is electrically connected to the gate electrode (or upper gate electrode) of the fourth sub-transistor T42. Indicates the case where it is connected.

FIG. 12 is a layout diagram showing a fourth transistor of a first sub-pixel according to another embodiment.

Referring to FIG. 12, the third sub-transistor (T41) of the fourth transistor (T4) includes a third sub-channel (CH41), a third sub-gate electrode (G41), a fourth lower gate electrode (BML4), and a third sub-channel (CH41). It includes a source electrode (S41) and a third sub-drain electrode (D41). The third sub-channel CH41 may overlap the third sub-gate electrode G41 and the fourth lower gate electrode BML4 in the third direction DR3. The third sub-source electrode S41 may be placed on one side of the third sub-channel CH41, and the third sub-drain electrode D31 may be placed on the other side of the third sub-channel CH41.

The fourth sub-transistor T42 of the fourth transistor T4 includes a fourth sub-channel CH42, a fourth sub-gate electrode G42, a fourth lower gate electrode BML4, a fourth sub-source electrode S42, and a fourth sub-drain electrode (D42). The fourth sub-channel CH42 may overlap the fourth sub-gate electrode G42 and the fourth lower gate electrode BML4 in the third direction DR3. The fourth sub-source electrode S42 may be disposed on one side of the fourth sub-channel CH42, and the fourth sub-drain electrode D42 may be disposed on the other side of the fourth sub-channel CH42. The fourth sub-source electrode (S42) may be connected to the third sub-drain electrode (D32). The fourth sub-drain electrode D42 may be connected to the first source connection electrode DCE1 through the first source contact hole DCT1.

The third sub-gate electrode G41 and the fourth sub-gate electrode G42 may be formed integrally with the first gate connection electrode GCE1. The first gate connection electrode (GCE1) may be connected to the kth scan write line (GWLk) through the first gate contact hole (GCT1). The first gate connection electrode (GCE1) may be connected to the fourth lower gate electrode (BML4) through the first lower contact hole (BCT1).

The fourth lower gate electrode (BML4) is connected to the third sub-channel (CH41) of the third sub-transistor (T41), the third sub-source electrode (S41), the third sub-drain electrode (D41), and the fourth sub-transistor ( It may overlap the fourth sub-channel (CH42), the fourth sub-source electrode (S42), and the fourth sub-drain electrode (D42) of T42). Light incident from the outside is blocked by the fourth lower gate electrode (BML4), and the third sub-channel (CH41) of the third sub-transistor (T41) and the fourth sub-channel (CH42) of the fourth sub-transistor (T42) You may not be hired. Therefore, the light leakage current of the third sub-transistor T41 and the light leakage current of the fourth sub-transistor T42 can be reduced, thereby preventing multiple device identifiers (DIDs) from being recognized in the inspection mode.

FIG. 13 is a layout diagram showing an 11th transistor of a first sub-pixel according to another embodiment.

Referring to FIG. 13, the 7th sub-transistor (T111) of the 11th transistor (T11) includes the 7th sub-channel (CH111), the 7th sub-gate electrode (G111), the 11th lower gate electrode (BML11), and the 7th sub-channel (CH111). It includes a source electrode (S111) and a seventh sub-drain electrode (D111). The seventh sub-channel CH111 may overlap the seventh sub-gate electrode G111 and the eleventh lower gate electrode BML11 in the third direction DR3. The seventh sub-gate electrode G111 may be formed integrally with the first gate connection electrode GCE1. The seventh sub-source electrode S111 may be disposed on one side of the seventh sub-channel CH111, and the seventh sub-drain electrode D111 may be disposed on the other side of the seventh sub-channel CH111.

The eighth sub-transistor (T112) of the 11th transistor (T11) includes an 8th sub-channel (CH112), an 8th sub-gate electrode (G112), an 11th lower gate electrode (BML11), an 8th sub-source electrode (S112), and an eighth sub-drain electrode (D112). The eighth sub-channel CH112 may overlap the eighth sub-gate electrode G112 and the eleventh lower gate electrode BML11 in the third direction DR3. The eighth sub-gate electrode G112 may be formed integrally with the first gate connection electrode GCE1. The eighth sub-source electrode S112 may be disposed on one side of the eighth sub-channel CH112, and the eighth sub-drain electrode D112 may be disposed on the other side of the eighth sub-channel CH112. The eighth sub-source electrode (S112) is connected to the seventh sub-drain electrode (D111), and the eighth sub-drain electrode (D112) is connected to the second source connection electrode (DCE2) through the second source contact hole (DCT2). You can.

The seventh sub-gate electrode G111 and the eighth sub-gate electrode G112 may be formed integrally with the first gate connection electrode GCE1. The first gate connection electrode (GCE1) may be connected to the kth scan write line (GWLk) through the second gate contact hole (GCT2). The first gate connection electrode (GCE1) may be connected to the 11th lower gate electrode (BML11) through the second lower contact hole (BCT2).

The 11th lower gate electrode (BML11) is connected to the 7th sub-channel (CH111) of the 7th sub-transistor (T111), the 7th sub-source electrode (S111), the 7th sub-drain electrode (D111), and the 8th sub-transistor ( It may overlap the eighth sub-channel (CH112), the eighth sub-source electrode (S112), and the eighth sub-drain electrode (D112) of (T112). Light incident from the outside is blocked by the 11th lower gate electrode (BML11), and the 7th sub-channel (CH111) of the 7th sub-transistor (T111) and the 8th sub-channel (CH112) of the 8th sub-transistor (T112) You may not be hired. Therefore, the light leakage current of the seventh sub-transistor T111 and the light leakage current of the eighth sub-transistor T112 can be reduced, thereby preventing multiple device identifiers (DIDs) from being recognized in the inspection mode.

Figure 14 is a layout diagram showing the 19th transistor of the first sub-pixel according to another embodiment.

Referring to FIG. 14, the 19th transistor T19 includes a 19th channel (CH19), a 19th gate electrode (G19), a 19th source electrode (S19), and a 19th drain electrode (D19). The 19th channel CH19 may overlap the 19th gate electrode G19 in the third direction DR3. The 19th source electrode S19 may be disposed on one side of the 19th channel CH19, and the 19th drain electrode D19 may be disposed on the other side of the 19th channel CH19. The 19th source electrode S19 may be connected to the third source connection electrode DCE3 through the third source contact hole DCT3. The 19th drain electrode D19 may be connected to the third power line VSL through the fourth source contact hole DCT24.

The 19th gate electrode G19 may be formed integrally with the third gate connection electrode GCE3. The third gate connection electrode (GCE3) may be connected to the test signal line (TSTL) through the third gate contact hole (GCT3).

The first anode connection electrode ANDE1 may be connected to the third source connection electrode DCE3 through the first anode contact hole CCT1.

The light blocking layer (BML19) may be electrically floating. The light blocking layer (BML19) may not be electrically connected to other electrodes or other wiring. The light blocking layer (BML19) may overlap the 19th source electrode (S19). The light blocking layer (BML19) may be a structure to block light from the light emitting device (EL) from being reflected by the back metal layer and being incident on a channel of a transistor.

FIG. 15 is a cross-sectional view showing an example of a display panel cut along line A-A' of FIG. 13 . FIG. 16 is a cross-sectional view showing an example of a display panel cut along line B-B' of FIG. 14. FIG. 17 is a cross-sectional view showing an example of a display panel cut along line C-C' of FIG. 15.

15 to 17, the substrate SUB may be made of an insulating material such as glass or polymer resin. For example, when the substrate (SUB) is made of polymer resin, it may include polyimide. The substrate SUB may be a flexible substrate capable of bending, folding, rolling, etc.

On the substrate SUB, a light blocking metal layer such as the fourth lower gate electrode BML4 of the fourth transistor T4, the eleventh lower gate electrode BML11 of the eleventh transistor T11, and the light blocking layer BML19 will be disposed. You can. The light-shielding metal layer is made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. It can be formed as a single layer or multiple layers.

A buffer film (BF) may be disposed on the light-shielding metal layer. The buffer film BF may be composed of a plurality of inorganic films stacked alternately. For example, the buffer film BF may be formed as a multilayer in which one or more inorganic layers of a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

An active layer may be disposed on the buffer film (BF). The active layer includes first to 19th channels (CH1 to CH19), first to 19th source electrodes (S1 to S19), and first to 19th drains of the first to 19th transistors (T1 to T19). It includes electrodes (D1 to D19). The active layer may include polycrystalline silicon, single crystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or oxide semiconductor. The first to 19th source electrodes (S1 to S19) and the first to 19th drain electrodes (D1 to D19) may be conductive regions in which a silicon semiconductor or an oxide semiconductor is doped with ions or impurities.

15 to 17, the active layer includes the third sub-channel (CH41), the third sub-source electrode (S41), and the third sub-drain electrode (D41) of the third sub-transistor (T41) of the fourth transistor (T4). ), the fourth sub-channel (CH42) of the fourth sub-transistor (T42) of the fourth transistor (T4), the fourth sub-source electrode (S42), and the fourth sub-drain electrode (D42), the eleventh transistor (T11) The 7th sub-channel (CH111), the 7th sub-source electrode (S111), and the 7th sub-drain electrode (D111) of the 7th sub-transistor (T111), and the 8th sub-transistor (T112) of the 11th transistor (T11) the 8th sub-channel (CH112), the 8th sub-source electrode (S112), and the 8th sub-drain electrode (D112), and the 19th channel (CH19) and the 19th source electrode (S19) of the 19th transistor (T19) , and only the 19th drain electrode (D19) is exemplified.

A gate insulating layer 130 may be disposed on the active layer. The gate insulating layer 130 may be formed of an inorganic layer, for example, a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

A first gate metal layer may be disposed on the gate insulating film 130. The first gate metal layer includes first to nineteenth gate electrodes (G1 to G19) of the first to nineteenth transistors (T1 to T19), and first to third gate connection electrodes (GCE1 to GCE3). . The first gate metal layer is made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It can be formed as a single layer or multiple layers made of alloy.

15 to 17 , the first gate metal layer includes the third sub-gate electrode G41 of the third sub-transistor T41 of the fourth transistor T4, and the fourth sub-transistor T42 of the fourth transistor T4. The fourth sub-gate electrode (G42) of the 11th transistor (T11), the 7th sub-gate electrode (G111) of the 7th sub-transistor (T111) of Only the 8 sub-gate electrode (G112) and the 19th gate electrode (G19) of the 19th transistor (T19) are illustrated.

The third sub-channel (CH41) of the third sub-transistor (T41) overlaps the third sub-gate electrode (G41) in the third direction (DR3), but the third sub-source electrode (S41) and the third sub-drain electrode ( D41) does not overlap. The fourth sub-channel (CH42) of the fourth sub-transistor (T42) overlaps the fourth sub-gate electrode (G42) in the third direction (DR3), but the fourth sub-source electrode (S42) and the fourth sub-drain electrode ( D42) does not overlap. The seventh sub-channel (CH111) of the seventh sub-transistor (T111) overlaps the seventh sub-gate electrode (G111) in the third direction (DR3), but the seventh sub-source electrode (S111) and the seventh sub-drain electrode ( D111) does not overlap. The eighth sub-channel (CH112) of the eighth sub-transistor (T112) overlaps the eighth sub-gate electrode (G112) in the third direction (DR3), but the eighth sub-source electrode (S112) and the eighth sub-drain electrode ( D112) does not overlap. The 19th channel (CH19) of the 19th transistor (T19) overlaps the 19th gate electrode (G19) in the third direction (DR3), but does not overlap the 19th source electrode (S19) and the 19th drain electrode (D19). No.

A first interlayer insulating film 141 may be disposed on the first gate metal layer. The first interlayer insulating layer 141 may be formed of an inorganic layer, for example, a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

A second gate metal layer may be disposed on the first interlayer insulating film 141. The second gate metal layer is made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It can be formed as a single layer or multiple layers made of alloy.

A second interlayer insulating film 142 may be disposed on the second gate metal layer. The second interlayer insulating layer 142 may be formed of an inorganic layer, for example, a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

A first source metal layer may be disposed on the second interlayer insulating film 142. The first source metal layer may include a kth scan write line (GWLk), a test signal line (TSTL), a third power line (VSL), and first to third source connection electrodes (DCE1 to DCE3). The first source metal layer is any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It can be formed as a single layer or multiple layers made of alloy.

The k-th scan write line (GWLk) connects the first gate through the first gate contact hole (GCT1) and the second gate contact hole (GCT2) penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. It can be connected to the electrode (GCE1). The test signal line TSTL may be connected to the 19th gate electrode G19 through the third gate contact hole GCT3 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. The third power line (VSL) is connected to the 19th drain electrode (D19) through the fourth source contact hole (DCT4) penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. can be connected to

The first data connection electrode (DCE1) is connected to the fourth sub-drain electrode ( D42). The second data connection electrode (DCE2) is connected to the eighth sub-drain electrode ( D112). The third data connection electrode (DCE3) is connected to the 19th source electrode (S19) through the third data contact hole (DCT3) penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. ) can be connected to.

A first planarization film 160 may be disposed on the first source metal layer. The first planarization film 160 is formed of an organic film such as acryl resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. It can be.

A first inorganic insulating layer 161 may be disposed on the first planarization layer 160. The first inorganic insulating layer 161 may be formed of an inorganic layer, for example, a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

A second source metal layer may be disposed on the first inorganic insulating layer 161. The second source metal layer may include a first vertical power line (VVDL) and a first anode connection electrode (ANDE1). The second source metal layer is any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It can be formed as a single layer or multiple layers made of alloy.

The first anode connection electrode ANDE1 may be connected to the third source connection electrode DCE3 through the first anode contact hole ACT1 penetrating the first planarization film 160 and the first inorganic insulating film 161.

A second planarization film 180 may be disposed on the second source metal layer. The second planarization film 180 is formed of an organic film such as acryl resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. It can be.

A second inorganic insulating layer 181 may be disposed on the second planarization layer 180. The second inorganic insulating layer 181 may be formed of an inorganic layer, for example, a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

A third source metal layer may be disposed on the second inorganic insulating layer 181. The third source metal layer is any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It can be formed as a single layer or multiple layers made of alloy.

A third planarization film 190 may be disposed on the third source metal layer. The third planarization film 190 is formed of an organic film such as acryl resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. It can be.

A third inorganic insulating layer 191 may be disposed on the third planarization layer 190. The third inorganic insulating layer 191 may be formed of an inorganic layer, for example, a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

FIG. 18 is a cross-sectional view showing the Z region of FIG. 17 in detail.

Referring to FIG. 18 , as the thickness of the fourth lower gate electrode BML4 increases, the step of the buffer film BF at one end of the fourth lower gate electrode BML4 may increase. Since the step coverage of the fourth sub-source electrode S41 is poor, as the step of the buffer layer BF increases, the fourth lower gate electrode BML4 is more likely to be disconnected in the step area of the buffer layer BF. It is highly likely. Step coverage refers to the ratio of the extent to which a thin film is applied to a sloped area compared to the extent to which a thin film is applied to a flat area.

Figure 19 is a graph showing the driving current according to the gate voltage of the fourth transistor for each thickness of the fourth lower gate electrode.

In FIG. 19, the gate voltage of the fourth transistor T4 is shown on the X-axis, and the current (Isd) of the fourth transistor T4 is shown on the Y-axis.

Referring to FIG. 19, when the thickness of the fourth lower gate electrode (BML4) is approximately 500 Å or more, the off current of the fourth transistor (T4) is lower than that of the fourth transistor (T4) when there is no lighting without the fourth lower gate electrode (BML). It may be similar to the off current of . That is, when the thickness of the fourth lower gate electrode BML4 is approximately 500 Å or more, it can be seen that the light leakage current is greatly reduced.

Referring to FIG. 19, considering light leakage current, the thickness of the fourth lower gate electrode BML4 is preferably approximately 500 Å or more. However, referring to FIG. 18 , the step coverage of the fourth sub-source electrode S41 is disadvantageous as the thickness of the fourth lower gate electrode BML4 increases. Therefore, considering FIGS. 18 and 19, the thickness of the fourth lower gate electrode BML4 is approximately 500 Å and is preferably 800 Å or less.

Figure 20 is an equivalent circuit diagram showing a first sub-pixel according to another embodiment.

20 , the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3 include a lower gate electrode, and the fifth sub-transistor T101 of the tenth transistor T10 includes a lower gate electrode. It is different from the embodiment of FIG. 9 in that the sixth sub-transistor T102 includes a lower gate electrode. In FIG. 20, the description will focus on differences from the embodiment of FIG. 9.

Referring to FIG. 20, the lower gate electrode of the first sub-transistor T31 of the third transistor T3 and the lower gate electrode of the second sub-transistor T32 may be electrically connected to each other. For example, the lower gate electrode of the first sub-transistor T31 of the third transistor T3 and the lower gate electrode of the second sub-transistor T32 may be connected to the kth scan initialization line GILk. In this case, the lower gate electrode of the first sub-transistor T31 of the third transistor T3 and the lower gate electrode of the second sub-transistor T32 are connected to the gate of the first sub-transistor T31 of the third transistor T3. It may be connected to the electrode (or upper gate electrode) and the gate electrode (or upper gate electrode) of the second sub-transistor T32. Therefore, the lower gate electrode of the first sub-transistor T31 of the third transistor T3 and the lower gate electrode of the second sub-transistor T32 are the gate electrodes of the first sub-transistor T31 of the third transistor T3. (or upper gate electrode) and may have the same potential as the gate electrode (or upper gate electrode) of the second sub-transistor T32. That is, the voltage of the lower gate electrode and the gate electrode (or upper gate electrode) of the first sub-transistor T31 are synchronized, and the voltage of the lower gate electrode and the gate electrode (or upper gate electrode) of the second sub-transistor T32 are synchronized. The voltage of the electrodes can be synchronized.

The lower gate electrode of the fifth sub-transistor T101 of the tenth transistor T10 and the lower gate electrode of the sixth sub-transistor T102 may be electrically connected to each other. For example, the lower gate electrode of the fifth sub-transistor T101 of the tenth transistor T10 and the lower gate electrode of the sixth sub-transistor T102 may be connected to the kth scan initialization line GILk. In this case, the lower gate electrode of the fifth sub-transistor T101 of the tenth transistor T10 and the lower gate electrode of the sixth sub-transistor T102 are the gates of the fifth sub-transistor T101 of the tenth transistor T10. It may be connected to the electrode (or upper gate electrode) and the gate electrode (or upper gate electrode) of the sixth sub-transistor T102. Therefore, the lower gate electrode of the fifth sub-transistor T101 of the tenth transistor T10 and the lower gate electrode of the sixth sub-transistor T102 are the gate electrodes of the fifth sub-transistor T101 of the tenth transistor T10. (or upper gate electrode) and may have the same potential as the gate electrode (or upper gate electrode) of the sixth sub-transistor T102. That is, the voltage of the lower gate electrode and the gate electrode (or upper gate electrode) of the fifth sub-transistor T101 are synchronized, and the voltage of the lower gate electrode and the gate electrode (or upper gate electrode) of the sixth sub-transistor T102 are synchronized. The voltage of the electrodes can be synchronized.

FIG. 21 is a layout diagram showing a third transistor and a tenth transistor of a first sub-pixel according to another embodiment.

Referring to FIG. 21, the first sub-transistor (T31) of the third transistor (T3) includes a first sub-channel (CH31), a first sub-gate electrode (G31), a third lower gate electrode (BML3), and a first sub-channel (CH31). It includes a source electrode (S31) and a first sub-drain electrode (D31). The first sub-channel CH31 may overlap the first sub-gate electrode G31 and the third lower gate electrode BML3 in the third direction DR3. The first sub-source electrode S31 may be disposed on one side of the first sub-channel CH31, and the first sub-drain electrode D31 may be disposed on the other side of the first sub-channel CH31.

The second sub-transistor T32 of the third transistor T3 includes a second sub-channel CH32, a second sub-gate electrode G32, a third lower gate electrode BML3, a second sub-source electrode S32, and a second sub-drain electrode (D32). The second sub-channel CH32 may overlap the second sub-gate electrode G32 and the third lower gate electrode BML3 in the third direction DR3. The second sub-source electrode S32 may be disposed on one side of the second sub-channel CH32, and the second sub-drain electrode D32 may be disposed on the other side of the second sub-channel CH32. The second sub-source electrode S32 may be connected to the first sub-drain electrode D31, and the second sub-drain electrode D32 may be connected to the initialization voltage line VIL through the fifth source contact hole DCT5. .

The fifth sub-transistor (T101) of the tenth transistor (T10) includes a fifth sub-channel (CH101), a fifth sub-gate electrode (G101), a tenth lower gate electrode (BML10), a fifth sub-source electrode (S101), and a fifth sub-drain electrode (D101). The fifth sub-channel CH101 may overlap the fifth sub-gate electrode G101 and the tenth lower gate electrode BML10 in the third direction DR3. The fifth sub-source electrode S101 may be disposed on one side of the fifth sub-channel CH101, and the fifth sub-drain electrode D101 may be disposed on the other side of the fifth sub-channel CH101.

The sixth sub-transistor (T102) of the tenth transistor (T10) includes a sixth sub-channel (CH102), a sixth sub-gate electrode (G102), a tenth lower gate electrode (BML10), a sixth sub-source electrode (S102), and a sixth sub-drain electrode (D102). The sixth sub-channel CH102 may overlap the sixth sub-gate electrode G102 and the tenth lower gate electrode BML10 in the third direction DR3. The sixth sub-source electrode S102 may be disposed on one side of the sixth sub-channel CH102, and the sixth sub-drain electrode D102 may be disposed on the other side of the sixth sub-channel CH102. The sixth sub-source electrode (S102) is connected to the fifth sub-drain electrode (D101), and the sixth sub-drain electrode (D102) can be connected to the initialization voltage line (VIL) through the fifth source contact hole (DCT5). .

The first sub-gate electrode G31, the second sub-gate electrode G32, the fifth sub-gate electrode G101, and the sixth sub-gate electrode G102 may be formed integrally with the second gate connection electrode GCE2. You can. The second gate connection electrode GCE2 may be connected to the kth scan initialization line GILk through the fourth gate contact hole GCT4. The second gate connection electrode (GCE2) may be connected to the third lower gate electrode (BML3) through the third lower contact hole (BCT3). The second gate connection electrode GCE2 may be connected to the tenth lower gate electrode BML10 through the fourth lower contact hole BCT4.

The third lower gate electrode (BML3) is connected to the first sub-channel (CH31) of the first sub-transistor (T31), the first sub-source electrode (S31), the first sub-drain electrode (D31), and the second sub-transistor ( It may overlap the second sub-channel (CH32), the second sub-source electrode (S32), and the second sub-drain electrode (D32) of T32). Light incident from the outside is blocked by the third lower gate electrode (BML3), and the first sub-channel (CH31) of the first sub-transistor (T31) and the second sub-channel (CH32) of the second sub-transistor (T32) You may not be hired. Therefore, the light leakage current of the first sub-transistor T31 and the light leakage current of the second sub-transistor T32 can be reduced, thereby preventing multiple device identifiers (DIDs) from being recognized in the inspection mode.

The 11th lower gate electrode (BML11) is connected to the fifth sub-channel (CH101) of the fifth sub-transistor (T101), the fifth sub-source electrode (S101), the fifth sub-drain electrode (D101), and the sixth sub-transistor ( It may overlap the sixth sub-channel (CH102), the sixth sub-source electrode (S102), and the sixth sub-drain electrode (D102) of T102). Light incident from the outside is blocked by the 11th lower gate electrode (BML11), and the fifth sub-channel (CH101) of the fifth sub-transistor (T101) and the sixth sub-channel (CH102) of the sixth sub-transistor (T102) You may not be hired. Therefore, the light leakage current of the fifth sub-transistor T101 and the light leakage current of the sixth sub-transistor T102 can be reduced, thereby preventing multiple device identifiers (DIDs) from being recognized in the inspection mode.

FIG. 22 is a cross-sectional view showing an example of a display panel cut along line DD′ of FIG. 21 . FIG. 23 is a cross-sectional view showing an example of a display panel taken along line E-E' of FIG. 21.

22 and 23, the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3, and the fifth sub-transistor T101 and the sixth sub-transistor T10 of the tenth transistor T10. The description will focus on the sub-transistor T102, and descriptions that overlap with the embodiments of FIGS. 15 to 17 will be omitted.

Referring to FIGS. 22 and 23 , the light-shielding metal layer may further include a third lower gate electrode (BML3) and a tenth lower gate electrode (BML10).

The first gate metal layer may further include a second gate connection electrode (GCE2). The second gate connection electrode GCE2 may be connected to the third lower gate electrode BML3 through the third lower contact hole BCT3 penetrating the buffer film BF and the gate insulating film 130. The second gate connection electrode GCE2 may be connected to the tenth lower gate electrode BML10 through the fourth lower contact hole BCT4 penetrating the buffer film BF and the gate insulating film 130.

The first sub-channel (CH31) of the first sub-transistor (T31) overlaps the first sub-gate electrode (G31) in the third direction (DR3), but the first sub-source electrode (S31) and the first sub-drain electrode ( D31) does not overlap. The second sub-channel (CH32) of the second sub-transistor (T32) overlaps the second sub-gate electrode (G32) in the third direction (DR3), but the second sub-source electrode (S32) and the second sub-drain electrode ( D32) does not overlap. The fifth sub-channel (CH101) of the fifth sub-transistor (T101) overlaps the fifth sub-gate electrode (G101) in the third direction (DR3), but the fifth sub-source electrode (S101) and the fifth sub-drain electrode ( D101) does not overlap. The sixth sub-channel (CH102) of the sixth sub-transistor (T102) overlaps the sixth sub-gate electrode (G102) in the third direction (DR3), but the sixth sub-source electrode (S102) and the sixth sub-drain electrode ( D102) does not overlap.

Figure 24 is an equivalent circuit diagram showing a first sub-pixel according to another embodiment.

The embodiment of FIG. 24 differs from the embodiment of FIG. 20 in that the first transistor T1 includes a lower gate electrode and the eighth transistor T8 includes a lower gate electrode. In the embodiment of FIG. 24, the description will focus on differences from the embodiment of FIG. 20.

Referring to FIG. 24, the lower gate electrode of the first transistor T1 may be connected to the gate electrode (or upper gate electrode) of the first transistor T1. Therefore, the lower gate electrode of the first transistor T1 may have the same potential as the gate electrode (or upper gate electrode) of the first transistor T1. That is, the voltage of the lower gate electrode and the voltage of the gate electrode (or upper gate electrode) of the first transistor T1 may be synchronized.

The lower gate electrode of the eighth transistor T8 may be connected to the gate electrode (or upper gate electrode) of the eighth transistor T8. Therefore, the lower gate electrode of the eighth transistor T8 may have the same potential as the gate electrode (or upper gate electrode) of the eighth transistor T8. That is, the voltage of the lower gate electrode and the voltage of the gate electrode (or upper gate electrode) of the eighth transistor T8 may be synchronized.

Figure 25 is a layout diagram showing the first transistor of the first sub-pixel according to another embodiment.

Referring to FIG. 25, the first transistor T1 includes a first channel CH1, a first gate electrode G1, a first lower gate electrode BML1, a first source electrode S1, and a first drain electrode. Includes (D1). The first channel CH1 may extend in the first direction DR1. The first channel CH1 may overlap the first gate electrode G1 and the first lower gate electrode BML1 in the third direction DR3. The first gate electrode G1 may be connected to the first source connection electrode DCE1 through the sixth source contact hole DCT6. The first source electrode S1 may be disposed on one side of the first channel CH1, and the first drain electrode D1 may be disposed on the other side of the first channel CH1.

The first capacitor electrode (CE1) may be formed integrally with the first gate electrode (G1). The first capacitor electrode CE1 may overlap the second capacitor electrode CE2 in the third direction DR3. The overlapping area between the first capacitor electrode CE1 and the second capacitor electrode CE2 in the third direction DR3 may be defined as the first capacitor C1. The first capacitor electrode CE1 may be connected to the first lower gate electrode BML1 through the fifth gate contact hole GCT5.

The first lower gate electrode BML1 may overlap the first channel CH1, the first source electrode S1, and the first drain electrode D1 of the first transistor T1. Light incident from the outside is blocked by the first lower gate electrode BML1 and may not enter the first channel CH1 of the first transistor T1. Therefore, the light leakage current of the first transistor T1 can be reduced, thereby preventing multiple device identifiers (DIDs) from being recognized in the inspection mode.

Figure 26 is a layout diagram showing the eighth transistor of the first sub-pixel according to another embodiment.

The eighth transistor T8 includes an eighth channel CH8, an eighth gate electrode G8, an eighth lower gate electrode BML8, an eighth source electrode S8, and an eighth drain electrode D8. . The eighth channel CH8 may overlap the eighth gate electrode G8 and the eighth lower gate electrode BML8 in the third direction DR3. The eighth gate electrode G8 may be connected to the second source connection electrode DCE2 through the seventh source contact hole DCT7. The eighth source electrode S8 may be disposed on one side of the eighth channel CH8, and the eighth drain electrode D8 may be disposed on the other side of the eighth channel CH8.

The third capacitor electrode CE3 may be formed integrally with the eighth gate electrode G8. The third capacitor electrode CE3 may overlap the fourth capacitor electrode CE4 in the third direction DR3. The overlapping area of the third capacitor electrode CE3 and the fourth capacitor electrode CE4 in the third direction DR3 may be defined as the second capacitor C2. The third capacitor electrode CE3 may be connected to the eighth lower gate electrode BML8 through the sixth gate contact hole GCT6.

The first vertical power line (VVDL) of the second power line (VDL2) may be connected to the fourth source connection electrode (DCE4) through the first power contact hole (PCT1).

The eighth lower gate electrode BML8 may overlap the eighth channel CH8, the eighth source electrode S8, and the eighth drain electrode D8 of the eighth transistor T8. Light incident from the outside is blocked by the eighth lower gate electrode BML8 and may not enter the eighth channel CH8 of the eighth transistor T8. Therefore, the light leakage current of the eighth transistor T8 can be reduced, thereby preventing multiple device identifiers (DIDs) from being recognized in the inspection mode.

FIG. 27 is a cross-sectional view showing an example of a display panel cut along line F-F' of FIG. 25. FIG. 28 is a cross-sectional view showing an example of a display panel cut along line G-G' of FIG. 25.

In the embodiments of FIGS. 27 and 28 , description will be focused on the first transistor T1 and the eighth transistor T8 , and descriptions overlapping with the embodiments of FIGS. 15 to 17 will be omitted.

Referring to FIGS. 27 and 28 , the light-shielding metal layer may further include a first lower gate electrode (BML1) and an eighth lower gate electrode (BML8).

The first gate metal layer may further include a first capacitor electrode (CE1) and a third capacitor electrode (CE3). The first capacitor electrode CE1 may be connected to the first lower gate electrode BML1 through the fifth lower contact hole BCT5 penetrating the buffer film BF and the gate insulating film 130. The third capacitor electrode CE3 may be connected to the eighth lower gate electrode BML8 through the sixth lower contact hole BCT6 penetrating the buffer film BF and the gate insulating film 130.

The second gate metal layer may include a second capacitor electrode (CE2) and a fourth capacitor electrode (CE4). The first capacitor electrode (CE1), the second capacitor electrode (CE2), and the first interlayer insulating film 141 interposed between the first capacitor electrode (CE1) and the second capacitor electrode (CE2) are connected to the first capacitor (C1). can be configured. The third capacitor electrode (CE3), the fourth capacitor electrode (CE4), and the first interlayer insulating film 141 interposed between the third capacitor electrode (CE3) and the fourth capacitor electrode (CE4) are connected to the second capacitor (C2). can be configured.

The first source connection electrode (DCE1) may be connected to the first gate electrode (GE1) through the sixth source contact hole (DCT6) penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. The second source connection electrode DCE2 may be connected to the eighth gate electrode GE8 through the seventh source contact hole DCT7 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142.

The first source metal layer may further include a fourth source connection electrode (DCE4), and the second source metal layer may further include a first vertical power line (VVDL). The first vertical power line (VVDL) may be connected to the fourth source connection electrode (DCE4) through the first power contact hole (PCT1) penetrating the first planarization film 160 and the first inorganic insulating film 161.

The first channel (CH1) of the first transistor (T1) overlaps the first gate electrode (G1) in the third direction (DR3), but does not overlap the first source electrode (S1) and the first drain electrode (D1). No. The eighth channel (CH8) of the eighth transistor (T8) overlaps the eighth gate electrode (G8) in the third direction (DR3), but does not overlap the eighth source electrode (S8) and the eighth drain electrode (D8). No.

Figure 29 is an equivalent circuit diagram showing a first sub-pixel according to another embodiment.

29 , the third sub-transistor T41 and the fourth sub-transistor T42 of the fourth transistor T4 include a lower gate electrode, and the seventh sub-transistor T111 of the eleventh transistor T11 includes a lower gate electrode. It is different from the embodiment of FIG. 5 in that the eighth sub-transistor T112 includes a lower gate electrode. In FIG. 29, the description will focus on differences from the embodiment of FIG. 5.

Referring to FIG. 29 , the lower gate electrode of the third sub-transistor T41 of the fourth transistor T4 and the lower gate electrode of the fourth sub-transistor T42 may be electrically connected to each other. For example, the lower gate electrode of the third sub-transistor T41 of the fourth transistor T4 and the lower gate electrode of the fourth sub-transistor T42 may be connected to the first electrode of the third sub-transistor T41. . The first electrode of the third sub-transistor T41 may be connected to the second electrode of the first transistor T1 and the first electrode of the sixth transistor T6.

The lower gate electrode of the third sub-transistor T41 of the fourth transistor T4 and the lower gate electrode of the fourth sub-transistor T42 may have the same potential as the first electrode of the third sub-transistor T41. That is, the voltage of the lower gate electrode of the third sub-transistor T41 of the fourth transistor T4 and the voltage of the lower gate electrode of the fourth sub-transistor T42 are the voltage of the first electrode of the third sub-transistor T41. can be synchronized with

The lower gate electrode of the seventh sub-transistor T111 of the eleventh transistor T11 and the lower gate electrode of the eighth sub-transistor T112 may be electrically connected to each other. For example, the lower gate electrode of the seventh sub-transistor T111 of the eleventh transistor T11 and the lower gate electrode of the eighth sub-transistor T112 may be connected to the first electrode of the seventh sub-transistor T111. . The first electrode of the seventh sub-transistor T111 may be connected to the second electrode of the eighth transistor T8 and the first electrode of the fifteenth transistor T15.

In this case, the lower gate electrode of the seventh sub-transistor T111 of the eleventh transistor T11 and the lower gate electrode of the eighth sub-transistor T112 have the same potential as the first electrode of the seventh sub-transistor T111. You can. That is, the voltage of the lower gate electrode of the seventh sub-transistor T111 and the voltage of the lower gate electrode of the eighth sub-transistor T112 may be synchronized with the voltage of the first electrode of the seventh sub-transistor T111.

Figure 30 is a graph showing the threshold voltage of the fourth transistor depending on the presence or absence of a lower gate electrode according to another embodiment. Figure 31 is a graph showing the driving voltage range of the fourth transistor depending on the presence or absence of a lower gate electrode according to another embodiment.

30 and 31, the X-axis indicates the presence or absence of a lower gate electrode. In FIG. 30, the Y-axis shows the threshold voltage of the fourth transistor T4, and in FIG. 11, the Y-axis shows the driving voltage range of the fourth transistor T4.

30 and 31, when the lower gate electrode of the fourth transistor T4 is electrically connected to the first electrode of the fourth transistor T4 (SOURCE-SYNC), the threshold voltage of the fourth transistor T4 ( Vth) may be negatively shifted from the threshold voltage (Vth) of the fourth transistor (T4) when the fourth transistor (T4) does not include a lower gate electrode (NORMAL). In addition, when the lower gate electrode of the fourth transistor T4 is electrically connected to the first electrode of the fourth transistor T4 (SOURCE-SYNC), the driving voltage range (DR range) of the fourth transistor T4 is 4 When the transistor T4 does not include a lower gate electrode (NORMAL), the driving voltage range (DR range) of the fourth transistor T4 may be higher. However, when the lower gate electrode of the fourth transistor T4 is electrically connected to the first electrode of the fourth transistor T4 (SOURCE-SYNC), the width of the driving voltage range (DR range) of the fourth transistor T4 is When the fourth transistor T4 does not include a lower gate electrode (NORMAL), the width of the driving voltage range (DR range) of the fourth transistor T4 may be similar.

10 and 11, when the lower gate electrode of the fourth transistor T4 is electrically connected to the first electrode of the fourth transistor T4 (SOURCE-SYNC), the third sub-transistor (SOURCE-SYNC) of the fourth transistor T4 This refers to a case where the lower gate electrode of the fourth sub-transistor (T41) and the lower gate electrode of the fourth sub-transistor (T42) are electrically connected to the first electrode of the third sub-transistor (T41).

Figure 32 is a layout diagram showing the fourth transistor of the first sub-pixel according to another embodiment.

The embodiment of FIG. 32 is different from the embodiment of FIG. 12 in that the third sub-source electrode S41 of the third sub-transistor T41 is connected to the fourth lower gate electrode BML4. In the embodiment of FIG. 32, descriptions overlapping with the embodiment of FIG. 12 will be omitted.

Referring to FIG. 32, the third sub-source electrode S41 of the third sub-transistor T41 of the fourth transistor T4 is connected to the fourth lower gate electrode BML4 through the first lower contact hole BCT1'. can be connected

The fourth lower gate electrode (BML4) is connected to the third sub-channel (CH41) of the third sub-transistor (T41), the third sub-source electrode (S41), the third sub-drain electrode (D41), and the fourth sub-transistor ( It may overlap the fourth sub-channel (CH42), the fourth sub-source electrode (S42), and the fourth sub-drain electrode (D42) of T42). Light incident from the outside is blocked by the fourth lower gate electrode (BML4), and the third sub-channel (CH41) of the third sub-transistor (T41) and the fourth sub-channel (CH42) of the fourth sub-transistor (T42) You may not be hired. Therefore, the light leakage current of the third sub-transistor T41 and the light leakage current of the fourth sub-transistor T42 can be reduced, thereby preventing multiple device identifiers (DIDs) from being recognized in the inspection mode.

Figure 33 is a layout diagram showing the 11th transistor of the first sub-pixel according to another embodiment.

The embodiment of FIG. 33 is different from the embodiment of FIG. 13 in that the seventh sub-source electrode S111 of the seventh sub-transistor T111 is connected to the 11th lower gate electrode BML11. In the embodiment of FIG. 33, descriptions overlapping with the embodiment of FIG. 13 will be omitted.

Referring to FIG. 33 , the seventh sub-source electrode S111 of the seventh sub-transistor T111 may be connected to the 11th lower gate electrode BML11 through the second lower contact hole BCT1'.

The 11th lower gate electrode (BML11) is connected to the 7th sub-channel (CH111) of the 7th sub-transistor (T111), the 7th sub-source electrode (S111), the 7th sub-drain electrode (D111), and the 8th sub-transistor ( It may overlap the eighth sub-channel (CH112), the eighth sub-source electrode (S112), and the eighth sub-drain electrode (D112) of (T112). Light incident from the outside is blocked by the 11th lower gate electrode (BML11), and the 7th sub-channel (CH111) of the 7th sub-transistor (T111) and the 8th sub-channel (CH112) of the 8th sub-transistor (T112) You may not be hired. Therefore, the light leakage current of the seventh sub-transistor T111 and the light leakage current of the eighth sub-transistor T112 can be reduced, thereby preventing multiple device identifiers (DIDs) from being recognized in the inspection mode.

FIG. 34 is a cross-sectional view showing the display panel cut along line H-H' of FIG. 32. FIG. 35 is a cross-sectional view showing the display panel cut along line II′ of FIG. 33 .

The embodiments of FIGS. 34 and 35 are different from the embodiments of FIGS. 15 to 17 in the first lower contact hole (BCT1') and the second lower contact hole (BCT2'). In FIGS. 34 and 35 , descriptions overlapping with the embodiments of FIGS. 15 to 17 are omitted.

34 and 35, the third sub-source electrode S41 of the third sub-transistor T41 is connected to the fourth lower gate electrode through the first lower contact hole BCT1' penetrating the buffer film BF. (BML4).

The seventh sub-source electrode S111 of the seventh sub-transistor T111 may be connected to the 11th lower gate electrode BML11 through the second lower contact hole BCT1' penetrating the buffer film BF.

Figure 36 is an equivalent circuit diagram showing a first sub-pixel according to another embodiment.

36 , the first sub-transistor T31 and the second sub-transistor T32 of the third transistor T3 include a lower gate electrode, and the fifth sub-transistor T101 of the tenth transistor T10 includes a lower gate electrode. It is different from the embodiment of FIG. 29 in that the sixth sub-transistor T102 includes a lower gate electrode. In FIG. 36, the description will focus on differences from the embodiment of FIG. 29.

Referring to FIG. 36, the lower gate electrode of the first sub-transistor T31 of the third transistor T3 and the lower gate electrode of the second sub-transistor T32 may be electrically connected to each other. For example, the lower gate electrode of the first sub-transistor T31 of the third transistor T3 and the lower gate electrode of the second sub-transistor T32 may be connected to the first electrode of the first sub-transistor T31. . The first electrode of the first sub-transistor T31 may be connected to the gate electrode of the first transistor T1 and the second electrode of the fourth sub-transistor T42 of the fourth transistor T4.

The lower gate electrode of the first sub-transistor T31 of the third transistor T3 and the lower gate electrode of the second sub-transistor T32 may have the same potential as the first electrode of the first sub-transistor T31. That is, the voltage of the lower gate electrode of the first sub-transistor T31 of the third transistor T3 and the voltage of the lower gate electrode of the second sub-transistor T32 are the voltage of the first electrode of the first sub-transistor T31. can be synchronized with

The lower gate electrode of the fifth sub-transistor T101 of the tenth transistor T10 and the lower gate electrode of the sixth sub-transistor T102 may be electrically connected to each other. For example, the lower gate electrode of the fifth sub-transistor T101 of the tenth transistor T10 and the lower gate electrode of the sixth sub-transistor T102 may be connected to the first electrode of the fifth sub-transistor T101. . The first electrode of the fifth sub-transistor T101 may be connected to the gate electrode of the eighth transistor T8 and the second electrode of the eighth sub-transistor T112 of the 11th transistor T11.

The lower gate electrode of the fifth sub-transistor T101 of the tenth transistor T10 and the lower gate electrode of the sixth sub-transistor T102 may have the same potential as the first electrode of the fifth sub-transistor T101. That is, the voltage of the lower gate electrode of the fifth sub-transistor (T101) of the tenth transistor (T10) and the voltage of the lower gate electrode of the sixth sub-transistor (T102) are the voltage of the first electrode of the fifth sub-transistor (T101). can be synchronized with

Figure 37 is a layout diagram showing the third transistor and the tenth transistor of the first sub-pixel according to another embodiment.

37 , the first sub-source electrode S31 of the first sub-transistor T31 is connected to the third lower gate electrode BML3, and the fifth sub-source electrode S51 of the fifth sub-transistor T101 is connected to the third lower gate electrode BML3. ) is different from the embodiment of FIG. 21 in that it is connected to the 11th lower gate electrode (BML11). In the embodiment of FIG. 37, descriptions overlapping with the embodiment of FIG. 21 will be omitted.

Referring to FIG. 37, the first sub-source electrode (S31) of the first sub-transistor (T31) of the third transistor (T3) is connected to the third lower gate electrode (BML3) through the third lower contact hole (BCT3'). can be connected The fifth sub-source electrode S51 of the fifth sub-transistor T101 of the tenth transistor T10 may be connected to the eleventh lower gate electrode BML11 through the fourth lower contact hole BCT4'.

The third lower gate electrode (BML3) is connected to the first sub-channel (CH31) of the first sub-transistor (T31), the first sub-source electrode (S31), the first sub-drain electrode (D31), and the second sub-transistor ( It may overlap the second sub-channel (CH32), the second sub-source electrode (S32), and the second sub-drain electrode (D32) of T32). Light incident from the outside is blocked by the third lower gate electrode (BML3), and the first sub-channel (CH31) of the first sub-transistor (T31) and the second sub-channel (CH32) of the second sub-transistor (T32) You may not be hired. Therefore, the light leakage current of the first sub-transistor T31 and the light leakage current of the second sub-transistor T32 can be reduced, thereby preventing multiple device identifiers (DIDs) from being recognized in the inspection mode.

The 11th lower gate electrode (BML11) is connected to the fifth sub-channel (CH101) of the fifth sub-transistor (T101), the fifth sub-source electrode (S101), the fifth sub-drain electrode (D101), and the sixth sub-transistor ( It may overlap the sixth sub-channel (CH102), the sixth sub-source electrode (S102), and the sixth sub-drain electrode (D102) of T102). Light incident from the outside is blocked by the 11th lower gate electrode (BML11), and the fifth sub-channel (CH101) of the fifth sub-transistor (T101) and the sixth sub-channel (CH102) of the sixth sub-transistor (T102) You may not be hired. Therefore, the light leakage current of the fifth sub-transistor T101 and the light leakage current of the sixth sub-transistor T102 can be reduced, thereby preventing multiple device identifiers (DIDs) from being recognized in the inspection mode.

FIG. 38 is a cross-sectional view showing an example of a display panel cut along line J-J' of FIG. 37. FIG. 39 is a cross-sectional view showing an example of a display panel cut along line K-K' of FIG. 37.

38 and 39, the first sub-source electrode S31 of the first sub-transistor T31 is connected to the third lower gate electrode BML3, and the fifth source electrode of the fifth sub-transistor T101 is connected to the third lower gate electrode BML3. It is different from the embodiment of FIGS. 22 and 23 in that (S101) is connected to the 11th lower gate electrode (BML11). In the embodiments of FIGS. 38 and 39, descriptions overlapping with the embodiments of FIGS. 22 and 23 will be omitted.

38 and 39, the first sub-source electrode (S31) of the first sub-transistor (T31) is connected to the third lower gate electrode through the third lower contact hole (BCT3') penetrating the buffer film (BF). (BML3).

The fifth sub-source electrode S101 of the fifth sub-transistor T101 may be connected to the tenth lower gate electrode BML10 through the fourth lower contact hole BCT3' penetrating the buffer film BF.

Figure 40 is an equivalent circuit diagram showing a first sub-pixel according to another embodiment.

The embodiment of FIG. 40 differs from the embodiment of FIG. 24 in that the first transistor T1 includes a lower gate electrode and the eighth transistor T8 includes a lower gate electrode. In the embodiment of FIG. 40, the description will focus on differences from the embodiment of FIG. 24.

Referring to FIG. 40, the lower gate electrode of the first transistor T1 may be connected to the first electrode of the first transistor T1. The first electrode of the first transistor T1 may be connected to the second electrode of the second transistor T2 and the second electrode of the fifth transistor T5. The lower gate electrode of the first transistor T1 may have the same potential as the first electrode of the first transistor T1. That is, the voltage of the lower gate electrode of the first transistor T1 and the voltage of the first electrode may be synchronized.

The lower gate electrode of the eighth transistor T8 may be connected to the first electrode of the eighth transistor T8. The first electrode of the eighth transistor T8 may be connected to the second electrode of the ninth transistor T9 and the second electrode of the twelfth transistor T12. The lower gate electrode of the eighth transistor T8 may have the same potential as the first electrode of the eighth transistor T8. That is, the voltage of the lower gate electrode and the voltage of the first electrode of the eighth transistor T8 may be synchronized.

Figure 41 is a layout diagram showing the first transistor of the first sub-pixel according to another embodiment.

The embodiment of FIG. 41 is different from the embodiment of FIG. 25 in that the first source electrode S1 of the first transistor T1 is connected to the first lower gate electrode BML1. In the embodiment of FIG. 41, descriptions overlapping with the embodiment of FIG. 25 will be omitted.

Referring to FIG. 41, the first source electrode S1 of the first transistor T1 may be connected to the first lower gate electrode BML1 through the fifth lower contact hole BCT5'. 41 illustrates that the fifth lower contact hole BCT5' overlaps the first gate electrode G1 and the second capacitor electrode CE2 of the first transistor T1 in the third direction DR3. The embodiments of the specification are not limited thereto. For example, the fifth lower contact hole BCT5' does not overlap the first gate electrode G1 of the first transistor T1 in the third direction DR3, but may overlap the second capacitor electrode CE2. You can. Alternatively, the fifth lower contact hole BCT5' may not overlap the first gate electrode G1 and the second capacitor electrode CE2 of the first transistor T1 in the third direction DR3.

The first lower gate electrode BML1 may overlap the first channel CH1, the first source electrode S1, and the first drain electrode D1 of the first transistor T1. Light incident from the outside is blocked by the first lower gate electrode BML1 and may not enter the first channel CH1 of the first transistor T1. Therefore, the light leakage current of the first transistor T1 can be reduced, thereby preventing multiple device identifiers (DIDs) from being recognized in the inspection mode.

Figure 42 is a layout diagram showing the eighth transistor of the first sub-pixel according to another embodiment.

The embodiment of FIG. 42 is different from the embodiment of FIG. 26 in that the eighth source electrode S8 of the eighth transistor T8 is connected to the eighth lower gate electrode BML8. In the embodiment of FIG. 42, descriptions overlapping with the embodiment of FIG. 26 will be omitted.

Referring to FIG. 42, the eighth source electrode S8 of the eighth transistor T8 may be connected to the eighth lower gate electrode BML8 through the sixth lower contact hole BCT6'. 42 illustrates that the sixth lower contact hole BCT6' overlaps the eighth gate electrode G8 and the fourth capacitor electrode CE4 of the eighth transistor T8 in the third direction DR3. The embodiments of the specification are not limited thereto. For example, the sixth lower contact hole BCT6' does not overlap the eighth gate electrode G8 of the eighth transistor T8 in the third direction DR3, but may overlap the fourth capacitor electrode CE4. You can. Alternatively, the sixth lower contact hole BCT6' may not overlap the eighth gate electrode G8 and the fourth capacitor electrode CE4 of the eighth transistor T1 in the third direction DR3.

The eighth lower gate electrode BML8 may overlap the eighth channel CH8, the eighth source electrode S8, and the eighth drain electrode D8 of the eighth transistor T8. Light incident from the outside is blocked by the eighth lower gate electrode BML8 and may not enter the eighth channel CH8 of the eighth transistor T8. Therefore, the light leakage current of the eighth transistor T8 can be reduced, thereby preventing multiple device identifiers (DIDs) from being recognized in the inspection mode.

FIG. 43 is a cross-sectional view showing an example of a display panel cut along line L-L' of FIG. 41. FIG. 44 is a cross-sectional view showing an example of a display panel cut along line MM′ of FIG. 42 .

43 and 44, the first source electrode S1 of the first transistor T1 is connected to the first lower gate electrode BML1, and the eighth source electrode S8 of the eighth transistor T8 is connected to the first lower gate electrode BML1. This is different from the embodiments of FIGS. 27 and 28 in that it is connected to the eighth lower gate electrode (BML8). In FIGS. 43 and 44 , descriptions overlapping with the embodiments of FIGS. 27 and 28 are omitted.

43 and 44, the first source electrode (S1) of the first transistor (T1) is connected to the first lower gate electrode (BML1) through the fifth lower contact hole (BCT5') penetrating the buffer film (BF). ) can be connected to.

The eighth source electrode S8 of the eighth transistor T8 may be connected to the eighth lower gate electrode BML8 through the sixth lower contact hole BCT6' penetrating the buffer film BF.

Figure 45 is a perspective view showing a tiled display device including a plurality of display devices according to an embodiment.

Referring to FIG. 45 , the tiled display device TDIS may include a plurality of display devices 11 , 12 , 13 , and 14 and a joint SM. For example, the tiled display device (TDIS) may include a first display device 11, a second display device 12, a third display device 13, and a fourth display device 14.

The plurality of display devices 11, 12, 13, and 14 may be arranged in a matrix form in M (M is a positive integer) rows and N (N is a positive integer) columns. For example, the first display device 11 and the second display device 12 may be adjacent to each other in the first direction DR1. The first display device 11 and the third display device 13 may be adjacent to each other in the second direction DR2. The third display device 13 and the fourth display device 14 may be adjacent to each other in the first direction DR1. The second display device 12 and the fourth display device 14 may be adjacent to each other in the second direction DR2.

However, the number and arrangement of the plurality of display devices 11, 12, 13, and 14 in the tiled display device TDIS are not limited to those shown in FIG. 45. The number and arrangement of the display devices 11, 12, 13, and 14 in the tiled display device (TDIS) depend on the size and shape of the display device 10 and the tiled display device (TDIS), respectively. It can be decided according to .

The plurality of display devices 11, 12, 13, and 14 may have the same size, but embodiments of the present specification are not limited thereto. For example, the plurality of display devices 11, 12, 13, and 14 may have different sizes.

Each of the plurality of display devices 11, 12, 13, and 14 may have a rectangular shape including a long side and a short side. The plurality of display devices 11, 12, 13, and 14 may be arranged with their long or short sides connected to each other. Some or all of the plurality of display devices 11, 12, 13, and 14 are disposed at the edge of the tiled display device TDIS and may form one side of the tiled display device TDIS. At least one display device among the plurality of display devices 11, 12, 13, and 14 may be disposed at at least one corner of the tiled display device TDIS, and may be disposed on two adjacent sides of the tiled display device TDIS. can be formed. At least one display device among the plurality of display devices 11, 12, 13, and 14 may be surrounded by other display devices.

Each of the plurality of display devices 11, 12, 13, and 14 may be substantially the same as the display device 10 described in connection with FIG. 1. Therefore, description of each of the plurality of display devices 11, 12, 13, and 14 will be omitted.

The joint SM may include a coupling member or an adhesive member. In this case, the plurality of display devices 11, 12, 13, and 14 may be connected to each other through a coupling member or adhesive member of the joint SM. The joint SM is between the first display device 11 and the second display device 12, between the first display device 11 and the third display device 13, and between the second display device 12 and the fourth display device 12. It may be disposed between the display devices 14 and between the third display device 13 and the fourth display device 14.

FIG. 46 is an enlarged layout diagram showing the Y area of FIG. 45 in detail.

Referring to FIG. 46, the joint SM is a tile-type display where the first display device 11, the second display device 12, the third display device 13, and the fourth display device 14 are adjacent to each other. The central area of the device (TDIS) may have the flat form of a cross, a cross, or a plus sign. The joint SM is between the first display device 11 and the second display device 12, between the first display device 11 and the third display device 13, and between the second display device 12 and the fourth display device 12. It may be disposed between the display devices 14 and between the third display device 13 and the fourth display device 14.

The first display device 11 may include first pixels PX1 arranged in a matrix form in the first direction DR1 and the second direction DR2 to display an image. The second display device 12 may include second pixels PX2 arranged in a matrix form in the first direction DR1 and the second direction DR2 to display an image. The third display device 13 may include third pixels PX3 arranged in a matrix form in the first direction DR1 and the second direction DR2 to display an image. The fourth display device 14 may include fourth pixels PX4 arranged in a matrix form in the first direction DR1 and the second direction DR2 to display an image.

The minimum distance between neighboring first pixels (PX1) in the first direction (DR1) is defined as the first horizontal separation distance (GH1), and the minimum distance between neighboring second pixels (PX2) in the first direction (DR1) is defined as It may be defined as the second horizontal separation distance (GH2). The first horizontal separation distance GH1 and the second horizontal separation distance GH2 may be substantially the same.

A joint SM may be disposed between the first pixel PX1 and the second pixel PX2 that are adjacent in the first direction DR1. The minimum distance G12 between the neighboring first pixel PX1 and the second pixel PX2 in the first direction DR1 is the distance between the first pixel PX1 and the joint SM in the first direction DR1. The minimum distance (GHS1), the minimum distance (GHS2) between the second pixel (PX2) and the seam (SM) in the first direction (DR1), and the width of the seam (SM) in the first direction (DR1) It can be the sum of GSM1).

The minimum distance G12, the first horizontal separation distance GH1, and the second horizontal separation distance GH2 between the first pixel PX1 and the second pixel PX2 neighboring in the first direction DR1 are substantially can be the same. To this end, the minimum distance (GHS1) between the first pixel (PX1) and the joint (SM) in the first direction (DR1) is smaller than the first horizontal separation distance (GH1), and the second The minimum distance (GHS2) between the pixel (PX2) and the joint (SM) may be smaller than the second horizontal separation distance (GH2). Additionally, the width GSM1 of the joint SM in the first direction DR1 may be smaller than the first horizontal distance GH1 or the second horizontal distance GH2.

The minimum distance between neighboring third pixels (PX3) in the first direction (DR1) is defined as the third horizontal separation distance (GH3), and the minimum distance between neighboring fourth pixels (PX4) in the first direction (DR1) is defined as It may be defined as the fourth horizontal separation distance (GH4). The third horizontal separation distance GH3 and the fourth horizontal separation distance GH4 may be substantially the same.

A joint SM may be disposed between the third and fourth pixels PX3 and PX4 that are adjacent in the first direction DR1. The minimum distance G34 between the neighboring third pixel PX3 and fourth pixel PX4 in the first direction DR1 is between the third pixel PX3 and the joint SM in the first direction DR1. The minimum distance (GHS3), the minimum distance (GHS4) between the fourth pixel (PX4) and the seam (SM) in the first direction (DR1), and the width of the seam (SM) in the first direction (DR1) It can be the sum of GSM1).

The minimum distance G34, the third horizontal separation distance GH3, and the fourth horizontal separation distance GH4 between the third pixel PX3 and the fourth pixel PX4 neighboring in the first direction DR1 are substantially can be the same. To this end, the minimum distance (GHS3) between the third pixel (PX3) and the joint (SM) in the first direction (DR1) is smaller than the third horizontal separation distance (GH3), and the fourth distance (GHS3) in the first direction (DR1) is smaller than the third horizontal separation distance (GH3). The minimum distance (GHS4) between the pixel (PX4) and the joint (SM) may be smaller than the fourth horizontal separation distance (GH4). Additionally, the width GSM1 of the joint SM in the first direction DR1 may be smaller than the third horizontal distance GH3 or the fourth horizontal distance GH4.

The minimum distance between neighboring first pixels (PX1) in the second direction (DR2) is defined as the first vertical separation distance (GV1), and the minimum distance between neighboring third pixels (PX3) in the second direction (DR2) is defined as It may be defined as the third vertical separation distance (GV3). The first vertical distance GV1 and the third vertical distance GV3 may be substantially the same.

A joint SM may be disposed between the first pixel PX1 and the third pixel PX3 that are adjacent in the second direction DR2. The minimum distance G13 between the neighboring first pixel PX1 and the third pixel PX3 in the second direction DR2 is between the first pixel PX1 and the joint SM in the second direction DR2. Minimum distance GVS1, minimum distance GVS3 between the third pixel PX3 and the seam SM in the second direction DR2, and width of the seam SM in the second direction DR2 ( It can be the sum of GSM2).

The minimum distance G13, the first vertical separation distance GV1, and the third vertical separation distance GV3 between the first pixel PX1 and the third pixel PX3 neighboring in the second direction DR2 are substantially can be the same. To this end, the minimum distance (GVS1) between the first pixel (PX1) and the joint (SM) in the second direction (DR2) is smaller than the first vertical separation distance (GV1), and the third The minimum distance (GVS3) between the pixel (PX3) and the joint (SM) may be smaller than the third vertical separation distance (GV3). Additionally, the width GSM2 of the joint SM in the second direction DR2 may be smaller than the first vertical distance GV1 or the third vertical distance GV3.

The minimum distance between neighboring second pixels (PX2) in the second direction (DR2) is defined as the second vertical separation distance (GV2), and the minimum distance between neighboring fourth pixels (PX4) in the second direction (DR2) is defined as It can be defined as the fourth vertical separation distance (GV4). The second vertical distance GV2 and the fourth vertical distance GV4 may be substantially the same.

A joint SM may be disposed between the second pixel PX2 and the fourth pixel PX4 that are adjacent in the second direction DR2. The minimum distance G24 between the neighboring second pixel PX2 and the fourth pixel PX4 in the second direction DR2 is between the second pixel PX2 and the joint SM in the second direction DR2. The minimum distance (GVS2), the minimum distance (GVS4) between the fourth pixel (PX4) and the seam (SM) in the second direction (DR2), and the distance of the seam (SM) in the second direction (DR2) It can be the sum of GSM4).

The minimum distance G24, the second vertical separation distance GV2, and the fourth vertical separation distance GV4 between the second pixel PX2 and the fourth pixel PX4 neighboring in the second direction DR2 are substantially can be the same. To this end, the minimum distance (GVS2) between the second pixel (PX2) and the joint (SM) in the second direction (DR2) is smaller than the second vertical separation distance (GV2), and the fourth The minimum distance GVS4 between the pixel PX4 and the joint SM may be smaller than the fourth vertical separation distance GV4. Additionally, the width GSM2 of the joint SM in the second direction DR2 may be smaller than the second vertical distance GV2 or the fourth vertical distance GV4.

As shown in FIG. 46, in order to prevent the seam SM between images displayed by a plurality of display devices 11, 12, 13, and 14 from being visible, the minimum distance between pixels of neighboring display devices is set to may be substantially equal to the minimum distance between each pixel.

FIG. 47 is a cross-sectional view showing an example of a tile-type display device cut along line N-N' of FIG. 46.

Referring to FIG. 47 , the first display device 11 includes a first display module (DPM1) and a first front cover (COV1). The second display device 12 includes a second display module (DPM2) and a second front cover (COV2).

Each of the first display module DPM1 and the second display module DPM2 includes a substrate SUB, a thin film transistor layer TFTL, and light emitting elements LE.

Referring to FIG. 47 , the display panel 100 may include a thin film transistor layer (TFTL) and light emitting elements (LE) disposed on a substrate (SUB). The thin film transistor layer (TFTL) may be a layer in which thin film transistors are formed. Thin film transistors may include first to nineteenth transistors T1 to T19 shown in FIGS. 5, 9, 20, 24, 29, 36, and 40.

The thin film transistor layer (TFTL) includes an active layer (ACT), a first gate metal layer, a second gate metal layer, a first source metal layer, a second source metal layer, a third source metal layer, a fourth source metal layer, and a transparent metal layer. In addition, the thin film transistor layer (TFTL) includes a buffer film (BF), a gate insulating film 130, a first interlayer insulating film 141, a second interlayer insulating film 142, a first planarization film 160, and a first inorganic insulating film ( 161), a second planarization film 180, a second inorganic insulating film 181, a third planarization film 190, a third inorganic insulating film 191, and a protective film (PVX1).

Active layer (ACT), first gate metal layer, second gate metal layer, first source metal layer, second source metal layer, buffer film (BF), gate insulating film 130, first interlayer insulating film 141, second interlayer insulating film (142), the first planarization film 160, the first inorganic insulating film 161, the second planarization film 180, the second inorganic insulating film 181, the third planarization film 190, and the third inorganic insulating film ( 191) has already been described previously in connection with FIGS. 15 to 17, so redundant description will be omitted.

The second source metal layer may further include a second anode connection electrode (ANDE2). The second anode connection electrode ANDE2 may be disposed on the first inorganic insulating film 161. The second anode connection electrode ANDE2 may be connected to the first anode connection electrode ANDE1 through the third anode contact hole ANCT3 penetrating the first planarization film 160 and the first inorganic insulating film 161.

The third source metal layer may include a third anode connection electrode ANDE3. The third anode connection electrode ANDE3 may be disposed on the second inorganic insulating film 181. The third anode connection electrode ANDE3 may be connected to the second anode connection electrode ANDE2 through the fourth anode contact hole ANCT4 penetrating the second planarization film 180 and the second inorganic insulating film 181.

The fourth source metal layer may include an anode pad electrode (APD) and a cathode pad electrode (CPD). The anode pad electrode (APD) and the cathode pad electrode (CPD) may be disposed on the third inorganic insulating layer 191. The anode pad electrode (APD) may be connected to the third anode connection electrode (ANDE3) through the fifth anode contact hole (ACT5) penetrating the third planarization film 190 and the third inorganic insulating film 191. The cathode pad electrode (CPD) may be supplied with a first power voltage that is a low potential voltage. The fourth data metal layer is any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It can be formed as a single layer or multiple layers made of alloy.

The transparent metal layer (TCO) may be disposed on the anode pad electrode (APD) and the cathode pad electrode (CPD). The transparent metal layer (TCO) may be a layer to increase adhesion to the first contact electrode (CTE1) and the second contact electrode (CTE2) of the light emitting device (LE). The transparent metal layer (TCO) may be formed of a transparent conductive oxide such as indium tin oxide (ITO) and indium zinc oxide (IZO).

A protective film (PVX1) may be disposed on the anode pad electrode (APD), the cathode pad electrode (CPD), and the transparent metal layer (TCO). The protective film PVX1 may be disposed to cover the edges of the anode pad electrode (APD), the cathode pad electrode (CPD), and the transparent metal layer (TCO). The protective film PVX1 may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The light emitting device (LE) is illustrated as a flip chip type micro LED in which the first contact electrode (CTE1) and the second contact electrode (CTE2) are arranged to face the anode pad electrode (APD) and the cathode pad electrode (CPD). . The light emitting device (LE) may be an inorganic light emitting device made of an inorganic material such as GaN. The light emitting device LE may have a length of several to hundreds of μm in the first direction DR1, a length in the second direction DR2, and a length in the third direction DR3, respectively. For example, the length of the light emitting device LE in the first direction DR1, the length in the second direction DR2, and the length in the third direction DR3 may each be approximately 100 μm or less.

Light emitting elements (LE) may be formed by growing on a semiconductor substrate such as a silicon wafer. Each of the light emitting elements (LE) can be directly transferred from the silicon wafer onto the anode pad electrode (APD) and cathode pad electrode (CPD) of the substrate (SUB). Alternatively, each of the light emitting elements (LE) is connected to the anode pad electrode of the substrate (SUB) through an electrostatic method using an electrostatic head or a stamp method using an elastic polymer material such as PDMS or silicon as a transfer substrate. (APD) and cathode pad electrode (CPD).

Each of the light emitting elements (LE) includes a base substrate (SSUB), an n-type semiconductor (NSEM), an active layer (MQW), a p-type semiconductor (PSEM), a first contact electrode (CTE1), and a second contact electrode (CTE2). It may be a light-emitting structure.

The base substrate (SSUB) may be a sapphire substrate, but embodiments of the present specification are not limited thereto.

The n-type semiconductor (NSEM) may be disposed on one side of the base substrate (SSUB). For example, an n-type semiconductor (NSEM) may be disposed on the lower surface of the base substrate (SSUB). An n-type semiconductor (NSEM) may be made of GaN doped with an n-type conductive dopant such as Si, Ge, or Sn.

The active layer (MQW) may be disposed on a portion of one side of the n-type semiconductor (NSEM). The active layer (MQW) may include a material with a single or multiple quantum well structure. When the active layer (MQW) includes a material with a multi-quantum well structure, it may have a structure in which a plurality of well layers and barrier layers are alternately stacked. At this time, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but are not limited thereto. Alternatively, the active layer (MQW) may be a structure in which a type of semiconductor material with a large band gap energy and a semiconductor material with a small band gap energy are alternately stacked, and other types of semiconductor materials from group 3 to 3 depending on the wavelength of the emitted light. It may also contain Group 5 semiconductor materials.

A p-type semiconductor (PSEM) may be disposed on one side of the active layer (MQW). A p-type semiconductor (PSEM) may be made of GaN doped with a p-type conductive dopant such as Mg, Zn, Ca, Se, Ba, etc.

The first contact electrode (CTE1) may be disposed on the p-type semiconductor (PSEM), and the second contact electrode (CTE2) may be disposed on another part of one side of the n-type semiconductor (NSEM). Another part of one surface of the n-type semiconductor NSEM on which the second contact electrode CTE2 is disposed may be disposed away from a part of one surface of the n-type semiconductor NSEM on which the active layer MQW is disposed.

The first contact electrode (CTE1) and the anode pad electrode (APD) may be bonded to each other through a conductive adhesive member such as an anisotropic conductive film (ACF) or anisotropic conductive paste (ACP). Alternatively, the first contact electrode (CTE1) and the anode pad electrode (APD) may be bonded to each other through a soldering process.

The distance GSUB between the substrate SUB of the first display device 11 and the substrate SUB of the second display device 12 is the distance between the first front cover COV1 and the second front cover COV2. It can be larger than (GCOV).

The first front cover (COV1) and the second front cover (COV2) each have an adhesive member 51, a light transmittance adjustment layer 52 disposed on the adhesive member 51, and a light transmittance adjustment layer 52. It may include an anti-glare layer (53) disposed.

The adhesive member 51 of the first front cover (COV1) serves to attach the light emitting element layer (EML) of the first display module (DPM1) to the first front cover (COV1). The adhesive member 51 of the second front cover (COV2) serves to attach the light emitting element layer (EML2) of the second display module (DPM2) to the second front cover (COV2). The adhesive member 51 may be a transparent adhesive member capable of transmitting light. For example, the adhesive member 51 may be an optically clear adhesive film or an optically clear resin.

The anti-glare layer 53 may be designed to diffusely reflect external light in order to prevent external light from being directly reflected and deteriorating image visibility. Accordingly, the anti-glare layer 53 can increase the contrast ratio of images displayed by the first display device 10 and the second display device 20.

The light transmittance adjustment layer 52 may be designed to reduce the transmittance of external light or light reflected from the first display module DPM1 and the second display module DPM2. As a result, the gap GSUB between the substrate SUB of the first display module DPM1 and the substrate SUB of the second display module DPM2 can be prevented from being viewed from the outside.

The anti-glare layer 53 may be implemented as a polarizing plate, and the light transmittance adjustment layer 52 may be implemented as a phase retardation layer, but the embodiments of the present specification are not limited thereto.

Meanwhile, an example of a tile-type display device cut along O-O', P-P', and Q-Q' of FIG. 46 is a tile-type display device cut along N-N' described in conjunction with FIG. 47. Since it is substantially the same as an example of, description thereof is omitted.

Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention can be implemented in other specific forms without changing its technical idea or essential features. You will be able to understand it. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

10: display device
RP: 1st sub-pixel
GP: 2nd sub pixel
BP: Third sub-pixel
LE: light emitting element
PDU1: first pixel driver
PDU2: second pixel driver
PDU3: Third pixel driving unit

Claims (21)

It has a sub-pixel connected to a scan write line, a first data line, and a second data line,
The sub-pixel is,
light emitting device;
a first pixel driver that generates a control current according to the first data voltage of the first data line;
a second pixel driver that generates a driving current applied to the light emitting device according to a second data voltage of the second data line; and
and a third pixel driver that applies the driving current to the light emitting device according to the control current of the first pixel driver,
The first pixel driver,
a first transistor generating the control current according to the first data voltage;
a second transistor that applies the first data voltage of the first data line to a first electrode of the first transistor according to a scan write signal of the scan write line; and
A third transistor connecting a gate electrode and a second electrode of the first transistor according to the scan write signal of the scan write line,
The third transistor includes a first sub-transistor and a second sub-transistor connected in series between the gate electrode of the first transistor and the second electrode,
A display device wherein the channel of the first sub-transistor and the channel of the second sub-transistor overlap a lower gate electrode of the third transistor. According to claim 1,
A display device wherein the lower gate electrode of the third transistor is connected to the gate electrode of the first sub-transistor and the gate electrode of the second sub-transistor. According to claim 1,
The lower gate electrode of the third transistor is connected to the first electrode of the first sub-transistor,
A display device in which a first electrode of the first sub-transistor is connected to a second electrode of the first transistor. According to claim 1,
The first pixel driver,
A fourth transistor that initializes the voltage of the gate electrode of the first transistor to an initialization voltage according to the scan initialization signal of the scan initialization line,
The fourth transistor includes a third sub-transistor and a fourth sub-transistor connected in series between the gate electrode of the first transistor and an initialization voltage line to which the initialization voltage is applied,
A display device wherein the channel of the third sub-transistor and the channel of the fourth sub-transistor overlap a lower gate electrode of the fourth transistor. According to clause 4,
A display device wherein the lower gate electrode of the fourth transistor is connected to the gate electrode of the third sub-transistor and the gate electrode of the fourth sub-transistor. According to clause 4,
The lower gate electrode of the fourth transistor is connected to the first electrode of the third sub-transistor,
A display device wherein the first electrode of the third sub-transistor is connected to the gate electrode of the first transistor. According to claim 1,
A display device in which a channel of the first transistor overlaps a lower gate electrode of the first transistor. According to clause 7,
A display device wherein a lower gate electrode of the first transistor is connected to a gate electrode of the first transistor. According to clause 7,
A display device wherein a lower gate electrode of the first transistor is connected to a first electrode of the first transistor. According to claim 1,
A lower gate electrode of the third transistor is disposed between the channel of the first sub-transistor and the substrate, and the lower gate electrode of the third transistor is disposed between the channel of the second sub-transistor and the substrate. According to claim 1,
The second electrode of the light emitting device is connected to a first power wiring to which a first power voltage is applied,
The third pixel driver includes a fifth transistor that electrically connects the first electrode of the light emitting device to the first power line according to a test signal of the test signal line. According to claim 11,
A display device wherein the second electrode of the fifth transistor overlaps a light blocking layer. According to claim 12,
A display device in which the light blocking layer is electrically floating. According to claim 12,
A display device wherein the lower gate electrode of the third transistor includes the same material as the light blocking layer. According to claim 12,
The lower gate electrode of the third transistor and the light blocking layer are disposed on a substrate,
A buffer film is disposed on a lower gate electrode of the third transistor and the light blocking layer. It has a sub-pixel connected to a scan write line, a first data line, and a second data line,
The sub-pixel is,
light emitting device;
a first pixel driver that generates a control current according to the first data voltage of the first data line;
a second pixel driver that generates a driving current applied to the light emitting device according to a second data voltage of the second data line; and
and a third pixel driver that applies the driving current to the light emitting device according to the control current of the first pixel driver,
The second pixel driver,
a first transistor generating the driving current according to the second data voltage;
a second transistor that applies the second data voltage of the second data line to a first electrode of the first transistor according to a scan write signal of the scan write line; and
A third transistor connecting a gate electrode and a second electrode of the first transistor according to the scan write signal of the scan write line,
The third transistor includes a first sub-transistor and a second sub-transistor connected in series between the gate electrode of the first transistor and the second electrode,
A display device wherein the channel of the first sub-transistor and the channel of the second sub-transistor overlap a lower gate electrode of the third transistor. According to claim 16,
A display device wherein the lower gate electrode of the third transistor is connected to the gate electrode of the first sub-transistor and the gate electrode of the second sub-transistor. According to claim 16,
The lower gate electrode of the third transistor is connected to the first electrode of the first sub-transistor,
A display device in which a first electrode of the first sub-transistor is connected to a second electrode of the first transistor. According to claim 16,
The channel of the first transistor overlaps the lower gate electrode of the first transistor,
A display device wherein a lower gate electrode of the first transistor is connected to a gate electrode of the first transistor. According to claim 16,
The channel of the first transistor overlaps the lower gate electrode of the first transistor,
A display device wherein a lower gate electrode of the first transistor is connected to a first electrode of the first transistor. a plurality of display devices; and
having a joint disposed between the plurality of display devices,
Among the plurality of display devices, one display device is:
It has a sub-pixel connected to a scan write line, a first data line, and a second data line,
The sub-pixel is,
light emitting device;
a first pixel driver that generates a control current according to the first data voltage of the first data line;
a second pixel driver that generates a driving current applied to the light emitting device according to a second data voltage of the second data line; and
and a third pixel driver that applies the driving current to the light emitting device according to the control current of the first pixel driver,
The first pixel driver,
a first transistor generating the control current according to the first data voltage;
a second transistor that applies the first data voltage of the first data line to a first electrode of the first transistor according to a scan write signal of the scan write line; and
A third transistor connecting a gate electrode and a second electrode of the first transistor according to the scan write signal of the scan write line,
The third transistor includes a first sub-transistor and a second sub-transistor connected in series between the gate electrode of the first transistor and the second electrode,
A tiled display device wherein the channel of the first sub-transistor and the channel of the second sub-transistor overlap a lower gate electrode of the third transistor.

Images