KR20240042935A - Power management circuit and display device - Google Patents

Abstract

Embodiments of the present disclosure relate to a power management circuit and a display device, and more specifically, to a high-frequency detection circuit that removes high-frequency components of input power, and a first voltage that outputs a first driving voltage by stepping down the input power. A converter, a second converter that boosts the input power and outputs a second driving voltage, a third converter that converts the second driving voltage and outputs a third driving voltage, and detects noise at a plurality of noise nodes A power management circuit including a noise cancellation circuit that generates a noise cancellation signal can be provided.

Description

Power management circuit and display device {POWER MANAGEMENT CIRCUIT AND DISPLAY DEVICE}

Embodiments of the present disclosure relate to a power management circuit and a display device, and more specifically, to a power management circuit and a display device that can detect and effectively cancel major noise generated in the power management circuit.

As the information society develops, various demands for display devices that display images are increasing, and various types of display devices such as Liquid Crystal Display (LCD), Organic Light Emitting Display, etc. It is being utilized.

Among these display devices, organic light emitting display devices use organic light emitting diodes that emit light on their own, so they have advantages in terms of fast response speed, contrast ratio, luminous efficiency, luminance, and viewing angle.

This organic light emitting display device includes organic light emitting diodes disposed in each of a plurality of sub-pixels arranged on a display panel, and causes the organic light emitting diodes to emit light by controlling the current flowing through the organic light emitting diodes, so that each sub Images can be displayed by controlling the luminance expressed by pixels.

These display devices include a display panel that displays images through a subpixel array, a driving circuit that drives the display panel, a timing controller that controls the operation timing of the driving circuit, and driving the display panel. It may include a power management circuit that generates the necessary power.

Among these, the power management circuit controls the level of the input power when the power switch of the display device is turned on and outputs the logic voltage required for the operation of the timing controller, driving circuit, and display panel. .

For this purpose, the power management circuit includes a boost converter for step-up to supply an output voltage at a higher level than the input power and a buck converter for step-down to supply an output voltage at a lower level than the input power. It will be designed in the form of a system on chip.

At this time, noise may be generated during the switching process of the converter located inside the power management circuit, and this noise may cause a malfunction in the display device.

Accordingly, the inventors of the present disclosure have invented a power management circuit and a display device that can generate a stable driving voltage by removing internal noise.

Embodiments of the present disclosure can provide a power management circuit and a display device that can clarify noise generation points and thereby suppress noise.

Embodiments of the present disclosure include a high-frequency detection circuit that removes high-frequency components of the input power, a first converter that outputs a first driving voltage by stepping down the input power, and outputting a second driving voltage by boosting the input power. A power management circuit including a second converter, a third converter that converts the second driving voltage and outputs a third driving voltage, and a noise canceling circuit that detects noise at a plurality of noise nodes and generates a noise canceling signal. can be provided.

Embodiments of the present disclosure include a display panel on which a plurality of gate lines, a plurality of data lines, and a plurality of subpixels are arranged, a gate driving circuit for supplying a scan signal to the plurality of gate lines, and converting digital image data into analog data. a data driving circuit that converts the voltage into a voltage and supplies it to the plurality of data lines, a timing controller that controls the gate driving circuit and the data driving circuit, the display panel, the gate driving circuit, the data driving circuit, and the A power management circuit that supplies a driving voltage to the timing controller, wherein the power management circuit includes a high-frequency detection circuit that removes high-frequency components of the input power, a first converter that steps down the input power and outputs a first driving voltage, and , a second converter that boosts the input power to output a second driving voltage, a third converter that converts the second driving voltage to output a third driving voltage, and detects noise at a plurality of noise nodes to cancel noise. A display device including a noise cancellation circuit that generates a signal can be provided.

According to embodiments of the present disclosure, there is an effect of generating a stable driving voltage by removing internal noise.

According to the embodiments of the present disclosure, there is an effect of clarifying the noise generation point and suppressing the noise through this.

1 is a diagram illustrating a schematic configuration of a display device according to embodiments of the present disclosure.
Figure 2 is a system diagram of a display device according to an embodiment of the present specification.
3 is an example diagram of a circuit forming a subpixel in a display device according to embodiments of the present disclosure.
Figure 4 is a diagram illustrating the internal configuration and main noise of the power management circuit as an example.
Figure 5 is a diagram showing the configuration of a power management circuit according to embodiments of the present disclosure.
FIG. 6 is a diagram illustrating the waveform of a noise detection signal applied to an amplifier circuit through a noise detection circuit in a power management circuit according to embodiments of the present disclosure.
FIG. 7 is a diagram showing an example of a structure in which the non-inverting input terminal of an amplifier constituting the noise cancellation circuit is connected to the device ground in the power management circuit according to embodiments of the present disclosure.
FIG. 8 is a diagram illustrating signal waveforms when the amplifier of the noise cancellation circuit is connected to the electrical ground and when the amplifier of the noise cancellation circuit is connected to the device ground in the power management circuit according to embodiments of the present disclosure.
FIG. 9 is a diagram comparing signal waveforms of a case without a noise cancellation circuit and a case of including a noise cancellation circuit in the display device according to embodiments of the present disclosure.

Hereinafter, some embodiments of the present disclosure will be described in detail with reference to illustrative drawings. In adding reference numerals to components in each drawing, identical components may have the same reference numerals as much as possible even if they are shown in different drawings. Additionally, in describing the present disclosure, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present disclosure, the detailed description may be omitted. When “comprises,” “has,” “consists of,” etc. mentioned in the specification are used, other parts may be added unless “only” is used. When a component is expressed in the singular, it can also include the plural, unless specifically stated otherwise.

Additionally, in describing the components of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the components are not limited by the term.

In the description of the positional relationship of components, when two or more components are described as being “connected,” “coupled,” or “connected,” the two or more components are directly “connected,” “coupled,” or “connected.” ", but it should be understood that two or more components and other components may be further "interposed" and "connected," "combined," or "connected." Here, other components may be included in one or more of two or more components that are “connected,” “coupled,” or “connected” to each other.

In the description of temporal flow relationships related to components, operation methods, production methods, etc., for example, temporal precedence relationships such as “after”, “after”, “after”, “before”, etc. Or, when a sequential relationship is described, non-continuous cases may be included unless “immediately” or “directly” is used.

Meanwhile, when a numerical value or corresponding information (e.g., level, etc.) for a component is mentioned, even if there is no separate explicit description, the numerical value or corresponding information is related to various factors (e.g., process factors, internal or external shocks, It can be interpreted as including the error range that may occur due to noise, etc.).

Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the attached drawings.

1 is a diagram illustrating a schematic configuration of a display device according to embodiments of the present disclosure.

Referring to FIG. 1, the display device 100 according to embodiments of the present disclosure has a plurality of gate lines (GL) and data lines (DL) connected and a plurality of subpixels (SP) arranged in a matrix form. A display panel 110, a gate driving circuit 120 that drives a plurality of gate lines (GL), a data driving circuit 130 that supplies a data voltage through a plurality of data lines (DL), and a gate driving circuit 120. and a timing controller 140 that controls the data driving circuit 130, and a power management circuit 150.

The display panel 110 is based on a scan signal transmitted from the gate driving circuit 120 through a plurality of gate lines (GL) and a data voltage transmitted from the data driving circuit 130 through a plurality of data lines (DL). Display the video.

In the case of a liquid crystal display, the display panel 110 includes a liquid crystal layer formed between two substrates, and operates in Twisted Nematic (TN) mode, Vertical Alignment (VA) mode, In Plane Switching (IPS) mode, and Fringe Field Switching (FFS) mode. ) mode, etc. may be operated in any known mode. On the other hand, in the case of an organic light emitting display, the display panel 110 may be implemented in a top emission method, a bottom emission method, or a dual emission method.

The display panel 110 may have a plurality of pixels arranged in a matrix form, and each pixel has subpixels (SP) of different colors, for example, white subpixel, red subpixel, green subpixel, and blue subpixel. It consists of, and each subpixel (SP) may be defined by a plurality of data lines (DL) and a plurality of gate lines (GL).

One subpixel (SP) is a thin film transistor (TFT) formed in the area where one data line (DL) and one gate line (GL) intersect, and a light-emitting device such as an organic light-emitting diode that charges data voltage. It may include a storage capacitor that is electrically connected to the device and the light emitting device to maintain the voltage.

For example, if the display device 100 with a resolution of 2,160 By 3,840 data lines (DL) connected to the gate line (GL) and four subpixels (WRGB), a total of 3,840 A subpixel (SP) will be placed at each point where ) and the data line (DL) intersect.

The gate driving circuit 120 is controlled by the controller 140, which sequentially outputs scan signals to the plurality of gate lines (GL) disposed on the display panel 110 to determine the driving timing for the plurality of subpixels (SP). control.

In the display device 100 with a resolution of 2,160 can do. Alternatively, as in the case of sequentially outputting scan signals from the first gate line to the fourth gate line and then sequentially outputting the scan signals from the fifth gate line to the eighth gate line, four gate lines (GL) The case where scan signals are output sequentially in units is called 4-phase drive. In other words, the case of sequentially outputting scan signals for each N gate lines (GL) can be referred to as N-phase driving.

At this time, the gate driving circuit 120 may include one or more gate driving integrated circuits (GDIC), and depending on the driving method, it may be located only on one side of the display panel 110 or on both sides. It may be located. Alternatively, the gate driving circuit 120 may be built into the bezel area of the display panel 110 and implemented in a GIP (Gate In Panel) form.

The data driving circuit 130 receives image data DATA from the timing controller 140 and converts the received image data DATA into an analog data voltage. Then, the data voltage is output to each data line (DL) according to the timing when the scan signal is applied through the gate line (GL), so that each subpixel (SP) connected to the data line (DL) corresponds to the data voltage. Displays a light emitting signal with a brightness of

Likewise, the data driving circuit 130 may include one or more source driving integrated circuits (SDICs), which may use a Tape Automated Bonding (TAB) method or a Chip On Glass (COG) method. ) may be connected to a bonding pad of the display panel 110 or may be placed directly on the display panel 110.

In some cases, each source driving integrated circuit (SDIC) may be integrated and disposed on the display panel 110. In addition, each source driving integrated circuit (SDIC) may be implemented in a COF (Chip On Film) method. In this case, each source driving integrated circuit (SDIC) is mounted on a circuit film and displays the display panel through the circuit film. It may be electrically connected to the data line (DL) of (110).

The timing controller 140 supplies various control signals to the gate driving circuit 120 and the data driving circuit 130, and controls the operations of the gate driving circuit 120 and the data driving circuit 130. That is, the timing controller 140 controls the gate driving circuit 120 to output a scan signal according to the timing implemented in each frame, and on the other hand, the externally received image data (DATA) is controlled by the data driving circuit 130. ) is delivered to.

At this time, the timing controller 140 includes video data (DATA), a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable; DE), a main clock (MCLK), etc. Various timing signals are received from the external host system 200.

The host system 200 may be any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a wearable device.

Accordingly, the timing controller 140 generates a control signal using various timing signals received from the host system 200 and transmits the control signal to the gate driving circuit 120 and the data driving circuit 130.

For example, the timing controller 140 uses a gate start pulse (GSP), a gate clock (GCLK), and a gate output enable signal (Gate Output Enable) to control the gate driving circuit 120. It outputs various gate control signals including ; GOE), etc. Here, the gate start pulse (GSP) controls the timing at which one or more gate driving integrated circuits (GDIC) constituting the gate driving circuit 120 start operating. Additionally, the gate clock (GCLK) is a clock signal commonly input to one or more gate driving integrated circuits (GDIC), and controls the shift timing of the scan signal. Additionally, the gate output enable signal (GOE) specifies timing information of one or more gate driver integrated circuits (GDIC).

In addition, the timing controller 140 uses a source start pulse (SSP), a source sampling clock (SCLK), and a source output enable signal (Source Output Enable signal) to control the data driving circuit 130. Outputs various data control signals including ; SOE), etc. Here, the source start pulse (SSP) controls the timing at which one or more source driving integrated circuits (SDICs) constituting the data driving circuit 130 start sampling data. The source sampling clock (SCLK) is a clock signal that controls the timing of sampling data in a source driving integrated circuit (SDIC). The source output enable signal (SOE) controls the output timing of the data driving circuit 130.

This display device 100 supplies various voltages or currents to the display panel 110, gate driving circuit 120, data driving circuit 130, etc., or includes a power management circuit 150 that controls various voltages or currents to be supplied. may include.

The power management circuit 150 adjusts the direct current input power (Vin) supplied from the host system 200 to operate the display panel 100, the gate driving circuit 120, the data driving circuit 130, and the timing controller 140. Generates power required for operation.

The power management circuit 150 starts operating when the input power (Vin) supplied from the host system 200 is above the UVLO (Under Voltage Lock Out) level, and generates an output signal after a predetermined time delay. The input power (Vin) may be a voltage of 12V.

The output signal of the power management circuit 150 may include gate high voltage (VGH), gate low voltage (VGL), buck voltage (VCC1, VCC2, VCC3), and pixel driving voltage (ELVDD, ELVSS).

For example, the first converter boosts the level of the input power Vin applied to the power management circuit 150 and outputs a boost voltage at a higher level than the input power Vin. The boost voltage may include a gate high voltage (VGH) and a gate low voltage (VGL) that operate the gate driving circuit 120.

The gate high voltage (VGH) is a voltage that can turn on the gate driving circuit 120, and may be, for example, a voltage of 28V.

Additionally, the second converter that steps down the input power source Vin in the power management circuit 150 may output a plurality of buck voltages VCC1, VCC2, and VCC3.

The first buck voltage VCC1 is a first logic voltage for operating the timing controller 140 and may be a voltage of 1V to 1.2V.

The second buck voltage (VCC2) has a different level from the first buck voltage (VCC1) and may be a second logic voltage for operating the data driving circuit 130 and may be a voltage of 1.7V to 1.9V.

The third buck voltage (VCC3) has a different level from the first buck voltage (VCC1) and the second buck voltage (VCC2), and is used as a third logic for driving memory, including EEPROM (Electrically Erasable Programmable Read-Only Memory). The voltage can have a value of 3.2V to 3.4V.

The buck voltages (VCC1, VCC2, VCC3) used in the display device 100 are of the three levels of 1V to 1.2V, 1.7V to 1.9V, and 3.2V to 3.4V mentioned above. Depending on the type, the voltage level and supply sequence may be different.

Additionally, the third converter may output pixel driving voltages (ELVDD and ELVSS) that drive subpixels of the display panel 110.

Meanwhile, the subpixel SP is located at a point where the gate line GL and the data line DL intersect, and a light emitting device may be disposed in each subpixel SP. For example, an organic light emitting display device includes a light emitting device such as an organic light emitting diode in each subpixel (SP), and can display an image by controlling a current flowing through the light emitting device according to a data voltage.

The display device 100 may be of various types, such as a liquid crystal display, an organic light emitting display, or a plasma display panel.

Figure 2 is a system diagram of a display device according to an embodiment of the present specification.

Referring to FIG. 2, the display device 100 according to embodiments of the present disclosure has a source driving integrated circuit (SDIC) included in the data driving circuit 130 that uses COF among various methods (TAB, COG, COF, etc.). It is implemented in a (Chip On Film) method, and the gate driving circuit 120 is implemented in a GIP (Gate In Panel) form among various methods (TAB, COG, COF, GIP, etc.).

When the gate driving circuit 120 is implemented in the GIP form, a plurality of gate driving integrated circuits (GDICs) included in the gate driving circuit 120 may be formed directly in the bezel area of the display panel 110. At this time, the gate driving integrated circuit (GDIC) can receive various signals (clock signal, gate high signal, gate low signal, etc.) necessary for generating the scan signal through the gate driving-related signal wiring arranged in the bezel area. .

Likewise, one or more source driving integrated circuits (SDICs) included in the data driving circuit 130 may each be mounted on the source film (SF), and one side of the source film (SF) is electrically connected to the display panel 110. can be connected Additionally, wires for electrically connecting the source driving integrated circuit (SDIC) and the display panel 110 may be disposed on the source film SF.

This display device 100 includes at least one source printed circuit board (SPCB), control components, and various electrical components for circuit connection between a plurality of source driving integrated circuits (SDICs) and other devices. It may include a control printed circuit board (CPCB) for mounting devices.

At this time, the other side of the source film (SF) on which the source driving integrated circuit (SDIC) is mounted may be connected to at least one source printed circuit board (SPCB). That is, one side of the source film SF on which the source driving integrated circuit (SDIC) is mounted may be electrically connected to the display panel 110, and the other side may be electrically connected to the source printed circuit board (SPCB).

A timing controller 140 and a power management circuit 150 may be mounted on a control printed circuit board (CPCB). The timing controller 140 may control the operations of the data driving circuit 130 and the gate driving circuit 120. The power management circuit 150 may supply driving voltage or current to the display panel 110, the data driving circuit 130, and the gate driving circuit 120, and may control the supplied voltage or current.

At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be connected circuitously through at least one connecting member, for example, a flexible printed circuit (FPC). , it may be made of a flexible flat cable (FFC), etc. Additionally, at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be integrated and implemented as one printed circuit board.

The display device 100 may further include a set board (Set Board) 170 electrically connected to a control printed circuit board (CPCB). At this time, the set board 170 may also be referred to as a power board. A main power management circuit 160 that manages the overall power of the display device 100 may be present in this set board 170. The main power management circuit 160 may be interconnected with the power management circuit 150.

In the case of the display device 100 configured as above, the driving voltage is generated in the set board 170 and transmitted to the power management circuit 150 in the control printed circuit board (CPCB). The power management circuit 150 transmits the driving voltage required for display driving or characteristic value sensing to the source printed circuit board (SPCB) through a flexible printed circuit (FPC) or flexible flat cable (FFC). The driving voltage delivered to the source printed circuit board (SPCB) is supplied to emit or sense a specific subpixel (SP) in the display panel 110 through the source driving integrated circuit (SDIC).

At this time, each subpixel SP arranged on the display panel 110 in the display device 100 may be composed of a light emitting element and a circuit element such as a driving transistor for driving the same.

The type and number of circuit elements constituting each subpixel (SP) may be determined in various ways depending on the provided function and design method.

3 is an example diagram of a circuit forming a subpixel in a display device according to embodiments of the present disclosure.

Referring to FIG. 3, in the display device 100 according to embodiments of the present disclosure, the subpixel SP may include one or more transistors and a capacitor, and an organic light emitting diode may be disposed as the light emitting element ED. You can.

For example, the subpixel (SP) may include a driving transistor (DRT), a switching transistor (SWT), a sensing transistor (SENT), a storage capacitor (Cst), and a light emitting element (ED).

The driving transistor DRT has a first node N1, a second node N2, and a third node N3. The first node (N1) of the driving transistor (DRT) may be a gate node to which the data voltage (Vdata) is applied from the data driving circuit 130 through the data line (DL) when the switching transistor (SWT) is turned on. there is. The second node N2 of the driving transistor DRT may be electrically connected to the anode electrode of the light emitting device ED and may be a source node or a drain node. The third node N3 of the driving transistor DRT is electrically connected to the driving voltage line DVL to which the pixel driving voltage ELVDD is applied, and may be a drain node or a source node.

At this time, during the display driving period, the pixel driving voltage (ELVDD) required to display the image may be supplied through the driving voltage line (DVL). For example, the pixel driving voltage (ELVDD) required to display the image may be 27V. there is.

The switching transistor (SWT) is electrically connected between the first node (N1) of the driving transistor (DRT) and the data line (DL), and the gate line (GL) is connected to the gate node and supplied through the gate line (GL). It operates according to the scan signal (SCAN). In addition, when the switching transistor (SWT) is turned on, the operation of the driving transistor (DRT) is controlled by transferring the data voltage (Vdata) supplied through the data line (DL) to the gate node of the driving transistor (DRT). I do it.

The sensing transistor (SENT) is electrically connected between the second node (N2) of the driving transistor (DRT) and the reference voltage line (RVL), and the gate line (GL) is connected to the gate node to transmit energy through the gate line (GL). It operates according to the supplied sense signal (SENSE). When the sensing transistor (SENT) is turned on, the sensing reference voltage (Vref) supplied through the reference voltage line (RVL) is transmitted to the second node (N2) of the driving transistor (DRT).

That is, by controlling the switching transistor (SWT) and the sensing transistor (SENT), the first node (N1) voltage and the second node (N2) voltage of the driving transistor (DRT) are controlled, which causes the light emitting device (ED) Ensure that current to drive is supplied.

The gate nodes of the switching transistor (SWT) and the sensing transistor (SENT) may be connected together to one gate line (GL) or may be connected to different gate lines (GL). Here, a structure in which the switching transistor (SWT) and the sensing transistor (SENT) are connected to different gate lines (GL) is shown as an example. In this case, the scan signal (SCAN) transmitted through different gate lines (GL) and The switching transistor (SWT) and sensing transistor (SENT) can be controlled independently by the sense signal (SENSE).

On the other hand, when the switching transistor (SWT) and sensing transistor (SENT) are connected to one gate line (GL), switching is performed by the scan signal (SCAN) or sense signal (SENSE) transmitted through one gate line (GL). The transistor (SWT) and sensing transistor (SENT) can be controlled simultaneously, and the aperture ratio of the subpixel (SP) can be increased.

Meanwhile, the transistor disposed in the subpixel SP may be made of not only an n-type transistor but also a p-type transistor, and here, the case of being made of an n-type transistor is shown as an example.

The storage capacitor Cst is electrically connected between the first node N1 and the second node N2 of the driving transistor DRT and maintains the data voltage Vdata for one frame.

This storage capacitor Cst may be connected between the first node N1 and the third node N3 of the driving transistor DRT depending on the type of the driving transistor DRT. The anode electrode of the light emitting device (ED) may be electrically connected to the second node (N2) of the driving transistor (DRT), and the base voltage (ELVSS) may be applied to the cathode electrode of the light emitting device (ED). .

Here, the base voltage (ELVSS) may be the ground voltage or a voltage higher or lower than the ground voltage. Additionally, the electromotive voltage (ELVSS) may vary depending on the driving state. For example, the base voltage (ELVSS) at the time of display driving and the base voltage (ELVSS) at the time of sensing driving may be set differently.

The structure of the subpixel (SP) described above as an example is a 3T (Transistor) 1C (Capacitor) structure, which is only an example for explanation, and may further include one or more transistors or, in some cases, one or more capacitors. It may include more. Alternatively, each of the multiple subpixels (SP) may have the same structure, or some of the multiple subpixels (SP) may have a different structure.

Figure 4 is a diagram illustrating the internal configuration and main noise of the power management circuit as an example.

Referring to FIG. 4, the power management circuit 150 includes a high-frequency detection circuit 151 that removes the high-frequency component of the input power (Vin), and a second circuit that outputs the first driving voltage (VC1) by stepping down the input power (Vin). 1 converter 152, a second converter 153 that boosts the input power (Vin) to output the second driving voltage (VC2), and converts the second driving voltage (VC2) to the third driving voltage (VC3) It may include a third converter 154 that outputs.

The high-frequency detection circuit 151 may be comprised of an inductor (L) and a plurality of capacitors (C) connected in parallel between the inductor (L) and the ground, and the configuration of the high-frequency detection circuit 151 may be changed in various ways.

The first converter 152 may be a buck converter that converts the input power (Vin) into the first driving voltage (VC1). The first driving voltage VC1 may be a first buck voltage VCC1 to a third buck voltage VCC3 for driving the timing controller 140 or the data driving circuit 130.

The second converter 153 may be a boost converter that converts the input power (Vin) into the second driving voltage (VC2). The second driving voltage VC2 may be a gate high voltage (VGH) or a gate low voltage (VGL) for driving the gate driving circuit 120.

The third converter 154 may be a converter that converts the second driving voltage VC2 into the third driving voltage VC3. The third driving voltage VC3 may be a high-potential pixel driving voltage (ELVDD) or a low-potential pixel driving voltage (ELVSS) for driving a subpixel.

Here, the output node NN2 of the second converter 153 and the input node NN3 of the third converter 154 are electrically connected, but the output node NN2 of the second converter 153 and the third converter 154 are electrically connected to each other. Since various circuit elements may be located between the input nodes NN3 of (154), electrical characteristics may vary.

As such, the power management circuit 150 uses various types of driving voltages (VC1, VC2, VC3) to drive the display panel 110, timing controller 140, data driving circuit 130, and gate driving circuit 120. ) may include a plurality of converters 152, 153, and 154 for generating.

At this time, noise may occur in the process of switching the plurality of converters 152, 153, and 154 that generate various driving voltages (VC1, VC2, and VC3).

For example, the input node NN1 of the first converter 152, the output node NN2 of the second converter 153, and the input node NN3 of the third converter 154 are the main noise generating nodes. It may correspond to a node. In this case, the input node NN1 of the first converter 152 is the first noise node, the output node NN2 of the second converter 153 is the second noise node, and the input node NN3 of the third converter 154 is connected to the first noise node. ) can be called the third noise node.

For example, the first noise node NN1 may generate a noise signal of 2.2 MHz, and the second noise node NN2 may generate a noise signal of 930 KHz. Additionally, a noise signal of 680 KHz may be generated in the third noise node NN3.

Due to this noise, the driving voltage supplied to the display device 100 may become unstable, and errors in image quality or malfunction of the display device 100 may occur.

In order to solve this problem, the power management circuit of the present disclosure uses a noise cancellation circuit to cancel out noise generated at major nodes and provide a display device capable of stable operation.

FIG. 5 is a diagram showing the configuration of a power management circuit according to embodiments of the present disclosure, and FIG. 6 is a diagram illustrating a noise detection signal applied to the amplifier circuit through a noise detection circuit in the power management circuit according to embodiments of the present disclosure. This is a diagram showing the waveform.

5 and 6, the power management circuit 150 according to embodiments of the present disclosure includes a high-frequency detection circuit 151 that removes the high-frequency component of the input power source Vin, and steps down the input power source Vin. A first converter 152 that outputs a first driving voltage (VC1), a second converter 153 that boosts the input power supply (Vin) and outputs a second driving voltage (VC2), and a second driving voltage (VC2) It may include a third converter 154 that converts and outputs the third driving voltage VC3, and a noise cancellation circuit 155 that detects noise at a main node and generates a noise cancellation signal.

The high-frequency detection circuit 151 may be composed of an inductor (L) and a plurality of capacitors (C), and the configuration of the high-frequency detection circuit 151 may be changed in various ways.

The first converter 152 may be a buck converter that converts the input power Vin to the first driving voltage VC1. The first driving voltage VC1 may be a first buck voltage VCC1 to a third buck voltage VCC3 for driving the timing controller 140 or the data driving circuit 130.

The second converter 153 may be a boost converter that converts the input power (Vin) into the second driving voltage (VC2). The second driving voltage VC2 may be a gate high voltage (VGH) or a gate low voltage (VGL) for driving the gate driving circuit 120.

The third converter 154 may be a converter that converts the second driving voltage VC2 into the third driving voltage VC3. The third driving voltage VC3 may be a high-potential pixel driving voltage (ELVDD) or a low-potential pixel driving voltage (ELVSS) for driving a subpixel.

Here, the output node NN2 of the second converter 153 and the input node NN3 of the third converter 154 are electrically connected, but the output node NN2 of the second converter 153 and the third converter 154 are electrically connected to each other. Since various circuit elements may be located between the input nodes NN3 of (154), electrical characteristics may vary.

The noise cancellation circuit 155 is a noise detection circuit 156 that detects noise generated from the first noise node (NN1), the second noise node (NN2), and the third noise node (NN3) and inverts the detected noise. It may include an amplifier circuit 157 that outputs a noise canceling signal.

The noise detection circuit 156 includes a first resistor (R1) and a first capacitor (C1) connected in series to the first noise node (NN1), and a second resistor (R2) connected in series to the second noise node (NN2). ) and a second capacitor C2, and a third resistor R3 and a third capacitor C3 connected in series to the third noise node NN3.

The first capacitor C1 to the third capacitor C3 serve to remove the direct current component included in the first noise node NN1, the second noise node NN2, and the third noise node NN3, respectively. You can.

Accordingly, as shown in FIG. 6, noise signals occurring in the first noise node (NN1), the second noise node (NN2), and the third noise node (NN3) can be detected respectively according to the frequency component. .

The noise signal detected through the noise detection circuit 156 is transmitted to the amplification circuit 157 through the noise input node (NI).

The voltages of the first noise node (NN1), the second noise node (NN2), and the third noise node (NN3) have different levels. Therefore, to convert the noise signals detected at the first noise node (NN1), the second noise node (NN2), and the third noise node (NN3) to similar levels, the first to third resistors R1 (R3) and the first to third capacitors (C1) to C3 may have different values.

To this end, the first resistor (R1) to the third resistor (R3) may be formed as a variable resistor, or the first capacitor (C1) to the third capacitor (C3) may be formed as a variable capacitor.

The amplifier circuit 157 is an amplifier (AMP) in which the noise signal transmitted through the noise input node (NI) is input to the inverting input terminal, and the instrument ground (M_GND) is connected to the non-inverting input terminal, and the inverter of the amplifier (AMP) It may include a feedback resistor (Rf) connected between the input terminal and the output terminal, and an output resistor (Ro) and an output capacitor (Co) connected to the output terminal of the amplifier (AMP).

The amplifier (AMP) inverts and amplifies the noise signal applied to the inverting input terminal according to the size of the feedback resistor (Rf) and supplies it to the noise output node (NO). That is, the output signal of the amplifier (AMP) supplies a noise cancellation signal to the input node of the high frequency detection circuit 151 through the output resistor (Ro) and the output capacitor (Co). At this time, the noise output node (NO) to which the noise canceling signal is supplied from the noise canceling circuit 155 corresponds to the input node of the high frequency detection circuit 151.

The sizes of the output resistance (Ro) and the output capacitor (Co) may be determined so that the noise canceling signal corresponds to the input power (Vin).

Since the noise cancellation signal has a phase and level opposite to the noise generated by the first converter 152 to third converter 154, the noise generated by the first converter 152 to third converter 154 It can be contradictory. As a result, the first to third driving voltages VC1 to VC3 generated by the power management circuit 150 may be output as stable voltages with noise removed.

Meanwhile, the display device 100 may include an electrical ground (PCB_GND) and a mechanical ground (M_GND). The electrical ground (PCB_GND) is a ground terminal formed on a circuit board on which electrical operation is performed, such as a printed circuit board, and the mechanical ground (M_GND) is a ground terminal placed on a fixture formed on the outside of the display device 100, such as a metal case. am.

In the power management circuit 150 of the present disclosure, the noise cancellation circuit 155 preferably connects the non-inverting input terminal of the amplifier (AMP) to the device ground (M_GND) in order to generate a stable noise cancellation signal.

FIG. 7 is a diagram showing an example of a structure in which the non-inverting input terminal of an amplifier constituting the noise cancellation circuit is connected to the device ground in the power management circuit according to embodiments of the present disclosure.

Referring to FIG. 7, in the power management circuit 150 of the present disclosure, the noise cancellation circuit 155 is a non-inverting input terminal of the amplifier (AMP) for generating a stable noise cancellation signal is connected to the metal case through the ground pad (PAD_G). It can be connected to the device ground (M_GND) formed in the device 300, such as .

For example, the power management circuit 150 may be mounted on a control printed circuit board (CPCB). In this case, the ground pad (PAD_G) coupled to the non-inverting input terminal of the amplifier (AMP) constituting the noise cancellation circuit 155 is not the electrical ground (PCB_GND) formed on the control printed circuit board (CPCB) but the metal case. It is preferable to be directly connected to the device ground (M_GND) formed in the device 300, such as .

The device 300 may be made of a metal material, or may be a case with a built-in control printed circuit board (CPCB) to protect against external shock.

The electrical ground (PCB_GND) formed on the control printed circuit board (CPBC) may exhibit an unstable ground level due to noise that appears during the operation of the control printed circuit board (CPCB).

On the other hand, because the mechanical ground (M_GND) formed in the metal case is formed far away from the control printed circuit board (CPCB), the noise formed in the electrical ground (PCB_GND) by the control printed circuit board (CPCB) is connected to the mechanical ground ( M_GND) is not transmitted.

Therefore, the power management circuit 150 of the present disclosure does not connect the non-inverting input terminal of the amplifier (AMP) included in the noise cancellation circuit 155 to the electrical ground (PCB_GND) formed on the control printed circuit board (CPCB), Noise inflow can be minimized by connecting directly to the mechanical ground (M_GND) formed in the metal case.

For example, the ground pad (PAD_G) coupled to the non-inverting input terminal of the amplifier (AMP) and the instrument ground (M_GND) may be connected with conductive tape.

Alternatively, the ground pad (PAD_G) coupled to the non-inverting input terminal of the amplifier (AMP) and the device ground (M_GND) may be connected through a coupling structure such as a bolt or nut, or may be connected to a protruding structure formed on the non-conductive device 300. It may be connected by

At this time, a ground pad (PAD_G) can be coupled to the non-inverting input terminal of the amplifier (AMP), and in order to facilitate connection with the device ground (M_GND), the ground pad (PAD_G) is placed close to the device ground (M_GND). It would be desirable to form

FIG. 8 is a diagram illustrating example signal waveforms when the amplifier of the noise cancellation circuit is connected to the electrical ground and the device ground in the power management circuit according to embodiments of the present disclosure.

Referring to FIG. 8, in the power management circuit 150 according to embodiments of the present disclosure, the non-inverting input terminal of the amplifier (AMP) constituting the noise cancellation circuit 155 may be connected to the ground.

At this time, the non-inverting input terminal of the amplifier (AMP) constituting the noise cancellation circuit 155 is preferably connected to the device ground (M_GND) of the device 300 on which the control printed circuit board (CPCB) is mounted.

As previously explained, the electrical ground (PCB_GND) formed on the control printed circuit board (CPCB) maintains the ground level, but noise may enter during the operation of the control printed circuit board (CPCB).

Therefore, when the non-inverting input terminal of the amplifier (AMP) constituting the noise canceling circuit 155 is connected to the electrical ground (PCB_GND) formed on the control printed circuit board (CPCB), through the noise canceling circuit 155 The output noise cancellation signal may also include noise.

On the other hand, since the mechanical ground (M_GND) of the device 300 on which the control printed circuit board (CPCB) is mounted is far away from the electrical ground (PCB_GND) of the control printed circuit board (CPCB), Noise generated by operation is hardly transmitted.

Therefore, by directly connecting the non-inverting input terminal of the amplifier (AMP) constituting the noise canceling circuit 155 to the device ground (M_GND) of the device 300, such as a metal case, noise caused by the control printed circuit board (CPCB) It is possible to minimize the inflow and output a noise cancellation signal that can accurately reflect the noise generated in the switching process of the converters 152, 153, and 154.

FIG. 9 is a diagram comparing signal waveforms of a case without a noise cancellation circuit and a case of including a noise cancellation circuit in the display device according to embodiments of the present disclosure.

Referring to FIG. 9, in the display device 100 according to embodiments of the present disclosure, when there is no noise cancellation circuit 155 (400), the first noise node NN1, the second noise node NN2, and Noise signals of different frequencies generated from the third noise node NN3 may be included in the driving signal generated from the power management circuit 150.

On the other hand, when there is a noise canceling circuit 155 according to an embodiment of the present disclosure (500), different noises generated from the first noise node (NN1), the second noise node (NN2), and the third noise node (NN3) are present (500). Since noise signals of different frequencies can be canceled out, the power management circuit 150 can generate a stable driving signal.

The embodiments of the present disclosure described above are briefly described as follows.

The power management circuit 150 of the present disclosure includes a high-frequency detection circuit 151 that removes the high-frequency component of the input power source Vin, and a first converter 152 that steps down the input power source Vin and outputs a first driving voltage. ), a second converter 153 that boosts the input power (Vin) to output a second driving voltage, and a third converter 154 that converts the second driving voltage to output a third driving voltage, It may include a noise cancellation circuit 155 that detects noise signals from a plurality of noise nodes and generates a noise cancellation signal.

The high frequency detection circuit 151 may include an inductor (L) and a plurality of capacitors (C) connected in parallel between the inductor (L) and the ground.

The first converter 152 is a buck converter, and the first driving voltage may be a plurality of buck voltages for driving the timing controller 140 or the data driving circuit 130.

The second converter 153 is a boost converter, and the second driving voltage may be a boost voltage for driving the gate driving circuit 120.

The third converter 154 may output a pixel driving voltage for driving the subpixel SP.

The plurality of noise nodes include a first noise node (NN1) corresponding to the input node of the first converter 152, a second noise node (NN2) corresponding to the output node of the second converter 153, It may include a third noise node NN3 corresponding to the input node of the third converter 154.

The noise cancellation circuit 155 includes a noise detection circuit 156 that detects noise signals from the first noise node (NN1), the second noise node (NN2), and the third noise node (NN3), and It may include an amplifier circuit 157 that inverts the noise signal detected by the noise detection circuit 156 and outputs a noise cancellation signal.

The noise detection circuit 156 includes a first resistor (R1) and a first capacitor (C1) connected in series to the first noise node (NN1), and a second resistor (R1) connected in series to the second noise node (NN2). It may include a resistor (R2) and a second capacitor (C2), and a third resistor (R3) and a third capacitor (C3) connected in series to the third noise node (NN3).

The first resistor (R1) to the third resistor (R3) may be a variable resistor, and the first capacitor (C1) to the third capacitor (C3) may be a variable capacitor.

The amplification circuit 157 includes an amplifier (AMP) through which the noise signal is input to an inverting input terminal and an instrument ground (M_GND) connected to a non-inverting input terminal, and an inverting input terminal and output terminal of the amplifier (AMP). It may include a feedback resistor (Rf) connected therebetween, an output resistor (Ro) and an output capacitor (Co) connected to the output terminal of the amplifier (AMP).

The instrument ground (M_GND) is a ground terminal formed in a metal case, and the non-inverting input terminal of the amplifier (AMP) may be connected to the instrument ground (M_GND) through a ground pad (PAD_G).

The ground pad (PAD_G) may be formed at a location close to the instrument ground (M_GND).

The noise cancellation signal may be supplied to the input node of the high frequency detection circuit 151.

A display device 100 according to embodiments of the present disclosure includes a display panel 110 on which a plurality of gate lines (GL), a plurality of data lines (DL), and a plurality of subpixels (SP) are arranged, and the plurality of A gate driving circuit 120 that supplies a scan signal to the gate line GL, a data driving circuit 130 that converts digital image data into an analog data voltage and supplies it to the plurality of data lines DL, A timing controller 140 that controls the gate driving circuit 120 and the data driving circuit 130, the display panel 110, the gate driving circuit 120, the data driving circuit 130, and It includes a power management circuit 150 that supplies a driving voltage to the timing controller 140, wherein the power management circuit 150 includes a high-frequency detection circuit 151 that removes high-frequency components of the input power Vin, and the input A first converter 152 that outputs a first driving voltage by stepping down the power supply (Vin), a second converter 153 that outputs a second driving voltage by boosting the input power supply (Vin), and the second driving voltage. It may include a third converter 154 that converts the voltage and outputs a third driving voltage, and a noise cancellation circuit 155 that detects noise signals from a plurality of noise nodes and generates a noise cancellation signal.

The above description is merely an illustrative explanation of the technical idea of the present disclosure, and those skilled in the art will be able to make various modifications and variations without departing from the essential characteristics of the present disclosure. In addition, the embodiments disclosed in the present disclosure are not intended to limit the technical idea of the present disclosure, but rather are for explanation, and therefore the scope of the technical idea of the present disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of this disclosure.

100: display device
110: display panel
120: Gate driving circuit
130: data driving circuit
140: Timing controller
150: power management circuit
151: High frequency detection circuit
152, 153, 154: converter circuit
155: Noise cancellation circuit
156: Noise detection circuit
157: Amplification circuit
200: Host system
300: Equipment

Claims (14)

a high-frequency detection circuit that removes high-frequency components of the input power;
a first converter that steps down the input power and outputs a first driving voltage;
a second converter that boosts the input power and outputs a second driving voltage;
a third converter converting the second driving voltage to output a third driving voltage; and
A power management circuit including a noise cancellation circuit that detects noise signals from a plurality of noise nodes and generates a noise cancellation signal.
According to claim 1,
The high frequency detection circuit is
inductor; and
A power management circuit including a plurality of capacitors connected in parallel between the inductor and ground.
According to claim 1,
The first converter is a buck converter,
A power management circuit wherein the first driving voltage is a plurality of buck voltages for driving a timing controller or a data driving circuit.
According to claim 1,
The second converter is a boost converter,
A power management circuit wherein the second driving voltage is a boost voltage for driving a gate driving circuit.
According to claim 1,
The third converter is
A power management circuit that outputs a pixel driving voltage to drive subpixels.
According to claim 1,
The plurality of noise nodes are
a first noise node corresponding to the input node of the first converter;
a second noise node corresponding to the output node of the second converter; and
A power management circuit including a third noise node corresponding to the input node of the third converter.
According to claim 6,
The noise cancellation circuit is
a noise detection circuit that detects the noise signal at the first noise node, the second noise node, and the third noise node; and
A power management circuit including an amplifier circuit that inverts the noise signal detected by the noise detection circuit and outputs a noise cancellation signal.
According to claim 7,
The noise detection circuit is
a first resistor and a first capacitor connected in series to the first noise node;
a second resistor and a second capacitor connected in series to the second noise node; and
A power management circuit including a third resistor and a third capacitor connected in series to the third noise node.
According to claim 8,
The first to third resistors are variable resistors,
A power management circuit wherein the first to third capacitors are variable capacitors.
According to claim 7,
The amplifier circuit is
an amplifier to which the noise signal is input to an inverting input terminal, and an instrument ground is connected to a non-inverting input terminal;
a feedback resistor connected between the inverting input terminal and the output terminal of the amplifier; and
A power management circuit including an output resistor and an output capacitor connected to the output terminal of the amplifier.
According to item 10 above,
The device ground is a ground terminal formed in the metal case,
A power management circuit wherein the non-inverting input terminal of the amplifier is connected to the device ground through a ground pad.
According to item 11 above,
The ground pad is
A power management circuit formed at a location close to the device ground.
According to item 1 above,
The noise cancellation signal is
A power management circuit supplied to the input node of the high frequency detection circuit.
A display panel including a plurality of gate lines, a plurality of data lines, and a plurality of subpixels;
a gate driving circuit that supplies scan signals to the plurality of gate lines;
a data driving circuit that converts digital image data into analog data voltage and supplies it to the plurality of data lines;
a timing controller that controls the gate driving circuit and the data driving circuit; and
A power management circuit that supplies a driving voltage to the display panel, the gate driving circuit, the data driving circuit, and the timing controller,
The power management circuit is
a high-frequency detection circuit that removes high-frequency components of the input power;
a first converter that steps down the input power and outputs a first driving voltage;
a second converter that boosts the input power and outputs a second driving voltage;
a third converter converting the second driving voltage to output a third driving voltage; and
A display device including a noise cancellation circuit that detects noise signals from a plurality of noise nodes and generates a noise cancellation signal.

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