KR20240041121A - A regulator with digital feedback control and event-driven method - Google Patents

Abstract

A method of operating a Digital Low Dropout Regulator (DLDO) according to an embodiment of the present invention includes the steps of extracting an output voltage from a PMOS array including a plurality of PMOS and transferring the extracted voltage to a Window ADC; The Window ADC determines whether the delivered voltage is within a preset voltage range, generates a clock signal based on the determination result, and transmits the voltage to a PID (Proportional Integral Derivative control) Controller; The PID Controller calculates an optimal PID gain value by inputting the voltage and target voltage into a preset Fuzzy Logic; The PID controller calculates a Correct value by applying the calculated optimal PID gain value to PID operation; and the PID controller transmitting the Correct value to the PMOS array to adjust the voltage output from the PMOS array. may include.

Description

Regulator with digital feedback control and event-driven method {A regulator with digital feedback control and event-driven method}

The present invention relates to a Digital Low Dropout Regulator (DLDO) applying the Auto Tuning PID type digital feedback control and Event Driven type.

Recently, wearable devices are required to be lightweight and have faster wireless communication. As a result, physical size and weight design constraints were created, which directly led to battery size and capacity limitations. As a result, the need for low-power circuits that consume less current in limited power sources is gradually increasing.

Additionally, existing fixed tuning controller circuits are unable to change or adapt quickly to various environments and variables, resulting in slow processing speed. In particular, the response speed of the existing analog LDO (Low Dropout Regulator) is reduced when it receives low supply power, which leads to a decrease in the performance of the entire module due to factors such as external noise. In addition, the existing DLDO operates even at low supply power by using a shift register or PI structure. There was a problem that the clock's current consumption was large. Additionally, there was a problem that fixed parameter values could not always be maintained in an optimal state due to various devices or environmental variables. To solve this problem, it is necessary to introduce a circuit that has a fast response speed and can operate at low power.

In order to solve the problems of the prior art as described above, this specification adopts a digital circuit to solve problems arising from a smaller size and lower power supply, and minimizes power consumption by minimizing the power used to drive the clock. We would like to propose DLDO with improved battery performance. Additionally, the purpose is to propose a DLDO that can actively respond to changes in power consumption according to various external environmental variables and device performance.

A method of operating a Digital Low Dropout Regulator (DLDO) according to an embodiment of the present invention includes the steps of extracting an output voltage from a PMOS array including a plurality of PMOS and transferring the extracted voltage to a Window ADC; The Window ADC determines whether the delivered voltage is within a preset voltage range, generates a clock signal based on the determination result, and transmits the voltage to a PID (Proportional Integral Derivative control) Controller; The PID Controller calculates an optimal PID gain value by inputting the voltage and target voltage into a preset Fuzzy Logic; The PID controller calculates a Correct value by applying the calculated optimal PID gain value to PID operation; and the PID controller transmitting the Correct value to the PMOS array to adjust the voltage output from the PMOS array. may include.

According to an embodiment of the present invention, the power supply is stable and the battery life is increased, so the function of a wearable device that requires constant power can be stably improved. In addition, since it is composed of digital, it can reduce the weight and area compared to the existing LDO (possible to make it lighter), so it can be effectively applied to manufacturing small and light wearable devices.

In addition, according to one embodiment of the present invention, the use of a dynamic PID controller has the effect of maintaining an accurate output voltage while showing a good effect on latency.

Additionally, according to one embodiment of the present invention, the ripple of the output voltage is reduced because limit cycle oscillation (LCO) that occurs in the steady-state does not occur.

In addition, according to an embodiment of the present invention, the rate of change in power consumption can be detected according to external environmental variables and the state of the device, and the gain value can be actively changed according to the detected change, resulting in faster and more stable power supply. There is.

Figure 1 is a block diagram of a Fully Synthesizable high-speed response Event Driven DLDO through Dynamic PID control according to an embodiment of the present invention.
Figure 2 is a block diagram of a PID Controller according to an embodiment of the present invention.
Figure 3 is a Fuzzy Logic block diagram according to an embodiment of the present invention.
Figure 4 is a flowchart illustrating the Fuzzy algorithm of Fuzzy Logic according to an embodiment of the present invention.
Figure 5 is a diagram schematically illustrating the inference engine steps according to an embodiment of the present invention.
Figure 6 shows the schematic of a Window ADC according to an embodiment of the present invention.
Figure 7 is a circuit layout of DLDO applying Auto Tuning PID type digital feedback control and Event driven method.

The detailed description of the present invention described below refers to the accompanying drawings, which show by way of example specific embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different from one another but are not necessarily mutually exclusive. For example, specific shapes, structures and characteristics described herein with respect to one embodiment may be implemented in other embodiments without departing from the spirit and scope of the invention. Additionally, it should be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the invention. Accordingly, the detailed description that follows is not intended to be taken in a limiting sense, and the scope of the invention is limited only by the appended claims, together with all equivalents to what those claims assert, if properly described. Similar reference numbers in the drawings refer to identical or similar functions across various aspects.

Hereinafter, in order to enable those skilled in the art to easily practice the present invention, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

According to the conventional DLDO technology, only limited control values were output using fixed parameters as a digital LDO using PI and Shift Register. In this specification, to solve this problem, we will use the Fuzzy Algorithm method, which is the basic theory of machine learning, to find the optimal gain value depending on the situation. More specifically, the Fuzzy Block, in which the Fuzzy Algorithm is implemented, can receive the error value and the rate of change of the error output from the comparator, and then determine the matrix value by the internal parameter value based on this. Matrix values can be classified into any one of five states/Levels according to preset rules within the Fuzzy Algorithm, and the Fuzzy Block can output parameter values corresponding to the classified states/Levels. The parameter values output from the Fuzzy Block are transmitted to the PID controller, and the PID controller can apply an active PID compensator for automatic voltage regulation based on the received parameter values. As a result, the DLDO according to an embodiment of the present invention exhibits good latency efficiency while maintaining an accurate output voltage.

In addition, the present invention prevents meaningless power loss from occurring compared to the conventional DLDO by introducing a Window ADC that efficiently generates a clock (i.e., generates an event) according to changes in self-triggering and load current, and increases the voltage value. It additionally includes an Event-Driven type detector (Window ADC in this specification) that re-generates the clock when it deviates and stops the clock when a specific condition is achieved.

The DLDO proposed in this specification is an integrated designed circuit with fast transient response, clock control, and power management modules, and can be used in the form of a low-power SoC (System on Chip) for wearable devices. DLDO can be configured to include a dynamic gain controller for control, a Window ADC Event detector for clock control, and an ADC and/or PMOS Array for digital detection. A more detailed description of DLDO will be provided below with reference to each drawing.

Figure 1 is a block diagram of a Fully Synthesizable high-speed response Event Driven DLDO through Dynamic PID control according to an embodiment of the present invention.

Referring to Figure 1, the Event Driven DLDO (hereinafter referred to as 'DLDO) 100 proposed in this specification includes a MUX (101), a PID Controller module (102), a Window ADC (103), a Divider (104), and a SOC Generator ( 105), Test Serializer (106), FLASHA (107), and/or PMOS Array (108), and the connection/operation relationship and input/output signals between each component are as shown in this figure.

It is difficult for Analog LDO to operate at the NTV (Near Threshold Voltage) low voltage required in low-power modules and to scale its size according to the process. On the other hand, the DLDO (100) proposed in this specification adopts a DVFS structure that can operate under NTV conditions, can be configured as a digital circuit, and size scaling for each process is possible accordingly, so SoC integration with MCU is possible. It has advantages.

In addition, we propose a structure that enables faster and more stable compensation using a PID method that combines fuzzy logic rather than general PID compensation and shift-resistor logic-based output voltage regulation.

Figure 2 is a PID Controller module block diagram according to an embodiment of the present invention. More specifically, Figure 2 shows the Dynamic PID Digital Controller module and shows Fast Settling Time implementation using the Gain Control Algorithm.

Referring to FIG. 2, the PID controller module 102 is configured to include a Fuzzy logic tuner (201), MUX (204), Fuzzy PID Controller (205), FSM and/or Derivative logic that perform a preset Fuzzy Algorithm. You can. The connection/operation relationship and input/output signals between each component are as shown in this drawing.

To implement Dynamic Gain Control, the optimal Settling Time and Stability K_(P, I, D) (i.e. K_p (propagate gain), K_i (integrate gain), and K_d (derivate gain)) can be obtained through Matlab. Fast settling time is realized by minimizing the calculation process, and overshoot and undershoot can be minimized through periodic gain updates. Additionally, the proposed Dynamic Gain Control can improve stability and settling time compared to the Fixed Gain Control method.

In addition, PID Gain Control is implemented as an external control device, and the load condition can be determined through the error value and the differential value of the error between the current voltage (or voltage delivered from Window ADC) and the target voltage. Heavy, Moderate, and Light can be determined with a K_(P, I, D) set with a limited decision range, and the optimal K_(P, I, D) determined according to the Stability Figure of Merit previously determined in Matlab is input to the PID. /may be applied. PID with optimal K_(P, I, D) can control the PMOS array to reach the target voltage more quickly and efficiently.

Figure 3 is a Fuzzy Logic block diagram according to an embodiment of the present invention.

Referring to FIG. 3, Fuzzy Logic (301) may be comprised of a Fuzzy logic tuner (201), Fuzzy PID controller (205), and Process (303). The parameters of the Fuzzy Algorithm according to Fuzzy Logic (301) can be automatically adjusted using the Fuzzy logic tuner (201). The input to the fuzzy logic tuner (201) is the error value (e(t)) and the differential of the error (e(t)) between the voltage (y(t)) received from the Window ADC and the target voltage (r(t)). It is a value, and the output to the Fuzzy PID controller (205) may be ΔKp, ΔKi, and ΔKd as illustrated in this figure. Because the parameters change according to the rate of change of the error value, the target voltage can be reached more quickly.

FIG. 4 is a flowchart illustrating the Fuzzy algorithm of Fuzzy Logic according to an embodiment of the present invention, and FIG. 5 is a diagram illustrating the inference engine steps according to an embodiment of the present invention.

Referring to Figure 4, the Fuzzy Algorithm can be comprised of three major steps: Fuzzification (S401), Inference Engine (S402), and Defuzzification (S403).

First, the first step, the fuzzification step (S401), is a step in which initial input values (Crisp input) are converted into individual fuzzy input values according to preset fuzzy rules. Here, the initial input value (Crisp input) is the error value (e(t)) between the voltage (y(t)) received from the Window ADC and the target voltage (r(t)) and the differential value of the error (e(t)). It may apply to

Next, the second step, the inference engine step (S402), corresponds to the step of inferring the result using the input value obtained in the previous process. For example, as shown in FIG. 5, it is possible to determine to which level the fuzzy input value is classified by the fuzzy rule. There may be a total of 5 levels, and the 5 levels may include Negative Big (NB), Negative small (NS), Zero error (ZE), Positive small (PS), and Positive big (PB).

Lastly, the third step, the Defuzzification step (S403), corresponds to the step of defuzzifying (i.e., decrypting) the fuzzy output value inferred according to the Fuzzy rule into the result of Crisp. Depending on the performance of step 3 (S401 to S403), the change values for each gain, ΔKp, ΔKi, and ΔKd, can be output as result values.

Fuzzy PID controller can perform PID operation using at least one of the ΔKp, ΔKi, and ΔKd values, which are the gain changes received from Fuzzy Logic, and calculate/obtain the correct value. The correct value corresponds to a value that corrects the current voltage value so that the voltage value (i.e., the current voltage value) received from the window ADC reaches the target voltage value (or the error value becomes 0).

The correct value calculated/obtained in this way can be input to the PMOS Array, and in the PMOS Array, a plurality of PMOSs included in a specific group among the plurality of groups described above are turned on based on the input correct value, thereby displaying the correct value. The corrected voltage can be extracted.

PMOSs in a PMOS array can be divided into multiple groups, and each group can have a certain number of PMOSs. For example, there may be 2k-1 PMOS in the K group, so the first group has 1 PMOS, the second group has 2 PMOS, the third group has 4 PMOS,... There may be 128 PMOS in the 8th group.

Specifically, initially, all PMOS in the PMOS array may correspond to an off state, and the voltage output from the PMOS array may correspond to '0'. If an event is generated because the voltage does not fall within the preset range, a correct value can be generated from the PID compensator and input into the PMOS array.

Next, in the PMOS Array, a plurality of PMOS included in a specific group in the PMOS Array can be changed to the on state to correspond to the correct value. For example, assuming that correct[7:0] is 10010110, the value would correspond to 2 ⁷ +2 ⁴ +2 ² +2 ¹ .

The PMOS may be changed to the on state to correspond to 10010110, and the PMOSs included in the second group, third group, fifth group, and seventh group may be changed to the on state (the rest remain in the off state). Ultimately, the on/off state of the PMOS can be adjusted in the PMOS array so that a voltage corresponding to the correct value is output, and the adjusted voltage can be output accordingly.

As above, in the DLDO of the present invention, the output voltage can be detected and adjusted to correspond to the target voltage in the PID controller, and the adjusted voltage can be output from the PMOS array. As this process is repeated, accurate output voltage can be maintained while showing good efficiency in latency.

Figure 6 shows the schematic of a Window ADC according to an embodiment of the present invention.

Referring to FIG. 6, if the Vin value is less than VREFH, the COMP_N value is output as 0, and if the Vin value is greater than the VREFL value, the COMP_P value is output as 0. If the Vin value is between these two values (VREFL, VREFH), 0 is output through the OR gate, which is input to the CLK gating part and always outputs 0 through the And gate output, turning the clock OFF. In other words, Window ADC does not generate events (clock signal generation event, voltage regulation event) if the current voltage exists between VREFL and VREFH (i.e., the voltage is greater than or equal to VREFL and less than or equal to VREFH). An event can be generated if the current voltage is less than VREFL or greater than VREFH.

Therefore, the voltage range between VREFL and VREFH is in a stable state, and if the voltage output from the PMOS Array is included in the above voltage range, the output voltage of DLDO is in a stable state (i.e., corresponding to the target voltage range) and must be added separately. No action or event will occur.

Conversely, if the voltage range between VREFL and VREFH is outside, it is an unstable state, and the Window ADC can initiate the operation of the PID controller by generating a clock signal.

Window ADC can reduce power consumption by temporarily stopping the clock when the current voltage is in a stable state within the preset voltage range (between VREFL and VREFH) and no events are generated. Of course, if the voltage changes depending on external input, etc., the clock can be generated again. This can be effective in reducing weight and improving battery performance, which are required for wearable devices.

Figure 7 is a circuit layout of DLDO applying Auto Tuning PID type digital feedback control and Event driven method.

Referring to FIG. 7, the DLDO may be configured to include at least one of an ADC block (103), Dynamic PID Controller module (102), PMOS Array (108), and Cap Array (701), and can be configured to suit the characteristics of the wearable device. It can be manufactured in SoC form with a small size/weight. For example, the die area is 1,800um horizontally and 1,200um vertically. For example, the area of each block is 180x180 (um)^2 for the Dynamic PID controller module 102, 390x435 (um)^2 for the ADC, and 400x135 (um)^2 for the PMOS Array.

Claims (6)

In the operation method of DLDO (Digital Low Dropout Regulator),
A PMOS array containing a plurality of PMOS extracts an output voltage and transmits the extracted voltage to the Window ADC;
The Window ADC determines whether the delivered voltage is within a preset voltage range, generates a clock signal based on the determination result, and transmits the voltage to a PID (Proportional Integral Derivative control) Controller;
The PID Controller calculates an optimal PID gain value by inputting the voltage and target voltage into a preset Fuzzy Logic;
The PID controller calculates a Correct value by applying the calculated optimal PID gain value to PID operation; and
The PID controller transmits the Correct value to the PMOS array to adjust the voltage output from the PMOS array; DLDO operation method, including. According to claim 1,
In the step of calculating the PID Gain value, the Fuzzy Logic is:
receiving an error value and a differential value of the error between the voltage and the target voltage;
Converting the error value and the differential value of the error into a Fuzzy input value according to a preset Fuzzy rule;
Classifying the fuzzy input value into one of preset levels according to the fuzzy rule;
Calculating the PID Gain value by defuzzifying the classified steps with the result of Crisp according to the Fuzzy rule; DLDO operation method, including. According to claim 2,
The preset level includes Negative Big (NB), Negative small (NS), Zero error (ZE), Positive small (PS), and Positive big (PB). According to claim 2,
The PID Gain value is,
A method of operating DLDO that corresponds to at least one of the change in Kp (propagate gain) value, the change in Ki (integrate gain) value, and the change in Kd (derivate gain) value. According to claim 1,
The PMOS Array is divided into a plurality of groups, and with the number of PMOS in the K group being 2k-1,
turning on, in the PMOS array, a plurality of PMOS included in a specific group based on the correct value transmitted from the PID controller; A method of operating DLDO, further comprising: In the DLDO (Digital Low Dropout Regulator) device,
PMOS Array, which includes a plurality of PMOS and extracts the output voltage and transfers it to the Window ADC;
A Window ADC that determines whether the received voltage is within a preset voltage range, generates a clock signal based on the determination result, and transmits the voltage to a PID (Proportional Integral Derivative control) Controller; and
Input the voltage and target voltage into the preset Fuzzy Logic to calculate the optimal PID Gain value, apply the calculated optimal PID Gain value to PID operation to calculate the Correct value, and transmit the Correct value to the PMOS Array. PID Controller, which controls the voltage output from the PMOS Array; DLDO device, including.