KR20240034750A - 감소된 임피던스 기판 - Google Patents

감소된 임피던스 기판 Download PDF

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Publication number
KR20240034750A
KR20240034750A KR1020247000604A KR20247000604A KR20240034750A KR 20240034750 A KR20240034750 A KR 20240034750A KR 1020247000604 A KR1020247000604 A KR 1020247000604A KR 20247000604 A KR20247000604 A KR 20247000604A KR 20240034750 A KR20240034750 A KR 20240034750A
Authority
KR
South Korea
Prior art keywords
substrate
metal layer
clause
micrometers
conductive channels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
KR1020247000604A
Other languages
English (en)
Korean (ko)
Inventor
아니켓 파틸
조안 레이 빌라르바 부오트
홍복 위
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20240034750A publication Critical patent/KR20240034750A/ko
Pending legal-status Critical Current

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Classifications

    • H01L23/49827—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H01L23/49838—
    • H01L23/53209—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0253—Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427—Power or ground buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H10W42/261—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their shapes or dispositions
    • H10W42/267—Patterned shielding planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10159—Memory
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/823—Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
KR1020247000604A 2021-07-14 2022-06-14 감소된 임피던스 기판 Pending KR20240034750A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/375,676 US20230018448A1 (en) 2021-07-14 2021-07-14 Reduced impedance substrate
US17/375,676 2021-07-14
PCT/US2022/072935 WO2023288164A1 (en) 2021-07-14 2022-06-14 Reduced impedance substrate

Publications (1)

Publication Number Publication Date
KR20240034750A true KR20240034750A (ko) 2024-03-14

Family

ID=82547141

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020247000604A Pending KR20240034750A (ko) 2021-07-14 2022-06-14 감소된 임피던스 기판

Country Status (7)

Country Link
US (1) US20230018448A1 (https=)
EP (1) EP4371154A1 (https=)
JP (1) JP2024526566A (https=)
KR (1) KR20240034750A (https=)
CN (1) CN117546289A (https=)
TW (1) TW202306083A (https=)
WO (1) WO2023288164A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102021214258A1 (de) 2021-12-13 2023-06-15 Volkswagen Aktiengesellschaft Wärmepumpenkaskade und Verfahren zur Erwärmung oder Abkühlung eines Kühlmittels mittels einer Wärmepumpenkaskade
CN120109110B (zh) * 2025-05-09 2025-08-29 合肥晶合集成电路股份有限公司 金属叠层结构及其制备方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101086520B1 (ko) * 2003-06-20 2011-11-23 엔엑스피 비 브이 전자 장치, 조립체 및 전자 장치 제조 방법
TWI286916B (en) * 2004-10-18 2007-09-11 Via Tech Inc Circuit structure
TWI242889B (en) * 2004-10-20 2005-11-01 Advanced Semiconductor Eng Integrated capacitor on packaging substrate
CN101305448B (zh) * 2005-11-08 2012-05-23 Nxp股份有限公司 电容器装置、宽带系统、电子部件及电容器的制造方法
US8067840B2 (en) * 2006-06-20 2011-11-29 Nxp B.V. Power amplifier assembly
KR20090078287A (ko) * 2008-01-14 2009-07-17 삼성전자주식회사 전기기기
KR101044203B1 (ko) * 2009-11-18 2011-06-29 삼성전기주식회사 전자기 밴드갭 구조물 및 이를 포함하는 인쇄회로기판
US8436477B2 (en) * 2011-10-03 2013-05-07 Invensas Corporation Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
US9131602B2 (en) * 2012-02-24 2015-09-08 Mediatek Inc. Printed circuit board for mobile platforms
US20140124124A1 (en) * 2012-11-08 2014-05-08 Boardtek Electronics Corporation Printed circuit board manufacturing method
US9349788B2 (en) * 2013-08-08 2016-05-24 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Thin film capacitors embedded in polymer dielectric
MY204695A (en) * 2017-12-30 2024-09-10 Intel Corp Zero-misalignment two-via structures using photoimageable dielectric, buildup film, and electrolytic plating
US10586844B2 (en) * 2018-01-23 2020-03-10 Texas Instruments Incorporated Integrated trench capacitor formed in an epitaxial layer
US11637057B2 (en) * 2019-01-07 2023-04-25 Qualcomm Incorporated Uniform via pad structure having covered traces between partially covered pads
US11955436B2 (en) * 2019-04-24 2024-04-09 Intel Corporation Self-equalized and self-crosstalk-compensated 3D transmission line architecture with array of periodic bumps for high-speed single-ended signal transmission
US12402331B2 (en) * 2021-02-09 2025-08-26 Intel Corporation Decoupling capacitors based on dummy through-silicon-via plates

Also Published As

Publication number Publication date
EP4371154A1 (en) 2024-05-22
CN117546289A (zh) 2024-02-09
JP2024526566A (ja) 2024-07-19
WO2023288164A1 (en) 2023-01-19
US20230018448A1 (en) 2023-01-19
TW202306083A (zh) 2023-02-01

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Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
D18-X000 Deferred examination requested

St.27 status event code: A-1-2-D10-D18-exm-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000