KR20240031882A - Non-silcon semiconductor complementary thin film transistor, manufacturing method thereof and pixel structure including the complementary thin film transistor - Google Patents

Abstract

A complementary thin film transistor is disclosed. The complementary thin film transistor includes a substrate; and a first thin film transistor and a second thin film transistor disposed on the substrate, wherein the first conductive semiconductor layer of the first thin film transistor and the second gate electrode layer of the second thin film transistor are disposed on the same layer and are the same. It is characterized by being a material.

Description

Non-silicon semiconductor complementary thin film transistor, manufacturing method thereof, and pixel structure including the complementary thin film transistor

The present invention relates to a field effect transistor, and more specifically to a complementary thin film transistor (TFT).

Complementary transistors and circuit configurations utilizing them are usually based on silicon semiconductor technology. Silicon semiconductor processes can be divided into single crystalline silicon semiconductor processes and amorphous and poly-crystalline silicon semiconductor processes.

Since the single-crystal silicon semiconductor process is a process that is carried out at a higher process temperature than the polycrystalline silicon semiconductor process, a complementary TFT is manufactured using a substrate (e.g., a silicon wafer) with a high heat resistance temperature. That is, in the single crystal silicon semiconductor process, there is a disadvantage that it is difficult to manufacture a complementary TFT using a substrate with a low heat resistance temperature, such as a glass or plastic substrate.

Additionally, various complementary integrated circuits including complementary TFTs made through this silicon semiconductor process have hard substrates and cannot be bent or folded flexibly. Therefore, in order to make a bendable or foldable electronic device, additional post-processing is required to transfer the fabricated complementary integrated circuit to a glass or plastic substrate. Therefore, there is a disadvantage that the total number of processes and costs increase.

In the case of the polycrystalline silicon semiconductor process, the process temperature is lower than that of the single-crystal silicon semiconductor process, but crystallization is required to change the amorphous silicon (a-Si) thin film into a polycrystalline silicon thin film, and N-type and P Since a mold doping process is required, the disadvantage is that the number of processes is still large.

The present invention to solve the above-mentioned problems is a complementary TFT structure that can be manufactured on a substrate with a low heat resistance temperature without an N-type and P-type doping process using a non-silicon semiconductor and can greatly reduce the number of steps, and a method for manufacturing the same. The purpose is to provide.

As a complementary TFT according to one aspect of the present invention for achieving the above-described object, a complementary thin film transistor is disclosed. The complementary thin film transistor includes a substrate; and a first thin film transistor and a second thin film transistor disposed on the substrate, wherein the first conductive semiconductor layer of the first thin film transistor and the second gate electrode layer of the second thin film transistor are disposed on the same layer and are the same. It is characterized by being a material.

A method of manufacturing a complementary thin film transistor according to another aspect of the present invention includes simultaneously forming a first conductive semiconductor layer of the first thin film transistor and a second gate electrode layer of the second thin film transistor on a substrate; forming a gate insulating film on the first conductive semiconductor layer and the second gate electrode layer; A first gate electrode layer, a first source electrode layer, and a first drain electrode layer of the first thin film transistor are formed on the gate insulating film, and at the same time, a second source electrode layer and a second drain electrode layer of the second thin film transistor are formed on the gate insulating film. and forming a metal pad connected to the second gate electrode layer. and forming a second conductive semiconductor layer electrically connected to the second source electrode layer and the second drain electrode layer, wherein the second gate electrode layer and the first conductive semiconductor layer are one thin film. do.

A display pixel circuit according to another aspect of the present invention includes a substrate, a switch thin film transistor structure and a driving thin film transistor structure disposed on the substrate, a passivation layer covering the switch thin film transistor structure and the driving thin film transistor structure, and on the passivation layer. A pixel electrode layer disposed and electrically connected to the source electrode layer of the driving thin film transistor through a contact hole formed in the passivation layer, and an OLED layer disposed on the pixel electrode layer, and the conductivity of the switch thin film transistor structure The semiconductor layer and the gate electrode layer of the driving thin film transistor structure are disposed on the same layer and are made of the same material.

In an embodiment, when the conductive semiconductor layer is an n-type semiconductor layer, the material of the gate electrode layer is the same as the material of the n-type semiconductor layer, and when the conductive semiconductor layer is a p-type semiconductor layer, the material of the gate electrode layer is the same. is the same as the material of the p-type semiconductor layer.

In an embodiment, the conductive semiconductor layer is a channel layer that is not doped with impurities.

In an embodiment, the conductive semiconductor layer and the gate electrode layer are formed simultaneously through one process.

According to the present invention, by manufacturing a complementary TFT using a non-silicon semiconductor capable of low-temperature processing using a substrate with a low heat resistance temperature, such as a glass or plastic substrate, the complementary TFT can be manufactured even in a low-temperature process.

In addition, by forming the first conductive semiconductor layer of the first TFT and the gate electrode of the second TFT in the same layer and made of the same material, the first conductive semiconductor layer of the first conductive TFT and the gate electrode of the second conductive TFT can be formed in the same process without a doping process. The electrodes can be formed simultaneously, thereby reducing the total number of manufacturing processes for complementary TFTs.

Figure 1 is a cross-sectional view showing the structure of a complementary thin film transistor (hereinafter referred to as complementary TFT) according to an embodiment of the present invention.
Figures 2 to 5 are layouts for explaining the manufacturing method of the complementary TFT shown in Figure 1.
FIG. 6 is an equivalent circuit diagram of a CMOS inverter including the complementary TFT shown in FIGS. 1 and 5.
FIG. 7 is a layout of the CMOS inverter shown in FIG. 6.
FIG. 8 is an equivalent circuit diagram of a single pixel including the complementary TFT shown in FIGS. 1 and 5 in a display backplane according to an embodiment of the present invention, and FIG. 9 is a cross-sectional view showing the structure of the single pixel shown in FIG. 8.
FIGS. 10 to 15 are layouts for explaining the manufacturing method of the single pixel shown in FIGS. 8 and 9.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. In order to facilitate overall understanding when describing the present invention, the same reference numerals are used for the same components in the drawings, and duplicate descriptions for the same components are omitted.

The terms used herein are only used to describe specific embodiments and are not intended to limit the invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, terms such as “comprise” or “have” are intended to designate the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but are not intended to indicate the presence of one or more other features. It should be understood that this does not exclude in advance the possibility of the existence or addition of elements, numbers, steps, operations, components, parts, or combinations thereof.

1 is a cross-sectional view showing the structure of a complementary TFT according to an embodiment of the present invention.

Referring to FIG. 1, a complementary TFT according to an embodiment of the present invention includes a substrate 110 and a first TFT 10 and a second TFT 20 disposed on the substrate 110.

The substrate 110 may be a non-silicon substrate having a low heat resistance temperature. Therefore, the complementary TFT according to an embodiment of the present invention can be manufactured at a low process temperature. The non-silicon substrate may be, for example, a glass or plastic substrate. The material of the glass substrate may be, for example, quartz or sapphire.

A complementary TFT according to an embodiment of the present invention includes a conductive semiconductor layer (hereinafter referred to as ‘first conductive semiconductor layer’) of the first TFT 10 and a gate electrode layer (hereinafter referred to as ‘first conductive semiconductor layer’) of the second TFT 20. The 'second gate electrode layer') is disposed on the same layer and is made of the same material. For example, the material of the gate electrode layer of the second TFT (20) is the same as the material of the conductive semiconductor layer of the first TFT (10). By doing this, the conductive semiconductor layer of the first TFT 10 and the gate electrode layer of the second TFT 20 can be formed simultaneously in one process (e.g., deposition process), reducing the number of total manufacturing processes and process time. can be shortened.

Specifically, the first TFT 10 includes a gate insulating film 140 disposed on the first conductive semiconductor layer 120 located on the same layer as the second gate electrode layer 130 of the second TFT 20. , a first source electrode layer 151 and a first drain electrode layer 152 disposed on the gate insulating film 140 and electrically connected to the first conductive semiconductor layer 120, and the first source electrode layer ( 151) and a first gate electrode layer 153 located on the same layer as the first drain electrode layer 152 and disposed between the first source electrode layer 151 and the first drain electrode layer 152.

The first conductive semiconductor layer 120 may be an n-type semiconductor layer or a p-type semiconductor layer. When the first conductive semiconductor layer 120 is the n-type semiconductor layer, the second gate electrode layer is made of the same material as the n-type semiconductor layer, and the first conductive semiconductor layer 120 is the p-type semiconductor layer. In this case, the second gate electrode layer 130 is made of the same material as the p-type semiconductor layer. In this embodiment, it is assumed that the first conductive semiconductor layer 120 is the n-type semiconductor layer. Accordingly, it is assumed that the second conductive semiconductor layer 160 of the second TFT 20, which will be described later, is a p-type semiconductor layer.

The gate insulating layer 140 has a first contact hole. The first contact hole includes two contact holes 142 and 144. The contact hole 142 serves to electrically connect the n-type semiconductor layer 120 and the first source electrode layer 151, and the other contact hole 144 serves to electrically connect the n-type semiconductor layer 120 and the first source electrode layer 151. It serves to electrically connect the first drain electrode layer 152.

The second TFT 20 is disposed on the gate insulating film 140, which is disposed on the second gate electrode layer 130 located on the same layer as the n-type semiconductor layer 120. The second source electrode layer 154 and the second drain electrode layer 155 are located on the same layer as the second source electrode layer 154 and the second drain electrode layer 155 and are electrically connected to the second gate electrode layer 130. a metal pad (156 in FIGS. 4 and 5), and the p-type semiconductor layer 160, a second conductive semiconductor layer, in contact with the second source electrode layer 154 and the second drain electrode layer 155. ) includes.

Although not shown in FIG. 1, the metal pad (156 in FIGS. 4 and 5) is electrically connected to the second gate electrode layer 130 through the second contact hole (146 in FIG. 3) patterned in the gate insulating film 140. It is connected to

Figures 2 to 5 are layouts for explaining the manufacturing method of the complementary TFT shown in Figure 1.

Referring to FIG. 2, first, the n-type semiconductor layer 120 (first conductive semiconductor layer) of the first TFT 10 and the second gate electrode layer of the second TFT 20 are placed on the substrate 110. (130) is formed.

In an embodiment, the n-type semiconductor layer 120 and the second gate electrode layer 130 are formed simultaneously in the same layer through one deposition process. Here, the deposition process includes, for example, chemical vapor deposition (CVD) and physical vapor deposition (PVD). Before the deposition process, a photolithography process may be further performed to pattern the positions of the n-type semiconductor layer 120 and the second gate electrode layer 130 on the substrate 110.

The n-type semiconductor layer 120 serves as a channel layer that is not doped with the n-type dopant of the first TFT 10. Therefore, in this embodiment, the doping process of doping the n-type semiconductor layer 120 with an n-type dopant to form the channel layer of the first TFT 10 can be omitted. Omitting this doping process can reduce the number of processes and process time. Additionally, by simultaneously forming the n-type semiconductor layer 120 and the second gate electrode layer 130 through one deposition process, the number of processes and process time can be further reduced.

The material of the second gate electrode layer 130 is the same as that of the n-type semiconductor layer 120. When the n-type semiconductor layer 120 of the first TFT 10 is a p-type semiconductor layer, the material of the second gate electrode layer 130 is the same as that of the p-type semiconductor layer.

In an embodiment, the n-type semiconductor layer is made of a zinc oxide (ZnO)-based material, an indium oxide (InO)-based material, a tin oxide (SnO)-based material, and titanium oxide. (Titanium oxide, TiO) series materials, indium-gallium-zinc oxide (InGaZnO) series materials, manganese-tin-indium oxide (manganese-tin-indium oxide, ZnSnInO) series materials, Any one of indium tin oxide (InSnO) series materials and a combination containing at least two of these materials may be used.

In an embodiment, the material of the p-type semiconductor layer is a tellurium (Te) series material, a tellurium oxide (TeO _x ) series material, a selenium (Se) series material, and copper oxide. (Copper oxide, CuO) series materials, tin oxide (SnO) series materials, nickel oxide (Nickel Oxide, NiO _x ) series materials, and combinations containing at least two of these materials. It can be used.

Next, referring to FIG. 3, the gate insulating film 140 is formed to cover the n-type semiconductor layer 120 (first conductive semiconductor layer) and the second gate electrode layer 130 over the entire surface of the substrate 110. After that, the gate insulating film 140 is patterned to form first contact holes 142 and 144 on the n-type semiconductor layer 120, and a second contact hole (142) is formed on the second gate electrode layer 130. The process of forming 146) proceeds.

To facilitate understanding of the drawing, the gate insulating layer 140 is not shown in FIG. 3 . The first contact holes 142 and 144 include two contact holes 142 and 144, and the contact hole 142 connects the n-type semiconductor layer 120 and the first source electrode layer 151. It serves to connect, and the other contact hole 144 serves to connect the n-type semiconductor layer 120 and the first drain electrode layer 152.

To form the first contact holes 142 and 144 and the second contact hole 146 in the gate insulating layer 140, a photolithography process and an etching process may be used. The etching process includes, for example, dry etching and/or wet etching.

Next, referring to FIG. 4, the first source electrode layer 151 and the first drain electrode layer 152 are formed to partially overlap the n-type semiconductor layer 120 with the gate insulating film 140 interposed therebetween. And at the same time, a process of forming the first gate electrode layer 153 across the n-type semiconductor layer 120 is performed between the first source electrode layer 151 and the first drain electrode layer 152. In this way, the first TFT 10 is completed.

In addition, the second source electrode layer 154 and the second drain electrode layer 155, which partially overlap the second gate electrode layer 130, are formed on the gate insulating film 140, and at the same time, the gate insulating film 140 ) A process of forming a metal pad 156 that partially overlaps the second gate electrode layer 130 is performed.

The first source electrode layer 151, the first drain electrode layer 152, the first gate electrode layer 153, the second source electrode layer 154, the second drain electrode layer 155, and the metal pad 156. ) may be made of the same metal material and are formed simultaneously through one deposition process. Here, the deposition process includes, for example, the CVD and the PVD.

The first source electrode layer 151 and the first drain electrode layer 152 are electrically connected to the n-type semiconductor layer 120 through first contact holes (142 and 144 in FIGS. 1 and 3), and the metal The pad 156 is electrically connected to the second gate electrode layer 130 through the second contact hole 146.

Next, referring to FIG. 5, the surface of the gate insulating film 140 (not shown in FIG. 5) between the second source electrode layer 154 and the second drain electrode layer 155 and the second source electrode layer 154 ) and a process of forming the p-type semiconductor layer 160 (the second conductive semiconductor layer) on a partial surface of the second drain electrode layer 155 is performed. Accordingly, the p-type semiconductor layer 160 is electrically connected to the second source electrode layer 154 and the second drain electrode layer 155.

The p-type semiconductor layer 160 serves as a channel layer of the second TFT 20 that is not doped with p-type dopant. Therefore, in this embodiment, the doping process of doping the p-type semiconductor layer 120 with an n-type dopant to form the channel layer of the second TFT 20 can be omitted. Omitting this doping process can reduce the number of processes and process time.

As described above, the complementary TFT according to an embodiment of the present invention adopts a non-silicon substrate with a low heat resistance temperature, such as a glass substrate such as quartz or sapphire, instead of a silicon substrate (silicon wafer) with a conventional high heat resistance temperature. , complementary TFTs can be manufactured even at low processing temperatures.

In addition, the first conductive semiconductor layer 120 of the first TFT 10 and the second gate electrode layer 130 of the second TFT 20 are formed in the same layer and made of the same material, so that the doping process is performed in the same process. The first conductive semiconductor layer 120 of the first TFT 10 and the second gate electrode layer 130 of the second TFT 20 can be formed at the same time, thereby reducing the total number of manufacturing processes for the complementary TFT. It can be reduced.

The complementary TFT according to an embodiment of the present invention includes a CMOS (Complementary Metal Oxide Semiconductor) inverter, a CMOS logic circuit including a CMOS NAND circuit, a COMS NOR circuit, a CMOS AND circuit, and a CMOS OR circuit, and a CMOS ALU (Arithmetic Logic Unit). , can be used in the design of various application circuits such as CMOS microprocessors, CMOS RFID TAG circuits, CMOS image sensors, energy harvester circuits, and display pixel circuits.

FIG. 6 is an equivalent circuit diagram of a CMOS inverter including the complementary TFT shown in FIGS. 1 and 5, and FIG. 7 is a layout of the CMOS inverter shown in FIG. 6.

Referring to Figures 6 and 7, the CMOS inverter according to an embodiment of the present invention includes a substrate 210 and a third TFT 30 and a fourth TFT 40 disposed on the substrate 210.

The substrate 210 may be a non-silicon substrate having a low heat resistance temperature. The non-silicon substrate may be, for example, a glass or plastic substrate. The material of the glass substrate may be, for example, quartz or sapphire.

In the CMOS inverter according to an embodiment of the present invention, the conductive semiconductor layer 220 of the third TFT 30 and the gate electrode layer 230 of the fourth TFT 40 are disposed on the same layer and made of the same material. . For example, the gate electrode layer 230 of the fourth TFT 40 is made of the same material as the conductive semiconductor layer 220.

Accordingly, the conductive semiconductor layer 220 of the third TFT 30 and the gate electrode layer 230 of the fourth TFT 40 can be formed simultaneously in one process (e.g., deposition process), and the CMOS inverter The total number of processes can be reduced.

Specifically, the third TFT 30 includes a gate insulating film (not shown in FIG. 6) disposed on the first conductive semiconductor layer 220 located on the same layer as the second gate electrode layer 230, and the gate. It includes a first source electrode layer 251 and a first drain electrode layer 252 disposed on an insulating film and electrically connected to the first conductive semiconductor layer 120, wherein the first source electrode layer 251 and the first It includes a first gate electrode layer 253 located on the same layer as the drain electrode layer 252 and disposed between the first source electrode layer 251 and the first drain electrode layer 252.

The first conductive semiconductor layer 220 may be an n-type semiconductor layer or a p-type semiconductor layer. When the first conductive semiconductor layer 220 is the n-type semiconductor layer, the second gate electrode layer 230 is made of the same material as the n-type semiconductor layer, and the first conductive semiconductor layer 220 is the p-type semiconductor layer. In the case of a semiconductor layer, the second gate electrode layer 230 is made of the same material as the p-type semiconductor layer.

Although not shown in FIG. 7, the gate insulating layer (140 in FIG. 1) has the first contact holes (142 and 144 in FIG. 1). One contact hole (142 in FIG. 1) serves to electrically connect the first conductive semiconductor layer 220 and the first source electrode layer 251, and another contact hole (144 in FIG. 1) serves to electrically connect the first conductive semiconductor layer 220 and the first source electrode layer 251. 1 It serves to electrically connect the conductive semiconductor layer 220 and the first drain electrode layer 252.

The third TFT 40 includes the gate insulating film disposed on the second gate electrode layer 230 located on the same layer as the first conductive semiconductor layer 220, and the second source electrode layer disposed on the gate insulating film ( 254) and the second drain electrode layer 255, and a metal pad 256 located on the same layer as the second source electrode layer 254 and the second drain electrode layer 255 and electrically connected to the second gate electrode layer 230. ), and a second conductive semiconductor layer 260 electrically connected to the second source electrode layer 254 and the second drain electrode layer 255.

The metal pad 256 is electrically connected to the second gate electrode layer 230 through a second contact hole (146 in FIG. 3) patterned in the gate insulating film.

In an embodiment of the present invention, the first drain electrode layer 252 is electrically connected to the second source electrode layer 254. That is, the first drain electrode layer 252 and the source electrode layer 254 are composed of one electrode layer. Additionally, the first gate electrode layer 253 is electrically connected to the metal pad 256. That is, the first gate electrode layer 253 and the metal pad 256 are composed of one electrode layer. In addition, the first gate electrode layer 253 and the metal pad 256 composed of one electrode layer serve as input terminals for receiving input signals, and the first drain electrode layer 252 composed of one electrode layer and the The source electrode layer 254 serves as an output terminal that outputs an output signal. And, the first source electrode layer 251 is connected to ground. Accordingly, a CMOS inverter is configured.

FIG. 8 is an equivalent circuit diagram of a single pixel including the complementary TFT shown in FIGS. 1 and 5 in a display backplane according to an embodiment of the present invention, and FIG. 9 is a cross-sectional view showing the structure of the single pixel shown in FIG. 8.

First, referring to FIG. 8, a single pixel has a gate line (GL), a data line (DL), a power line (PL), a switch TFT 50, and a driving line. ) TFT (60), a storage capacitor (70), and an Organic Light Emitting Diode (OLED) (70).

The gate line GL intersects the data line and the power line, and applies a gate voltage to the switch TF 50 to control the switching operation of the switch TFT 50.

The data line DL applies a data voltage (source voltage or pixel voltage) to the switch TFT 50. That is, the data line DL applies a data voltage to the unit pixel.

The power line PL continuously applies a power voltage VDD to the driving TFT 60 and the storage capacitor 70 for one frame time.

The switch TFT 50 controls the path between the data line DL and the gate electrode of the driving TFT 60. This switch TFT 50 has the same structure as the first TFT 10 of the complementary TFT shown in FIGS. 1 and 5.

The driving TFT 60 controls the amount of current flowing through the OLED 80 according to a switching operation based on the data voltage transmitted through the switch TFT 50 and the capacitor voltage of the storage capacitor 70. This driving TFT 60 has the same structure as the second TFT 20 of the complementary TFT shown in FIGS. 1 and 5.

The storage capacitor 70 maintains the power voltage (or programmed gate voltage) applied through the power line PL during the one frame time.

The OLED (80) emits light according to the amount of current controlled by the driving TFT (60).

Since the present invention is characterized by the operation of the above components included in a single pixel, the detailed description thereof is replaced with a description of the already well-known OLED pixel circuit.

Hereinafter, the structure of the single pixel shown in FIG. 8 will be described in detail. In FIG. 9 , some of the components shown in FIG. 8 are omitted to simplify the drawing. For example, in FIG. 9 , the structures of the gate line (GL), data line (DL), power line (PL), and storage capacitor 70 shown in FIG. 8 are not shown.

Referring to FIG. 9, a single pixel includes a substrate 310, the switch TFT 50 and the driving TFT 60 disposed on the substrate 310, and in addition, the driving TFT 60 and It includes an OLED layer that is electrically connected.

The substrate 310 is a non-silicon substrate with a low heat resistance temperature, and may be, for example, a glass substrate made of quartz or sapphire.

The switch TFT 50 includes a first conductive semiconductor layer 321 disposed on the substrate 310, a gate insulating film 330 disposed on the first conductive semiconductor layer 321, and the gate insulating film A first source electrode layer 341, a first drain electrode layer 342 disposed on (330), and a first gate electrode layer 343 disposed between the first source electrode layer 341 and the first drain electrode layer 342. ) further includes. Here, the first source electrode layer 341, the first drain electrode layer 342, and the first gate electrode layer 343 are disposed on the same layer. The first conductive semiconductor layer 321 serves as a channel layer and is electrically connected to the first source electrode layer 341 and the first drain electrode layer 342 through two contact holes 301 and 302.

The driving TFT 60 includes a second gate electrode layer 322 disposed on the substrate 310, and the gate insulating layer 330 disposed on the second gate electrode layer 322. The gate insulating layer 330 ) further includes a second source electrode layer 344 and a second drain electrode layer 345 disposed on the. In addition, the driving TFT 60 is disposed between the second source electrode layer 344 and the second drain electrode layer 345, and is located at one end of the second source electrode layer 344 and the second drain electrode layer 345. It further includes a second conductive semiconductor layer 350 in contact with .

In an embodiment, the first conductive semiconductor layer 321 of the switch TFT 50 and the second gate electrode layer 322 of the drive TFT 60 are disposed on the same layer and made of the same material. do. Therefore, the first conductive semiconductor layer 321 and the second gate electrode layer 322 can be formed simultaneously in one process (e.g., deposition process), and the number of processes and process time for the display pixel are reduced. can do.

In an embodiment, the first conductive semiconductor layer 321 is a channel layer of the switch TFT 50 and may be an n-type semiconductor layer or a p-type semiconductor layer. The second conductive semiconductor layer 350 is a channel layer of the driving TFT 60. When the first conductive semiconductor layer 321 is the n-type semiconductor layer, the second conductive semiconductor layer 350 is the p-type semiconductor layer, and in the opposite case, it is the n-type semiconductor layer.

In an embodiment, when the first conductive semiconductor layer 321 is the n-type semiconductor layer, the second gate electrode layer 322 of the driving TFT 60 is made of the same material as the n-type semiconductor layer. When the first conductive semiconductor layer 321 is the p-type semiconductor layer, the second gate electrode layer 322 of the driving TFT 60 is made of the same material as the p-type semiconductor layer.

In an embodiment, the first conductive semiconductor layer 321 is not doped with a first conductivity type dopant, and the second conductive semiconductor layer 350 is also not doped with a second conductivity type dopant. Therefore, in the present invention, the doping process can be omitted, and the number of processes and process time can be further reduced.

The single pixel includes a passivation layer 360 that protects the switch TFT 50 and the driving TFT 60, a pixel electrode layer 370 disposed on the passivation layer 360, and a pixel electrode layer 370. ) is disposed on the surface of the OLED (70) and further includes an encapsulation layer (380) that protects the OLED (70). The pixel electrode layer 370 is electrically connected to the second source electrode layer 344 of the driving TFT 60 through the contact hole 303 patterned in the passivation layer 360.

Figures 10 to 15 are layouts for explaining the manufacturing method of the single pixel shown in Figures 8 and 9.

First, referring to FIG. 10, first, on the prepared substrate 310, a first conductive semiconductor layer 321 of the switch TFT 50, a second gate electrode layer 322 of the drive TFT 60, and a first conductive semiconductor layer 321 of the switch TFT 50 are formed. A process of simultaneously forming the first bridge layer 323, the second bridge layer 324, and the bottom electrode layer 325 of the storage capacitor (70 in Figure 70) is performed. To form these (321-325) simultaneously, the above deposition process can be used. The deposition processes include, for example, photolithography, PVD and CVD.

The first bridge layer 323 is located below the gate line (GL in FIG. 8) at the intersection point (A in FIG. 8) of the gate line (GL in FIG. 8) and the data line (DL in FIG. 8). It serves as a partial path for the data line (DL) passing through. The second bridge layer 323 is the power line (GL) passing through the lower part of the gate line (GL in FIG. 8) at the intersection point (B in FIG. 8) of the gate line (GL) and the power line (PL). PL) serves as a part of the pathway.

In an embodiment, the first conductive semiconductor layer 321, the second gate electrode layer 322, the first bridge layer 323, the second bridge layer 324, and the bottom electrode layer 325A. may be made of the same material. For example, the second gate electrode layer 322, the first bridge layer 323, the second bridge layer 324, and the bottom electrode layer 325A are made of the material of the first conductive semiconductor layer 321. It can be done.

In an embodiment, when the first conductive semiconductor layer 321 is the n-type semiconductor layer, the components 322 to 325 are made of a material of the n-type semiconductor layer. Materials of the n-type semiconductor layer include, for example, zinc oxide (ZnO)-based materials, indium oxide (InO)-based materials, tin oxide (SnO)-based materials, and titanium oxide. (Titanium oxide, TiO) series materials, indium-gallium-zinc oxide (InGaZnO) series materials, manganese-tin-indium oxide (manganese-tin-indium oxide, ZnSnInO) series materials, Any one of indium tin oxide (InSnO) series materials and a combination containing at least two of these materials may be used.

In an embodiment, when the first conductive semiconductor layer 321 is the p-type semiconductor layer, the components 322 to 325 are made of a material of the p-type semiconductor layer. Materials of the p-type semiconductor layer include, for example, tellurium (Te)-based materials, tellurium oxide (TeO _x )-based materials, selenium (Se)-based materials, and copper oxide. (Copper oxide, CuO) series materials, tin oxide (SnO) series materials, nickel oxide (Nickel Oxide, NiO _x ) series materials, and combinations containing at least two of these materials. It can be used.

Next, referring to FIG. 11, after forming the gate insulating film (330 in FIG. 9) on the entire surface of the substrate 310, the gate insulating film (330 in FIG. 9) on the components 321 to 325 is patterned. Thus, the process of forming the contact holes 301 to 308 proceeds.

The contact holes 301 to 308 include the components 321 to 325A and target metal layers disposed on top of the components 321 to 325A (341, 342, 343, 344, 345 in FIG. 12, It serves as a passage to electrically connect 346, 325B, DL, PL). To form these contact holes 301 to 308, the etching process may be used. For example, photolithography, dry etching, and/or wet etching may be used.

Next, referring to FIG. 12, on the gate insulating film 360, the first source electrode layer 341 of the switch TFT 50, the first drain electrode layer 342 of the switch TFT 50, and the switch The first gate electrode layer 343 of the TFT 50, the second source electrode layer 344 of the driving TFT 60, the second drain electrode layer 345 of the driving TFT 60, and the driving TFT 60. ) of the metal pad layer 346, the top electrode layer 325B of the storage capacitor (70 in FIG. 8), the data line DL, and the power line PL are performed.

Specifically, the first source electrode layer 341 and the first drain electrode layer 342 are formed to be electrically connected to the first conductive semiconductor layer 321 formed below through contact holes 301 and 302. The first gate electrode layer 343 formed between the first source electrode layer 341 and the first drain electrode layer 342 is formed to be electrically connected to the gate line GL. The second drain electrode layer 345 is formed to be electrically connected to the power line PL. The metal pad layer 346 is formed to be electrically connected to the first drain electrode layer 342. The data line DL is formed to be electrically connected to the first bridge layer 323 formed below through the contact holes 304 and 305. Accordingly, the data line DL has a path passing under the gate line GL. The power line PL is formed to be electrically connected to the second bridge layer 324 formed below through the contact holes 306 and 307. Accordingly, the power line PL has a path passing under the gate line GL.

The components 341, 342, 343, 344, 345, 346, 325B, DL, and PL may be formed simultaneously through one process. For this purpose, photolithography processes, deposition processes, etc. may be used.

Next, referring to FIG. 13, a process of forming the second conductive semiconductor layer 350 in contact with the second source electrode layer 344 and the second drain electrode layer 345 is performed. Accordingly, the driving TFT 60 is completed. To form the second conductive semiconductor layer 350, photolithography and deposition processes may be used. The second conductive semiconductor layer 350, like the first conductive semiconductor layer 321, is a layer that is not doped with a second conductive dopant. Therefore, the doping process may be omitted in the display pixel manufacturing process according to an embodiment of the present invention.

Next, referring to FIG. 14, after forming a passivation layer (360 in FIG. 9) over the entire surface of the substrate 310 to protect the switch TFT 50 and the driving TFT 60, the passivation layer A process of patterning 360 to form a contact hole 309 is performed. To form the passivation layer 360, a PVD and/or CVD deposition process may be used, and to form the contact hole 309, an etching process including dry and/or wet etching may be used. .

Next, referring to FIG. 15, a pixel electrode layer 370 and an OLED electrically connected to the second source electrode layer 344 of the driving TFT 60 through the contact hole 309 on the passivation layer 360. After sequentially forming the stack 70, a process of forming an encapsulation layer 380 covering the OLED stack 70 is performed. The encapsulation layer 380 serves to protect the OLED stack 70. The pixel electrode layer 370, the OLED stack 70, and the encapsulation layer 380 may be formed through photolithography and deposition processes.

A single pixel is completed by forming the encapsulation layer 380. When these single pixels are organized into a pixel array, they become a display backplane.

Although the present invention has been described above with reference to preferred embodiments, those skilled in the art can make various modifications and changes to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. You will understand that it is possible.

Claims (15)

Board; and
Comprising a first thin film transistor and a second thin film transistor disposed on the substrate,
A complementary thin film transistor, wherein the first conductive semiconductor layer of the first thin film transistor and the second gate electrode layer of the second thin film transistor are disposed on the same layer and made of the same material. In paragraph 1:
The first thin film transistor,
a gate insulating film disposed on the first conductive semiconductor layer made of the same material as the second gate electrode layer;
a first source electrode layer and a first drain electrode layer disposed on the gate insulating layer and electrically connected to the first conductive semiconductor layer through a first contact hole patterned in the gate insulating layer; and
A first gate electrode layer disposed between the first source electrode layer and the first drain electrode layer.
A complementary thin film transistor containing a. In paragraph 1
The second thin film transistor,
a gate insulating film disposed on the second gate electrode layer made of the same material as the first conductive semiconductor layer;
a second source electrode layer and a second drain electrode layer disposed on the gate insulating layer;
a metal pad located on the same layer as the second source electrode layer and the second drain electrode layer and electrically connected to the second gate electrode layer; and
A second conductive semiconductor layer disposed on the second source electrode layer and the second drain electrode layer.
A complementary thin film transistor containing a. In paragraph 1:
The substrate is a non-silicon substrate with a low heat resistance temperature,
A complementary thin film transistor wherein the non-silicon substrate is a glass substrate. In paragraph 1:
The first conductive semiconductor layer is an n-type semiconductor layer or a p-type semiconductor layer,
When the first conductive semiconductor layer is the n-type semiconductor layer, the second gate electrode layer is made of the same material as the n-type semiconductor layer,
When the first conductive semiconductor layer is the p-type semiconductor layer, the second gate electrode layer is a complementary thin film transistor made of the same material as the p-type semiconductor layer. In paragraph 5,
The n-type semiconductor layer is made of a zinc oxide (ZnO) series material, an indium oxide (InO) series material, a tin oxide (SnO) series material, and a titanium oxide (TiO) series material. Material, indium-gallium-zinc oxide (InGaZnO) series material, manganese-tin-indium oxide (ZnSnInO) series material, indium tin oxide (indium tin) oxide, InSnO) series of materials and combinations containing at least two of these materials,
The p-type semiconductor layer is made of a tellurium (Te) series material, a tellurium oxide (TeO _x ) series material, a selenium (Se) series material, and a copper oxide (CuO) series material. A complementary thin film transistor that is any one of a tin oxide (SnO) series material, a nickel oxide (NiO _x ) series material, and a combination containing at least two of these materials. In paragraph 1:
The substrate, the first thin film transistor, and the second thin film transistor,
CMOS inverter, CMOS NAND circuit, COMS NOR circuit, CMOS logic circuit including CMOS AND circuit and CMOS OR circuit, CMOS ALU, CMOS microprocessor, CMOS RFID TAG circuit, CMOS image sensor and display pixels. Complementary thin film transistor included in the circuit. In a method of manufacturing a complementary thin film transistor including a first thin film transistor and a second thin film transistor,
forming a first conductive semiconductor layer of the first thin film transistor and a second gate electrode layer of the second thin film transistor on a substrate;
forming a gate insulating film on the first conductive semiconductor layer and the second gate electrode layer;
A first gate electrode layer, a first source electrode layer, and a first drain electrode layer of the first thin film transistor are formed on the gate insulating film, and at the same time, a second source electrode layer and a second drain electrode layer of the second thin film transistor are formed on the gate insulating film. and forming a metal pad connected to the second gate electrode layer. and
Forming a second conductive semiconductor layer electrically connected to the second source electrode layer and the second drain electrode layer,
A method of manufacturing a complementary thin film transistor, wherein the first conductive semiconductor layer and the second gate electrode layer are made of the same material. In paragraph 8:
The step of forming the first conductive semiconductor layer of the first thin film transistor and the second gate electrode layer of the second thin film transistor,
A method of manufacturing a complementary thin film transistor, which includes simultaneously forming the first conductive semiconductor layer and the second gate electrode layer in the same layer through one deposition process. In paragraph 8:
The first conductive semiconductor layer is an n-type semiconductor layer or a p-type semiconductor layer,
When the first conductive semiconductor layer is the n-type semiconductor layer, the material of the second gate electrode layer is the same as the material of the n-type semiconductor layer,
When the first conductive semiconductor layer is the p-type semiconductor layer, the second gate electrode layer is made of the same material as the p-type semiconductor layer. In paragraph 8:
The substrate is a non-silicon substrate with a low heat resistance temperature,
A method of manufacturing a complementary thin film transistor, wherein the non-silicon substrate is a glass substrate made of quartz or sapphire. Board; and
a switch thin film transistor structure and a driving thin film transistor structure disposed on the substrate;
A passivation layer covering the switch thin film transistor structure and the driving thin film transistor structure;
a pixel electrode layer disposed on the passivation layer and electrically connected to the source electrode layer of the driving thin film transistor through a contact hole formed in the passivation layer; and
Comprising an OLED layer disposed on the pixel electrode layer,
A single pixel structure, wherein the conductive semiconductor layer of the switch thin film transistor structure and the gate electrode layer of the driving thin film transistor structure are disposed on the same layer and made of the same material. In paragraph 12:
When the conductive semiconductor layer is an n-type semiconductor layer, the material of the gate electrode layer is the same as that of the n-type semiconductor layer,
When the conductive semiconductor layer is a p-type semiconductor layer, the material of the gate electrode layer is the same as the material of the p-type semiconductor layer. In paragraph 12:
A single pixel structure wherein the conductive semiconductor layer is a channel layer that is not doped with impurities. In paragraph 12:
A single pixel structure wherein the conductive semiconductor layer and the gate electrode layer are formed simultaneously through one process.

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