KR20240028697A - Semiconductor Memory Device Having ECC Circuit and Test Method Thereof - Google Patents

Abstract

A semiconductor memory device including an ECC circuit capable of determining memory defects using an ECC test mode and a test method using the same are disclosed. This can reduce the memory burden and simplify the device configuration because defective and good products can be judged by comparing the addresses of defective words with error bits using the ECC test mode of the ECC circuit. In addition, by using the ECC pattern test unit and ECC bypass test unit in ECC test mode, it is possible to determine defective and good products by comparing only the addresses of defective words, thereby significantly shortening the test time.

Description

Semiconductor memory device having ECC circuit and test method using same {Semiconductor Memory Device Having ECC Circuit and Test Method Thereof}

The present invention relates to a semiconductor memory device including an ECC circuit and a test method using the same. More specifically, a semiconductor memory device including an ECC circuit capable of determining memory defects using an ECC test mode and a test using the same. It's about method.

After manufacturing a semiconductor memory device, tests are performed to select defective memory cells. Accurately detecting memory cells with such subtle defects during the test stage of a memory device is an important factor in the reliability of the memory device.

As one of the methods of detecting such defective cells and improving the yield of the memory device, an error check and correction (ECC) circuit with an error check and correction function is provided in the semiconductor memory device.

The ECC circuit allows the controller to detect and correct single or more bit errors per N-bit memory word.

Generally, if a single bit per word is corrected, it is called 1-bit ECC, if two bits are corrected, it is called 2-bit ECC, then 3-bit ECC, etc. For example, 2-bit ECC operates normally because if there are two error bits in a word, both error bits are corrected, but if there are three or more bits, the word is treated as defective. Additionally, 1-bit ECC operates normally because it corrects one error bit if there is one error bit in the word, but if there are two or more error bits, the word is treated as defective.

Therefore, from the user's perspective, in a 2-bit ECC device, 2-bit defects among words operate normally, but for reasons such as quality improvement, samples with words containing 2-bit defects are treated as defective, and samples with 1-bit defects or less per word are treated as defective. A test method that treats only good products as good is considered.

On the other hand, if the test program for selecting defective memory cells needs to count error bits per word, time to count error bits and a separate memory capable of counting are required. In other words, in order to count error bits, a memory that records and stores the address of the defective cell is required.

However, when testing numerous words in a semiconductor memory device, the time to count error bits and the burden on the memory increase. For example, a memory device containing 64 bits per word contains 15,625 words per 1M. For example, assuming that the error bits are 100,000 bits, all of them must be recorded, which requires a lot of test time and memory.

Korean registered patent 10-1912372

The technical problem to be achieved by the present invention is to provide a semiconductor memory device including an ECC circuit that can determine defective and good products by comparing the addresses of defective words with error bits using the ECC test mode of the ECC circuit, and a test method using the same. It is provided.

A semiconductor memory device including an ECC circuit of the present invention for achieving the above-described problem includes a memory cell array including M bits (M is a positive integer) in one word among a plurality of words connected to the cell array, and An N-bit ECC circuit detects and corrects error bits of N-bits (N=2) or less of a memory cell array, wherein the ECC circuit compares the address of a bad word with an error bit to determine a normal state or a bad state. Includes an ECC test mode to determine.

The ECC test mode includes an ECC pattern test unit that records bits in the first state or second state in all of the M bits, reads them, and determines a normal state or a defective state; An ECC bypass test unit that records and reads the bits of the second state to determine a normal state or a defective state, extracts the address of the word corresponding to the defective state, and compares the extracted addresses to determine the final normal state or defective state. It may include an address comparison unit that determines.

The operation of the ECC bypass test unit may be performed on words determined to be in a normal state by the ECC pattern test unit.

The ECC pattern test unit records and reads the first state bits in all of the M bits, and determines a final defective state when more than (N-1) error bits are detected; and It may include a second state pattern mode in which bits of the second state are written and read in all of the M bits, and when more than (N-1) error bits are detected, a final defective state is determined.

The operation of the second state pattern mode may be performed on words determined to be normal in the first state pattern mode.

The ECC bypass test unit writes and reads the first state bits in all of the M bits, determines a first defect when one or more error bits are detected, and addresses the word corresponding to the first defect. A first state bypass mode for extracting a first word address, writing and reading bits of the second state in all of the M bits, determining a second defect when one or more error bits are detected, and determining the second defect It may include a second state bypass mode for extracting a second word address, which is the address of the word corresponding to .

The operation of the second state bypass mode may be performed on the word determined as the first defect in the first state bypass mode.

The address comparison unit may determine a final normal state and a final defective state by comparing the first word address and the second word address.

The address comparison unit may determine a final defective state if the first word address and the second word address correspond to the same word.

A test method for a semiconductor memory device including an ECC circuit of the present invention to achieve the above-described problem is to test N-bits (N=2) from a memory cell array containing M bits (M is a positive integer) in one word. ) Executing an ECC test mode using an N-bit ECC circuit that detects and corrects the following error bits, and operating the ECC test mode to compare addresses of bad words with error bits to determine whether the memory cell array is normal. and executing an ECC test mode to determine a good or bad condition.

The step of using the ECC test mode includes recording first-state or second-state bits in all of the M bits using an ECC pattern test unit and reading them to determine a normal state or a defective state, the ECC pattern test. For a word determined to be in a normal state in the unit, the ECC bypass test unit writes and reads bits in the first state or the second state in all of the M bits to determine the normal state or the defective state, and determines the defective state. It may include extracting the address of a word corresponding to the state and comparing the extracted addresses with an address comparison unit to determine the final normal state or defective state.

The step of using the ECC pattern test unit includes recording and reading the first state bits in all of the M bits, and determining a final defect when more than (N-1) error bits are detected. performing a mode, and performing a second state pattern mode in which bits of the second state are written and read in all of the M bits, and when more than (N-1) error bits are detected, a final defect is determined. It may include steps.

The step of using the ECC bypass test unit includes writing and reading bits in the first state in all of the M bits, determining a first defect if one or more error bits are detected, and writing a word corresponding to the first defect. performing a first state bypass mode for extracting a first word address that is an address of and writing and reading bits of the second state in all of the M bits, and detecting one or more error bits as a second defect. It may include performing a second state bypass mode of determining and extracting a second word address, which is the address of the word corresponding to the second defect.

The comparing using the address comparison unit may include comparing the first word address and the second word address to determine a final normal state and a final defective state.

In the step of comparing with the address comparison unit, the address comparison unit may determine a final defective state if the first word address and the second word address correspond to the same word, and determine a normal state if the first word address and the second word address correspond to different words. .

According to the present invention described above, defective and good products can be determined by comparing the addresses of defective words with error bits using the ECC test mode of the ECC circuit, thereby reducing the memory burden and simplifying the configuration of the device. there is.

In addition, by using the ECC pattern test unit and ECC bypass test unit in ECC test mode, it is possible to determine defective and good products by comparing only the addresses of defective words, thereby significantly shortening the test time.

The technical effects of the present invention are not limited to those mentioned above, and other technical effects not mentioned will be clearly understood by those skilled in the art from the description below.

1 is a block diagram showing a semiconductor memory device of the present invention.
Figure 2 is a diagram showing an example of applying an error detection pattern to detect an error bit.
Figure 3 is a diagram showing the ECC test mode of the present invention.
Figure 4 is a flowchart briefly showing the test method of the ECC test mode of the present invention.
FIG. 5 is a flow chart showing the test method shown in FIG. 4.
FIG. 6 is a diagram illustrating the test method shown in FIG. 4.
Figure 7 is a diagram showing an example of determining a defect using the (N-1) ECC test mode of the present invention.
Figure 8 is a diagram showing another example of determining defects using the (N-1) ECC test mode of the present invention.

Since the present invention can be subject to various changes and have various forms, specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, and should be understood to include all changes, equivalents, and substitutes included in the spirit and technical scope of the present invention. While describing each drawing, similar reference numerals are used for similar components.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the technical field to which the present invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and unless explicitly defined in the present application, should not be interpreted in an ideal or excessively formal sense. No.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings.

1 is a block diagram showing a semiconductor memory device of the present invention.

Referring to FIG. 1, the semiconductor memory device 100 of the present invention may be any device including a memory for storing input data and using the stored data as output data. For example, a system-on-chip (SoC) such as an application processor (AP), Dynamic Random Access Memory (DRAM), Magnetoresistive Random Access Memory (MRAM), flash memory, etc., according to external commands. It may be a memory system that stores input data and outputs output data according to a host's request, such as a semiconductor memory device that stores input data and outputs output data, a solid state drive (SSD), or a memory card.

Additionally, the semiconductor memory device 100 of the present invention may include a memory cell array 110, a memory controller 120, and an ECC circuit 130.

The memory cell array 110 may include a plurality of memory cells (not shown) each disposed in areas where a plurality of first signal lines and a plurality of second signal lines intersect. For example, the first signal lines may be bit lines, and the second signal lines may be word lines. Additionally, each of the plurality of memory cells may be a single level cell (SLC) that stores one bit, or a multi-level cell (MLC) that can store at least 2 bits of data. there is.

For example, among a plurality of words, one word may include M bits (M is a positive integer). That is, each of the plurality of words can be connected to M cells.

The memory controller 120 reads data stored in the memory cell array 110 in response to a write/read request from the host, or operates the memory cell array 110 to write data to the memory cell array 110. can be controlled. Specifically, the memory controller may control program (or write), read, and erase operations for the memory cell array 110 by providing addresses, commands, and control signals to the memory cell array 110. Additionally, data to be written and read data may be transmitted and received between the memory controller 120 and the memory cell array 110.

Although not shown, the memory controller may include RAM, a host interface, and a memory interface. RAM can be used as the operating memory of the processor. The processor can control the overall operation of the memory controller. The host interface may include a protocol for exchanging data between the host and the memory controller. As an example, the memory controller supports at least one of various interface protocols such as USB, MMC, PCI-E, ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI, ESDI, and IDE (Integrated Drive Electronics). It can be configured to communicate with the outside (HOST) through.

Additionally, the memory controller 120 may include an Error Correction Code (ECC) circuit 130. The ECC circuit 130 may perform error detection and correction operations on read data from the memory cell array 110.

The ECC circuit 130 can detect and correct error bits included in each of a plurality of words, and can have a correctable error amount. For example, when the ECC circuit 130 has 2-bit ECC, the ECC circuit 130 detects and corrects errors of 2-bit or less included in the received data, such as 1-bit errors and 2-bit errors. You can. That is, more than a 3-bit error can be treated as a defect. Additionally, when the ECC circuit 130 has 1-bit ECC, the ECC circuit 130 can only detect and correct errors of 1-bit or less, so errors of 2-bit or more can be treated as defects.

When the ECC circuit 130 has a correctable error amount of N-bits (N is a positive integer), the ECC circuit 130 may be referred to as ‘N-bit ECC’. For example, in a word containing M bits, N-bit ECC can detect and correct N errors per word. That is, out of M bits, there can be N correctable bits.

As described above, from the user's perspective, a 2-bit ECC device can detect and correct 1-bit errors and 2-bit errors, so it is possible to have a memory device that operates normally for 2-bit errors or less in a word. For reasons such as improving the quality of the device, an ECC test method may be considered in which samples with words containing 2-bit defects are treated as defective, and only samples with 1-bit defects or less per word are treated as good products.

Additionally, if all error bits in the memory cell array must be counted in an ECC test program to select defective memory cells, the time and memory burden for counting error bits increases.

Figure 2 is a diagram showing an example of applying an error detection pattern to detect an error bit.

Referring to FIG. 2, assuming that a word consisting of 8 bits has 2 error bits, a plurality of error pattern modes must be performed to determine the 2 error bits.

At this time, when a high bit ('1' bit) is recorded and the high bit is read, a defect in which the high bit cannot be recorded or read is referred to as a 'high-defect', and a low bit ( When a '0' bit) is written and a row bit is read, a defect in which the row bit cannot be written or read is referred to as a 'row-defect'.

As shown in Figure 2, assuming that among the words consisting of 8 bits, there is a high-defective (0_struck) in the 1st cell and a low-defective (1_stuck) in the 8th cell, '0' is present in all 8 bits. In the '00' error pattern mode, which writes and reads bits, and the 'FF' error pattern mode, which writes and reads '1' bits for all 8 bits, only one error bit is detected. That is, in ‘00’ error pattern mode, only cell number 8 with high-defect is detected as defective, and in ‘FF’ error pattern mode, only cell number 1 with low-defect is detected as defective.

Additionally, in the ‘0F’ error pattern mode, which records and reads ‘0’ bits from cells 1 to 4 and ‘1’ bits from cells 5 to 8, no error bits are detected at all. In the end, the two error bits are in the 'F0' error pattern mode, which records and reads '1' bits from cells 1 to 4, and '0' bits from cells 5 to 8, as shown in Figure 3. can be detected.

In other words, if a plurality of error bits exist in one word, all error bits can be checked only when all of the plurality of error pattern modes are operated.

For example, a memory device containing 64 bits per word contains 15,625 words per 1M, and assuming, for example, that the error bits are 100,000 bits, there is a burden of recording all of them in memory, which requires a lot of test time and a large amount of time. A large amount of memory is required.

Accordingly, the semiconductor memory device 100 including the ECC circuit 130 according to the present invention determines whether the memory is in a normal state or a bad state by comparing the addresses of bad words with error bits using the ECC test mode 200. . In other words, since the presence or absence of a defect can be determined by comparing only the address of the defective word, the burden on the memory can be reduced and the test time can be significantly shortened.

Figure 3 is a diagram showing the ECC test mode of the present invention.

Referring to FIG. 3, the ECC test mode 200 of the present invention compares the addresses of defective words with error bits to determine a normal state or a defective state, and includes an ECC pattern test unit 210 and an ECC bypass test unit. 220 and an address comparison unit 230.

At this time, among the ECC test modes 200 of the present invention, the ECC test mode in which errors of N-bit or less are determined as normal in the N-bit ECC device and errors exceeding N are determined as defective are called 'N- It can be referred to as 'bit ECC test mode', and in the same N-bit ECC device, an ECC test mode in which errors of (N-1) bits or less are judged as normal, and errors of N-bit or more are judged as defective. It may be referred to as ‘(N-1)-bit ECC test mode’ or ‘(N-1) ECC test mode’. Additionally, if even 1-bit error bit occurs regardless of ECC (ECC-off), the ECC test mode that determines the test to be in a defective state can be referred to as ‘ECC bypass test mode’.

For testing, the ECC pattern test unit 210 may record first or second state bits in all M bits per word and read them to determine a normal state or a defective state. Here, the bit in the first state may be a ‘1’ bit, and the bit in the second state may be a ‘0’ bit. Additionally, the bit in the first state may be a ‘0’ bit, and the bit in the second state may be a ‘1’ bit.

For example, the ECC pattern test unit 210 may perform an (N-1) ECC test mode in which errors of N-bits or more are determined to be defective. Therefore, the ECC pattern test unit 210 records and reads '1' bits or '0' bits in all M bits, and determines that it is normal (Pass) only when (N-1) or less error bits are detected. You can.

The ECC pattern test unit 210 may include a first state pattern mode 211 and a second state pattern mode 212.

The first state pattern mode 211 writes and reads the first state bits in all M bits, and when more than (N-1) error bits are detected, the corresponding word can be determined to be in a defective state. That is, only words with (N-1) error bits can be determined as normal (Pass). For example, the first status bit may be a ‘1’ bit or a ‘0’ bit.

For example, when the first state pattern mode 211 is a pattern mode using the '1' bit, the first state pattern mode 211 is referred to as '#FF (N-1) ECC pattern mode', and '0' is referred to as '0'. In the case of a pattern mode using bits, the first state pattern mode 211 may be referred to as '#00 (N-1) ECC pattern mode'.

For example, when the first state pattern mode 211 has a #FF (N-1) ECC pattern mode, the first state pattern mode 211 records and reads '1' bit in all M bits per word. do. At this time, if more than N error bits are detected among the M bits, the corresponding word is determined to be in a defective state (Fail) and the test is terminated (Reject). In addition, when the first state pattern mode 211 has a #00 (N-1) ECC pattern mode, the first state pattern mode 211 writes and reads '0' bits in all M bits per word. . At this time, if more than N error bits are detected among the M bits, it is determined to be in a defective state (Fail) and the test is terminated (Reject).

If error bits are detected below (N-1) among M bits in #FF (N-1) ECC pattern mode or #00 (N-1) ECC pattern mode, the corresponding word is judged as normal (Pass). and the second state pattern mode 212 is performed.

The second state pattern mode 212 writes and reads the second state bits in all M bits, and when more than (N-1) error bits are detected, the corresponding word can be determined to be in a defective state. That is, only words with (N-1) error bits can be determined as normal (Pass). For example, the second status bit may be a ‘1’ bit or a ‘0’ bit.

For example, if the first state pattern mode 211 is a pattern mode using a ‘1’ bit, the second state pattern mode 212 may be a pattern mode using a ‘0’ bit. Additionally, when the first state pattern mode 211 is a pattern mode using a ‘0’ bit, the second state pattern mode 212 may be a pattern mode using a ‘1’ bit.

That is, when the first state pattern mode 211 is operated in #FF (N-1) ECC pattern mode, the second state pattern mode 212 can be operated in #00 (N-1) ECC pattern mode, , when the first state pattern mode 211 is operated in #00 (N-1) ECC pattern mode, the second state pattern mode 212 may be operated in #FF (N-1) ECC pattern mode.

At this time, the operation of the second state pattern mode 212 is determined to be normal when (N-1) or less error bits are detected in the operation of the first state pattern mode 211. It can be performed on words that have passed. In addition, even in the second state pattern mode 212, if (N-1) or less error bits are detected, the final normal state (good product) is determined and the test can be terminated.

That is, the ECC pattern test unit 210 determines normal or final defectiveness using the first state bit in the first state pattern mode 211, and in the second state pattern mode 212, the first state pattern mode 211 ) can be determined as normal or final defective using the second status bit.

As an example, the first state pattern mode 211 operates in #FF (N-1) ECC pattern mode to write and read '1' bits in all M bits per word, and indicates normal (Pass) or final failure ( Reject) is determined, and the second state pattern mode 212 operates in #00 (N-1) ECC pattern mode for words judged to be normal (Pass) to determine normal (Pass) or final defect (Reject). can be judged. At this time, the ECC bypass test unit 220 may be performed on words determined to be normal in the second state pattern mode 212.

For testing, the ECC bypass test unit 220 records and reads bits in the first state or second state in all M bits per word to determine a normal state or a defective state, and determines whether the word corresponding to the defective state is in a normal state or a defective state. Extract the address.

At this time, the ECC bypass test unit 220 may determine it to be a failure if one or more error bits are detected. That is, the ECC bypass test unit 220 may use the ECC bypass test mode. Therefore, the ECC bypass test unit 220 can determine a normal state only when no error bit is detected.

For example, in a memory having M bits per word, the ECC bypass test unit 220 can write and read bits in the first state or the second state for all M bits. Here, the bit in the first state may be a ‘1’ bit, and the bit in the second state may be a ‘0’ bit. Additionally, the bit in the first state may be a ‘0’ bit, and the bit in the second state may be a ‘1’ bit. That is, the ECC bypass mode writes and reads first-state bits or second-state bits in all M bits, and if one or more error bits are detected, it can be determined as defective.

In order to detect an error bit using the ECC bypass test unit 220, the ECC bypass test unit 220 includes a first state bypass mode 221 and a second state bypass mode 222. can do.

The first state bypass mode 221 writes and reads first state bits from all of the M bits, and when one or more error bits are detected, it is determined as a first defect. For example, the first status bit may be a ‘1’ bit or a ‘0’ bit.

For example, if the first state bypass mode 221 is a bypass mode using the '1' bit, the first state bypass mode 221 is referred to as '#FF ECC bypass mode', and the '0' bit is referred to as '#FF ECC bypass mode'. In the case of a bypass mode using , the first state bypass mode 221 may be referred to as '#00 ECC bypass mode'.

For example, when the first state bypass mode 221 has a #FF ECC bypass mode, the first state bypass mode 221 writes and reads ‘1’ bit in all M bits per word. At this time, if one or more error bits are detected among the M bits, it is determined as a first defect. Additionally, when the first state bypass mode 221 has a #00 ECC bypass mode, the first state bypass mode 221 writes and reads '0' bits to all M bits per word, and M If one or more error bits are found among the bits, it is determined as a first defect. If even one error bit is not detected, the word is determined to be in the final normal state (Good Die) and the test is terminated.

In addition, if one or more error bits are detected in the first state bypass mode 221 and determined to be a first defect, the first state bypass mode 221 is configured to provide the first Word address (word_ad1) information can be extracted. For example, when one or more error bits are detected in a word having M bits, the first state bypass mode 221 extracts the first word address (word_ad1), which is the address information of the word in which the error bit occurred, and The second state bypass mode 222 can be performed on the word from which the word address (word_ad1) is extracted.

The second state bypass mode 222 writes and reads the second state bits in all M bits, and determines the second state defect when one or more error bits are detected. For example, the first status bit may be a ‘1’ bit or a ‘0’ bit.

For example, if the first state bypass mode 221 is a bypass mode using a ‘1’ bit, the second state bypass mode 222 may be a bypass mode using a ‘0’ bit. Additionally, when the first state bypass mode 221 is a bypass mode using a ‘0’ bit, the second state bypass mode 222 may be a bypass mode using a ‘1’ bit.

That is, when the first state bypass mode 221 is operated in the #FF ECC bypass mode, the second state bypass mode 222 can be operated in the #00 ECC bypass mode, and the first state bypass mode 222 is operated in the #00 ECC bypass mode. When mode 221 is operated in #00 ECC bypass mode, the second state bypass mode 222 may be operated in #FF ECC bypass mode.

At this time, the operation of the second state bypass mode 222 may be performed on the word determined to be first defective due to an error bit detected in the first state bypass mode 221 operation. Additionally, if an error bit is not detected in the second state bypass mode 222, the test may be terminated and the final normal state (Good Die) may be determined.

For example, when the first state bypass mode 221 is operated in #FF ECC bypass mode, '1' bit is written and read in all M bits per word to determine normal or first defect, and the first state bypass mode is operated in #FF ECC bypass mode. The second state bypass mode 222 operates in the #00 ECC bypass mode for a word determined to be 1 defective and can be determined as a final normal state or a second defective word.

In addition, if one or more error bits are detected in the second state bypass mode 222 and it is determined to be a second defect, the second state bypass mode 222 is configured to use the second state bypass mode 222 as the address information of the corresponding word in which the error bit was detected. The word address (word_ad2) can be extracted. For example, when one or more error bits are detected in a word having M bits, the second state bypass mode 222 may extract the second word address (word_ad2), which is address information of the word in which the error bit occurred.

The address comparison unit 230 may determine the final normal state or defective state by comparing the extracted addresses. That is, the address comparison unit 230 compares the first word address (word_ad1) extracted in the first state bypass mode 221 and the second word address (word_ad2) extracted in the second state bypass mode 222. Thus, it is determined whether the two word addresses correspond to the same word.

If the first word address (word_ad1) and the second word address (word_ad2) correspond to the same word, the address comparison unit 230 determines the final defective state (Reject), and the first word address (word_ad1) and the second word address (word_ad2) correspond to the same word. If the two-word address (word_ad2) corresponds to a different word, the address comparison unit 230 determines the final normal state (Good Die).

For example, in the case of (N-1) ECC test mode in an N-bit (N=2) ECC semiconductor memory device, if two or more error bits are detected in one word, a final defective state is determined. That is, if the first word address (word_ad1) extracted in the first state bypass mode 221 and the second word address (word_ad2) extracted in the second state bypass mode 222 correspond to the same word, this means Since it means that two error bits exist in one word, the address comparison unit 230 determines the final defective state.

In addition, if the first word address (word_ad1) and the second word address (word_ad2) correspond to different words, that is, if they do not correspond to the same word, this means that there is only one error bit in one word. The address comparison unit 230 determines the final normal state.

Figure 4 is a flowchart briefly showing the test method of the ECC test mode of the present invention.

FIG. 5 is a flow chart showing the test method shown in FIG. 4.

FIG. 6 is a diagram illustrating the test method shown in FIG. 4.

Referring to FIGS. 4 to 6, the test method using the (N-1) ECC test mode according to the N-bit (N=2) ECC semiconductor memory device of the present invention uses the ECC pattern test unit 210 to test M A step (S310) of recording and reading first or second state bits in all bits to determine whether they are in a normal state or a defective state, targeting words determined to be in a normal state by the ECC pattern test unit 210, Using the ECC bypass test unit 220, write and read bits of the first or second state in all M bits to determine a normal state or a defective state, and extract the address of the word corresponding to the defective state. It includes a step (S320) and a step (S330) of comparing the extracted addresses with the address comparison unit 230 to determine the final normal state or defective state.

In the step (S310) of determining a normal state or a defective state using the ECC pattern test unit 210, as shown in FIG. 5, the first state bit ('1' bit) is recorded and read in all M bits. , performing a first state pattern mode (#FF (N-1) ECC pattern mode) 211 for determining a final defect when more than (N-1) error bits are detected, and the first state pattern For a word determined to be in a normal state in mode 211, the second state bit ('0' bit) is written and read in all M bits, and more than (N-1) error bits are detected. If so, it may include performing a second state pattern mode (#00 (N-1) ECC pattern mode) 212 to determine the final defect.

At this time, it does not matter if the test is performed using bit ‘0’ as the first state bit in the first state pattern mode 211 and using bit ‘1’ as the second state bit in the second state pattern mode 212.

In the ECC pattern test unit 210, if two or more error bits per word are detected using the first state pattern mode 211 or the second state pattern mode 212, it is determined as a final defect, and one error bit is detected. If it is detected below, it is judged as normal.

That is, the ECC pattern test unit 210 uses the first state pattern mode 211 and the second state pattern mode 212 to create a word containing two high-defects or two low-defects in one word. If detected, it can be rejected. In addition, a word determined to be normal by the ECC pattern test unit 210 may have no error bit (case 1), only one high-defect (case 2), or one low-defect (case 3). ), or a case where there is one high-defect and one low-defect (case 4). Accordingly, the ECC bypass test unit 220 may determine a normal state or a defective state depending on each case (cases 1, 2, 3, and 4).

As shown in FIG. 5, the step (S320) of determining a normal state or a defective state using the ECC bypass test unit 220 involves writing and reading the first state bit ('1' bit) in all M bits. Thus, when one or more error bits are detected, the first state bypass mode (#FF ECC bypass mode) determines the first defect and extracts the first word address (word_ad1), which is the address of the word corresponding to the first defect. Performing (221) and writing and reading second state bits ('0' bits) in all M bits, determining a second defect when one or more error bits are detected, and It may include performing a second state bypass mode (#00 ECC bypass mode) 222 to extract a second word address (word_ad2), which is the address of the word.

At this time, it does not matter if the test is performed using bit '0' as the first state bit in the first state bypass mode 221 and using bit '1' as the second state bit in the second state bypass mode 222. do.

First, the first state bypass mode (#FF ECC bypass mode) 221 is performed. If no error bit is detected in the first state bypass mode 221 (Case 1), the final normal state (Good Die) is determined. Additionally, when an error bit is detected (Case 3 or Case 4), it is determined to be a first defect, and the first word address (word_ad1), which is the address of the corresponding word, is extracted.

The second state bypass mode 222 is performed on the word determined as the first defect in the first state bypass mode 221. If an error bit is not detected even in the second state bypass mode (#00 ECC bypass mode) 222 (Case 1), it is determined as the final normal state (Good Die). Additionally, when an error bit is detected (case 2 or case 4), it is determined to be a second defect, and the second word address (word_ad2), which is the address of the corresponding word, is extracted.

In the step (S330) of determining a normal state or a defective state using the address comparison unit 230, the first word address (case 3 or case 4) extracted in the first state bypass mode 221 and the second state bypass are used. The final normal state or final defective state is determined by comparing the second word address (case 2 or case 4) extracted in the pass mode 222.

The address comparison unit 230 determines that if the first word address (word_ad1) and the second word address (word_ad2) correspond to the same word, this is because two error bits exist in one word as in (case 4). It is judged as defective (Reject). In addition, if the first word address (word_ad1) and the second word address (word_ad2) correspond to different words, this is because one error bit exists in one word as in (Case 2 or Case 3). It is judged as good die.

As an example, referring to FIG. 6, assuming that a memory device including 64-bits per word includes 15,625 words per 1M, the ECC pattern test unit 210 and the ECC bypass test unit 220 each Can be performed on words. At this time, the ECC test mode 200 may sequentially test each word, or test all words simultaneously.

The ECC test mode 200 can extract the first word address (word_ad1) or the second word address (word_ad2) for each word through the ECC pattern test unit 210 and the ECC bypass test unit 220. , the address comparison unit 230 may compare the first word address (word_ad1) and the second word address (word_ad2) for 15,625 words. If the two addresses extracted from among the 15,625 words equally correspond to one word (eg, word 3) (case 4), the address comparison unit 230 can determine the final defective state. Additionally, if the two extracted addresses correspond to different words (eg, words 1 and 2) (case 2 and 3), the address comparison unit 230 may determine the final normal state.

Ultimately, if there are two high-defects or two low-defects for one word, the ECC pattern test unit 210 may determine it to be a final defective state, and even if there is one high-defect or low-defect, Since two error bits can be detected through the ECC bypass test unit 220 and the address comparison unit 230, the final defective state can be determined. Therefore, the burden on memory can be reduced and test time can be significantly shortened.

Figure 7 is a diagram showing an example of determining a defect using the (N-1) ECC test mode of the present invention.

Figure 8 is a diagram showing another example of determining defects using the (N-1) ECC test mode of the present invention.

Here, Figure 7 shows a method of performing a test using the (N-1) ECC test mode (N=2) when two error bits exist in a 16-bit word, and Figure 8 shows a method of performing a test using the 16-bit word. When there are three error bits in a word with (N-1), the method of performing a test using the ECC test mode (N=2) is shown.

First, referring to FIG. 7, assuming that among the words consisting of 16 bits, cell number 5 has a low defect and cell number 12 has a high defect, the ECC pattern test unit 210 is first performed. Since only the high-defect of cell 12 is detected in the first state pattern mode (#FF (N-1) ECC pattern mode) 211 of the ECC pattern test unit 210, it is determined to be in a normal state (Pass), The second state pattern mode (#00 (N-1) ECC pattern mode) 212 is performed. Even in the second state pattern mode (#00 (N-1) ECC pattern mode) 212, only the row-defect of cell No. 5 is detected, so it is determined to be in a normal state (Pass).

At this time, the second state pattern mode (#00 (N-1) ECC pattern mode) (212) is performed first, and the first state pattern mode (#FF (N-1) ECC pattern mode) (211) is performed later. It can be seen that the results are the same.

Since the ECC pattern test unit 210 determines a normal state, the ECC bypass test unit 220 is performed. First, since the high-failure of cell 12 is detected in the first state bypass mode (#FF ECC bypass mode) 221, it is determined as a first failure (Fail), and the second state bypass mode (#00 ECC bypass mode) 222 is performed. At this time, the first state bypass mode 221 extracts the first word address (word_ad1), which is the address of the word corresponding to the first defect.

Since the row-failure of cell 5 is detected in the second state bypass mode (#00 ECC bypass mode) 222, it is determined as a second failure (Fail), and the address comparison unit 230 is performed. At this time, the second state bypass mode 222 extracts the second word address (word_ad2), which is the address of the word corresponding to the second defect.

Since the first word address (word_ad1) and the second word address (word_ad2) extracted by the address comparison unit 230 correspond to the same word, the address comparison unit 230 determines that two error bits exist in one word. The final defect status (Reject) is determined and the test is terminated.

Continuing with reference to FIG. 8, assuming that among the words consisting of 16 bits, there is a high-defect in cell 4, a low-defect in cell 5, and a high-defect in cell 12, first, the ECC pattern test unit ( 210) is performed. In the first state pattern mode (#FF (N-1) ECC pattern mode) 211 of the ECC pattern test unit 210, the high-defect of the 4th cell and the high-defect of the 12th cell are detected. That is, because two error bits are detected, the ECC pattern test unit 210 determines the final defective state (Reject) and ends the test.

In addition, even if the second state pattern mode (#00 (N-1) ECC pattern mode) 212 is performed first, only a row-defect is detected in cell 5 in the second state pattern mode 212, but the first state pattern mode 212 is not detected. Since two error bits are detected in the state pattern mode (#FF (N-1) ECC pattern mode) 211, the ECC pattern test unit 210 determines the final defect state (Reject) and ends the test.

As described above, the semiconductor memory device including the ECC circuit and the test method using the same can determine defective and good products by comparing addresses of defective words with error bits using the ECC test mode 200 of the ECC circuit. Therefore, the memory burden can be reduced and the configuration of the device can be simplified. In addition, since the ECC pattern test unit 210 and the ECC bypass test unit 220 of the ECC test mode 200 can be used to determine defective and good products by comparing only the addresses of defective words, the test time can be significantly shortened. You can.

Meanwhile, the embodiments of the present invention disclosed in the specification and drawings are merely specific examples to aid understanding and are not intended to limit the scope of the present invention. It is obvious to those skilled in the art that in addition to the embodiments disclosed herein, other modifications based on the technical idea of the present invention can be implemented.

100: semiconductor memory device 110: memory cell array
120: memory controller 130: ECC circuit
200: ECC test mode 210: ECC pattern test unit
211: first state pattern mode 212: second state pattern mode
220: ECC bypass test unit 221: First state bypass mode
222: Second state bypass mode 230: Address comparison unit

Claims (15)

A memory cell array including M bits (M is a positive integer) in one word among a plurality of words connected to the cell array; and
It includes an N-bit ECC circuit that detects and corrects error bits of N-bits (N=2) or less of the memory cell array,
A semiconductor memory device comprising an ECC circuit, wherein the ECC circuit includes an ECC test mode to determine a normal state or a defective state by comparing addresses of defective words with error bits. The method of claim 1, wherein the ECC test mode is:
an ECC pattern test unit that records first or second state bits in all of the M bits and reads them to determine a normal state or a defective state;
An ECC bypass test unit that writes and reads bits in a first state or a second state in all of the M bits to determine a normal state or a defective state, and extracts the address of a word corresponding to the defective state; and
A semiconductor memory device including an ECC circuit including an address comparison unit that compares the extracted addresses to determine a final normal state or defective state. According to paragraph 2,
A semiconductor memory device including an ECC circuit, wherein the operation of the ECC bypass test unit is performed on words determined to be in a normal state by the ECC pattern test unit. The method of claim 2, wherein the ECC pattern test unit,
a first state pattern mode that records and reads the first state bits in all of the M bits and determines a final defective state when more than (N-1) error bits are detected; and
An ECC circuit including a second state pattern mode that writes and reads the second state bits in all of the M bits and determines a final defective state when more than (N-1) error bits are detected. semiconductor memory device. According to paragraph 4,
A semiconductor memory device including an ECC circuit, wherein the operation of the second state pattern mode is performed on a word determined to be normal in the first state pattern mode. The method of claim 2, wherein the ECC bypass test unit,
Writing and reading bits in the first state in all of the M bits, determining a first defect if one or more error bits are detected, and extracting a first word address, which is the address of the word corresponding to the first defect, first state bypass mode; and
Writing and reading bits in the second state in all of the M bits, determining a second defect if one or more error bits are detected, and extracting a second word address, which is the address of the word corresponding to the second defect, A semiconductor memory device comprising an ECC circuit including a second state bypass mode. According to clause 6,
A semiconductor memory device including an ECC circuit, wherein the operation of the second state bypass mode is performed on the word determined as the first defect in the first state bypass mode. According to clause 6,
The address comparison unit includes an ECC circuit that compares the first word address and the second word address to determine a final normal state and a final defective state. According to clause 6,
The address comparison unit includes an ECC circuit that determines a final defective state when the first word address and the second word address correspond to the same word. ECC test mode is performed using an N-bit ECC circuit that detects and corrects error bits of N-bits (N=2) or less from a memory cell array containing M bits (M is a positive integer) in one word. Steps to execute; and
A semiconductor memory device including an ECC circuit, including the step of executing an ECC test mode to determine a normal state or a defective state of the memory cell array by comparing addresses of bad words having error bits by operating the ECC test mode. How to test. The method of claim 10, wherein using the ECC test mode comprises:
Recording first or second state bits in all of the M bits using an ECC pattern test unit and reading them to determine a normal state or a defective state;
For words determined to be in a normal state by the ECC pattern test unit, write and read bits in the first state or second state in all of the M bits using the ECC bypass test unit to determine the normal state or defective state. and extracting the address of the word corresponding to the defective state; and
A test method for a semiconductor memory device including an ECC circuit, comprising comparing the extracted addresses with an address comparison unit to determine a final normal state or defective state. The method of claim 11, wherein using the ECC pattern test unit comprises:
performing a first state pattern mode of writing and reading the first state bits in all of the M bits and determining a final defect if more than (N-1) error bits are detected; and
ECC comprising the step of performing a second state pattern mode of writing and reading the second state bits in all of the M bits and determining a final defect when more than (N-1) error bits are detected. Test method for a semiconductor memory device containing a circuit. The method of claim 11, wherein using the ECC bypass test unit comprises:
Writing and reading bits in the first state in all of the M bits, determining a first defect if one or more error bits are detected, and extracting a first word address, which is the address of the word corresponding to the first defect, performing a first state bypass mode; and
Writing and reading bits in the second state in all of the M bits, determining a second defect if one or more error bits are detected, and extracting a second word address, which is the address of the word corresponding to the second defect, A method for testing a semiconductor memory device including an ECC circuit comprising performing a second state bypass mode. The method of claim 13, wherein the comparing using the address comparison unit comprises:
A test method for a semiconductor memory device including an ECC circuit, comprising comparing the first word address and the second word address to determine a final normal state and a final defective state. The method of claim 13, wherein in the step of comparing by the address comparison unit,
The address comparison unit determines a final defective state when the first word address and the second word address correspond to the same word, and determines a normal state when the first word address and the second word address correspond to different words. How to test.