KR102680953B1 - Semiconductor Memory Device Having ECC Circuit and Test Method Thereof - Google Patents

Abstract

A semiconductor memory device including an ECC circuit capable of determining memory defects using an ECC test mode and a test method using the same are disclosed. This is because the ECC test mode of the ECC circuit can be used to determine good or defective products based on the number of critical defects, rather than the conventional method of counting error bits. Therefore, a separate memory is required to record and remember the addresses of defective cells. It doesn't work. Therefore, costs can be reduced and the configuration of the device can be simplified. Additionally, in ECC test mode, good or defective products can be determined simply based on the critical number of defects, which can significantly shorten the test time.

Description

Semiconductor memory device having ECC circuit and test method using same {Semiconductor Memory Device Having ECC Circuit and Test Method Thereof}

The present invention relates to a semiconductor memory device including an ECC circuit and a test method using the same. More specifically, a semiconductor memory device including an ECC circuit capable of determining memory defects using an ECC test mode and a test using the same. It's about method.

After manufacturing a semiconductor memory device, tests are performed to select defective memory cells. Accurately detecting memory cells with such subtle defects during the test stage of a memory device is an important factor in the reliability of the memory device.

As one of the methods of detecting such defective cells and improving the yield of the memory device, an error check and correction (ECC) circuit with an error check and correction function is provided in the semiconductor memory device.

The ECC circuit allows the controller to detect and correct single or more bit errors per N-bit memory word.

Generally, if a single bit per word is corrected, it is called 1-bit ECC, if two bits are corrected, it is called 2-bit ECC, then 3-bit ECC, etc. For example, 2-bit ECC operates normally because if there are two error bits in a word, both error bits are corrected, but if there are three or more bits, the word is treated as defective. Additionally, 1-bit ECC operates normally because it corrects one error bit if there is one error bit in the word, but if there are two or more error bits, the word is treated as defective.

Therefore, from the user's perspective, in a 2-bit ECC device, 2-bit defects among words operate normally, but for reasons such as quality improvement, samples with words containing 2-bit defects are treated as defective, and samples with 1-bit defects or less per word are treated as defective. A test method that treats only good products as good is considered.

On the other hand, if the test program for selecting defective memory cells needs to count error bits per word, time to count error bits and a separate memory capable of counting are required. In other words, in order to count error bits, a memory that records and stores the address of the defective cell is required.

However, if numerous words are tested in a semiconductor memory device, the time required to count error bits and the burden on the memory increase. For example, a memory device containing 64 bits per word contains 15,625 words per 1M. For example, assuming that there are 100,000 error bits, all of them must be recorded, which requires a lot of test time and memory.

Korean registered patent 10-1912372

The technical problem to be achieved by the present invention is to provide a semiconductor memory device including an ECC circuit that can determine defective and good products based on threshold error bits using the ECC test mode of the ECC circuit, and a test method using the same.

A semiconductor memory device including an ECC circuit of the present invention for achieving the above-described problem includes a memory cell array including M bits (M is a positive integer) in one word among a plurality of words connected to the cell array, and the An N-bit ECC circuit detects and corrects error bits of N-bits (N is a positive integer) or less of a memory cell array, wherein the ECC circuit is in a normal state based on the number of critical error bits of the memory cell array. Or, it includes an ECC circuit including an ECC test mode for determining a defective state.

The ECC test mode includes an ECC bypass test unit that records bits in the first state or second state in all of the M bits and reads them to determine a normal state or a primary defect, and an error detection pattern in the M bits. It may include an ECC pattern test unit that sequentially records and reads to determine a normal state or a defective state.

The operation of the ECC pattern test unit may be performed on words determined to be primary defects in the ECC bypass test unit.

The ECC bypass test unit writes and reads the first state bits in all of the M bits, and determines the M bits as the first defect when one or more error bits are detected. It may include a second state bypass mode in which bits of the second state are written and read throughout, and if one or more error bits are detected, the second state bypass mode is determined as the first defect.

The operation of the second state bypass mode may be performed on words determined to be normal in the first state bypass mode.

A word determined to be normal in the second state bypass mode may be determined to be in the final normal state.

The ECC pattern test unit may determine a final defective state for words with more than (N-1) error bits.

When the one word has (M=2 ^L ) bits (L is a positive integer), the ECC pattern test unit can have (2L+2) different error pattern modes.

Each of the (2L+2) error pattern modes can be determined as normal only for words in which (N-1) or less error bits have occurred.

The (2L+2) error pattern mode is based on a first error pattern in which all of the M bits have bits in the first state, and odd-numbered error patterns excluding the first error pattern are sequentially changed to the previous odd-numbered error patterns. It is formed by M bits in which half of the first or second state bits of the th error pattern are maintained and the other half are inverted, and the even-numbered error patterns can be formed by inverting all the bits of the preceding odd-numbered error pattern.

A test method for a semiconductor memory device including an ECC circuit of the present invention to achieve the above-described problem is to test N-bits (N is a positive integer) from a memory cell array containing M bits (M is a positive integer) in one word. (an integer of) executing an ECC test mode using an N-bit ECC circuit that detects and corrects the following error bits, and using the ECC test mode to determine a normal state or It may include determining a defective state.

The step of using the ECC test mode includes recording first-state or second-state bits in all of the M bits using an ECC bypass test unit, reading them, and determining a normal state or a first bad word; For the word determined to be the first defective in the ECC bypass test unit, sequentially recording and reading an error pattern mode in the M bits using an ECC pattern test unit to determine a normal state or a defective state. It can be included.

The step of using the ECC bypass test unit includes a first step of recording and reading bits in the first state in all of the M bits and determining a first defect when one or more error bits are detected, and in the first step, It may include a second step of writing and reading bits in the second state in all of the M bits for a word determined to be in a normal state, and determining it as defective if one or more error bits are detected.

In the step of using the ECC pattern test unit, if the one word has (M=2 ^L ) bits (L is a positive integer), the ECC pattern test unit operates (2L+2) different error pattern modes. It may include an ECC circuit.

The (2L+2) error pattern mode is based on a first error pattern in which all of the M bits have bits in the first state, and odd-numbered error patterns excluding the first error pattern are sequentially changed to the previous odd-numbered error patterns. It is formed by M bits in which half of the first or second state bits of the th error pattern are maintained and the other half are inverted, and the even-numbered error patterns can be formed by inverting all the bits of the preceding odd-numbered error pattern.

The step of using the ECC pattern test unit includes determining a word containing an error bit using each of the (2L+2) error pattern modes, wherein any one of the (2L+2) error pattern modes If more than (N-1) error bits occur in the mode, the test may be stopped and an ECC circuit may be included to determine a final defective state.

According to the present invention described above, since good or defective products can be determined based on the critical defective number using the ECC test mode of the ECC circuit rather than the conventional method of counting error bits, the address of the defective cell must be recorded and stored. No separate memory is required. Therefore, costs can be reduced and the configuration of the device can be simplified.

Additionally, in ECC test mode, good or defective products can be determined simply based on the critical number of defects, which can significantly shorten the test time.

The technical effects of the present invention are not limited to those mentioned above, and other technical effects not mentioned will be clearly understood by those skilled in the art from the description below.

1 is a block diagram showing a semiconductor memory device of the present invention.
Figure 2 is a diagram showing the ECC test mode of the present invention.
Figure 3 is a diagram showing an example of applying an error detection pattern to detect an error bit.
Figure 4 is a diagram showing an error pattern mode consisting of 8 bits per word.
Figure 5 is a diagram showing an error pattern mode consisting of 64-bits per word.
Figure 6 is a flowchart briefly showing the test method of the ECC test mode of the present invention.
FIG. 7 is a flow chart showing the test method shown in FIG. 6.
Figure 8 is a diagram showing an example of determining defects using the 2-bit ECC test mode of the present invention.
Figure 9 is a diagram showing another example of determining defects using the 2-bit ECC test mode of the present invention.

Since the present invention can be subject to various changes and have various forms, specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, and should be understood to include all changes, equivalents, and substitutes included in the spirit and technical scope of the present invention. While describing each drawing, similar reference numerals are used for similar components.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by a person of ordinary skill in the technical field to which the present invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and unless explicitly defined in the present application, should not be interpreted in an ideal or excessively formal sense. No.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings.

1 is a block diagram showing a semiconductor memory device of the present invention.

Referring to FIG. 1, the semiconductor memory device 100 of the present invention may be any device including a memory for storing input data and using the stored data as output data. For example, a system-on-chip (SoC) such as an application processor (AP), dynamic random access memory (DRAM), magnetoresistive random access memory (MRAM), flash memory, etc., according to external commands. It may be a memory system that stores input data and outputs output data according to a host's request, such as a semiconductor memory device that stores input data and outputs output data, a solid state drive (SSD), or a memory card.

Additionally, the semiconductor memory device 100 of the present invention may include a memory cell array 110, a memory controller 120, and an ECC circuit 130.

The memory cell array 110 may include a plurality of memory cells (not shown) each disposed in areas where a plurality of first signal lines and a plurality of second signal lines intersect. For example, the first signal lines may be bit lines, and the second signal lines may be word lines. Additionally, each of the plurality of memory cells may be a single level cell (SLC) that stores one bit, or a multi-level cell (MLC) that can store at least 2 bits of data. there is.

For example, among a plurality of words, one word may include M bits (M is a positive integer). That is, each of the plurality of words can be connected to M cells.

The memory controller 120 reads data stored in the memory cell array 110 in response to a write/read request from the host, or operates the memory cell array 110 to write data to the memory cell array 110. can be controlled. Specifically, the memory controller may control program (or write), read, and erase operations for the memory cell array 110 by providing addresses, commands, and control signals to the memory cell array 110. Additionally, data to be written and read data may be transmitted and received between the memory controller 120 and the memory cell array 110.

Although not shown, the memory controller may include RAM, a host interface, and a memory interface. RAM can be used as the operating memory of the processor. The processor can control the overall operation of the memory controller. The host interface may include a protocol for exchanging data between the host and the memory controller. For example, the memory controller supports at least one of various interface protocols such as USB, MMC, PCI-E, ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI, ESDI, and IDE (Integrated Drive Electronics). It can be configured to communicate with the outside (HOST) through.

Additionally, the memory controller 120 may include an Error Correction Code (ECC) circuit. The ECC circuit 130 may perform error detection and correction operations on read data from the memory cell array 110.

The ECC circuit 130 can detect and correct error bits included in each of a plurality of words, and can have a correctable error amount. For example, when the ECC circuit 130 has 2-bit ECC, the ECC circuit 130 detects and corrects errors of 2-bit or less included in the received data, such as 1-bit errors and 2-bit errors. You can. That is, more than a 3-bit error can be treated as a defect. Additionally, when the ECC circuit 130 has 1-bit ECC, the ECC circuit 130 can only detect and correct errors of 1-bit or less, so errors of 2-bit or more can be treated as defects.

When the ECC circuit 130 has a correctable error amount of N-bits (N is a positive integer), the ECC circuit 130 may be referred to as ‘N-bit ECC’. For example, in a word containing M bits, N-bit ECC can detect and correct N errors per word. That is, out of M bits, there can be N correctable bits.

As described above, from the user's perspective, a 2-bit ECC device can detect and correct 1-bit errors and 2-bit errors, so it is possible to have a memory device that operates normally for 2-bit errors or less in a word. For reasons such as improving the quality of the device, an ECC test method may be considered in which samples with words containing 2-bit defects are treated as defective, and only samples with 1-bit defects or less per word are treated as good products.

In addition, if the ECC test program for selecting defective memory cells needs to count error bits per word, time to count error bits and a separate memory capable of counting are required. In other words, in order to count error bits, a memory that records and stores the address of the defective cell is required.

However, because numerous words must be tested in a semiconductor memory device, the time required to count error bits and the burden on the memory increase. For example, a memory device containing 64 bits per word contains 15,625 words per 1M, and assuming, for example, that the error bits are 100,000 bits, there is a burden of recording all of them in memory, which requires a lot of test time and memory. is required.

Therefore, the semiconductor memory device 100 including the ECC circuit 130 according to the present invention uses the ECC test mode 200, rather than counting error bits as in the prior art, to determine normal operation based on the number of critical error bits. Determines whether the memory is in good or bad condition. That is, no separate memory is required to record and remember the addresses of defective cells.

Figure 2 is a diagram showing the ECC test mode of the present invention.

Referring to FIG. 2, the ECC test mode 200 of the present invention uses the ECC bypass test unit 210 and the ECC pattern test to determine normal or bad memory based on the number of critical error bits without a separate memory. It may include unit 220.

At this time, among the ECC test modes 200 of the present invention, the ECC test mode in which errors of N-bit or less are determined as normal in the N-bit ECC device and errors exceeding N are determined as defective are called 'N- It can be referred to as 'bit ECC test mode', and in the same N-bit ECC device, an ECC test mode in which errors of (N-1) bits or less are judged as normal, and errors of N-bit or more are judged as defective. It may be referred to as ‘(N-1)-bit ECC test mode’ or ‘(N-1) ECC test mode’. Additionally, if even 1-bit error bit occurs regardless of ECC (ECC-off), the ECC test mode that determines the test to be in a defective state can be referred to as ‘ECC bypass test mode’.

The ECC bypass test unit 210 may determine a primary defect if one or more error bits occur. That is, the ECC bypass test unit 210 may use the ECC bypass test mode. Therefore, the ECC bypass test unit 210 can determine a normal state only when no error bit is determined.

For example, in a memory having M bits per word, the ECC bypass test unit 210 can write and read bits in the first state or the second state for all M bits. Here, the bit in the first state may be a ‘1’ bit, and the bit in the second state may be a ‘0’ bit. Additionally, the bit in the first state may be a ‘0’ bit, and the bit in the second state may be a ‘1’ bit. That is, the ECC bypass mode writes and reads first-state bits or second-state bits in all M bits, and if one or more error bits are detected, it can be determined as defective.

In order to perform error bit detection using the ECC bypass test unit 210, the ECC bypass test unit 210 uses the first state bypass mode 211 and the second state bypass mode 212. It can be included.

The first state bypass mode 211 writes and reads first state bits from all of the M bits, and if one or more error bits are detected, it is determined to be a primary defect. For example, the first status bit may be a ‘1’ bit or a ‘0’ bit.

For example, if the first state bypass mode 211 is a bypass mode using the '1' bit, the first state bypass mode 211 is referred to as '#FF ECC bypass mode', and the '0' bit is referred to as '#FF ECC bypass mode'. In the case of a bypass mode using , the first state bypass mode 211 may be referred to as '#00 ECC bypass mode'.

For example, when the first state bypass mode 211 has a #FF ECC bypass mode, the first state bypass mode 211 writes and reads ‘1’ bit in all M bits per word. At this time, if one or more error bits are found among the M bits, it is determined as a primary defect. Additionally, when the first state bypass mode 211 has a #00 ECC bypass mode, the first state bypass mode 211 writes and reads ‘0’ bits in all M bits per word. At this time, if one or more error bits are found among the M bits, it is determined as a primary defect.

The second state bypass mode 212 writes and reads second state bits from all of the M bits, and when one or more error bits are detected, it is determined as a primary defect. For example, the second status bit may be a ‘1’ bit or a ‘0’ bit.

For example, if the first state bypass mode 211 is a bypass mode using a ‘1’ bit, the second state bypass mode 212 may be a bypass mode using a ‘0’ bit. Additionally, when the first state bypass mode 211 is a bypass mode using a ‘0’ bit, the second state bypass mode 212 may be a bypass mode using a ‘1’ bit.

That is, when the first state bypass mode 211 is operated in the #FF ECC bypass mode, the second state bypass mode 212 can be operated in the #00 ECC bypass mode, and the first state bypass mode 212 is operated in the #00 ECC bypass mode. When mode 211 is operated in #00 ECC bypass mode, the second state bypass mode 212 may be operated in #FF ECC bypass mode.

At this time, the operation of the second state bypass mode 212 passes the first state bypass mode 211 because no error bit is detected in the operation of the first state bypass mode 211, that is, it is determined to be normal. ) can be performed on one word. Additionally, if an error bit is not detected in the second state bypass mode 212, the test may be terminated and the final normal state (good product) may be determined.

That is, the ECC bypass test unit 210 determines normal or first defective using the first state bit in the first state bypass mode 211, and the word that passed the first state bypass mode 211 The final normal state or the first defect can be determined using the second state bit in the second state bypass mode 212.

For example, when the first state bypass mode 211 is operated in #FF ECC bypass mode, '1' bit is written and read in all M bits per word to determine normal or primary defect, and normal The second state bypass mode 212 operates in the #00 ECC bypass mode for the word determined to be the final normal state or the first defect.

The ECC pattern test unit 220 detects one or more error bits that are determined to be defective in the ECC bypass test unit 210, that is, in the first state bypass mode 211 or the second state bypass mode 212. A test can be performed on words that are determined to be primary defects.

Additionally, the ECC pattern test unit 220 can sequentially record and read the error detection pattern per word having M bits for testing to determine the final defective state or the final normal state. That is, the ECC pattern test unit 220 can determine a defect using a plurality of error detection patterns.

Figure 3 is a diagram showing an example of applying an error detection pattern to detect an error bit.

Referring to FIG. 3, assuming that a word consisting of 8 bits has 2 error bits, a plurality of error pattern modes 221 must be performed to determine the 2 error bits.

At this time, when a high bit ('1' bit) is recorded and the high bit is read, a defect in which the high bit cannot be recorded or read is referred to as a 'high-defect', and a low bit ( When a '0' bit) is written and a row bit is read, a defect in which the row bit cannot be written or read is referred to as a 'row-defect'.

As shown in Figure 3, assuming that among the words consisting of 8 bits, there is a high-defect (0_struck) in the 1st cell and a low-defect (1_stuck) in the 8th cell, '0' is present in all 8 bits. In the '00' error pattern mode, which writes and reads bits, and the 'FF' error pattern mode, which writes and reads '1' bits for all 8 bits, only one error bit is detected. That is, in ‘00’ error pattern mode, only cell number 8 with high-defect is detected as defective, and in ‘FF’ error pattern mode, only cell number 1 with low-defect is detected as defective.

Additionally, in the ‘0F’ error pattern mode, which records and reads ‘0’ bits from cells 1 to 4 and ‘1’ bits from cells 5 to 8, no error bits are detected at all. In the end, the two error bits are in the 'F0' error pattern mode, which records and reads '1' bits from cells 1 to 4, and '0' bits from cells 5 to 8, as shown in Figure 3. can be detected.

That is, when multiple error bits exist in one word, multiple error pattern modes 221 must be operated to check all error bits.

Figure 4 is a diagram showing an error pattern mode consisting of 8 bits per word.

Figure 5 is a diagram showing an error pattern mode consisting of 64-bits per word.

First, referring to FIG. 4, in order to detect a defective cell of an 8-bit word, eight error pattern modes 221 are required, as shown in FIG.

For example, pattern #1 may be an 'FF' error pattern mode that writes and reads '1' bits in all eight cells, and pattern #2 inverts all of pattern #1 to write '0' in all eight cells. It may be a '00' error pattern mode that writes and reads bits.

Pattern #3 maintains only 4 '1' bits corresponding to half (50%) of the 8 '1' bits in pattern #1, and the remaining 4 '1' bits are inverted to form '0' bits. It can have 'F0' pattern mode. Additionally, pattern #4 may have a ‘0F’ pattern mode formed by reversing all of pattern #3.

Pattern #5 retains only two '1' bits, which is half (50%) of the four '1' bits in pattern #3, and the remaining two '1' bits are inverted to form '0' bits. It is possible to have a 'CC' pattern mode in which only two '0' bits, corresponding to half (50%) of the four '0' bits, are maintained, and the remaining two '0' bits are inverted to form '1' bits. Pattern #6 can have a ‘33’ pattern mode formed by reversing all of Pattern #5.

Using the above-described method, pattern #7 can have an ‘AA’ pattern mode, and pattern #8 can have a ‘55’ pattern mode.

That is, the error pattern mode 221 for an 8-bit word is based on the first error pattern (pattern #1) in which all 8 bits write and read the first state bit ('1' bit). , Odd error patterns (patterns #3, #5, #7) excluding the first error pattern (pattern #1) are in the first state ('1' bit) or second state ('bit) of the previous odd-numbered error pattern. Half (50%) of the 0' bits are maintained, and the bits corresponding to the remaining half (50%) are inverted to form 8 bits.

On the other hand, the even-numbered error patterns (patterns #2, #4, #6, #8) form 8 bits by inverting all the bits of the preceding odd-numbered error patterns. That is, the second error pattern (pattern #2) is formed by inverting all the bits of the first error pattern (pattern #1), and the fourth error pattern (pattern #4) is formed by inverting the entire bits of the first error pattern (pattern #3). It is formed by inverting all bits.

Accordingly, in an 8-bit word, the error bit can be accurately determined only when the above-described 8 error pattern modes 221 are operated.

As another example, Figure 5 shows an error pattern mode 221 consisting of 64-bits per word.

Referring to FIG. 5, a 64-bit word may have 14 error pattern modes 221, as shown in FIG. 5. That is, pattern #1 can have the 'FFFF_FFFF_FFFF_FFFF' pattern mode, pattern #2 can have the '0000_0000_0000_0000' pattern mode in which the entire pattern #1 is inverted, and the remaining pattern modes can be formed using the error pattern mode formation method described above, It can have 14 error pattern modes 221, including the final '5555_5555_5555_5555' pattern mode.

In addition, using the above-described error pattern mode 221 formation method, a 16-bit word can have 10 error pattern modes 221, and a 128-bit word can have 16 error pattern modes 221. .

That is, if one word has (M=2 ^L ) bits (M, L are positive integers), the error pattern mode 221 has (2L+2) different error pattern modes 221. You can.

For example, as shown in FIG. 4, a word composed of 8 (=2 ³ )-bits may have 8 (2*3+2) error pattern modes 221, and as shown in FIG. 5, 64 (=2 ⁶ ) bits. -A word composed of bits can have 14 (2*6+2) different error pattern modes (221).

Accordingly, the word determined to be a primary defect in the ECC bypass test unit 210 can be determined as a final defective state or a final normal state using the plurality of error pattern modes 221 described above in the ECC pattern test unit 220. You can.

Continuing to refer to FIG. 2, the word determined to be a primary defect in the ECC bypass test unit 210 is tested by the ECC pattern test unit 220 as a first error pattern (pattern #1) and a second error pattern (pattern # 2), each test can be performed using the third error pattern (pattern #3)... For example, if the first error pattern (pattern #1) is determined to be defective, it is determined to be in a final defective state, and the test is ended. Additionally, if the first error pattern is determined to be normal, the second error pattern (pattern #2) is performed, and if the second error pattern is determined to be normal, the third error pattern is performed. That is, if it is determined to be defective in each error pattern mode, the test is terminated, and if it is determined to be normal, the next step of the error pattern mode is performed. Therefore, only words that have passed all of the error pattern modes 221 can be determined to be in the final normal state.

As described above, it is possible to determine the error bit of a word even by using only the ECC pattern test unit 220. However, when testing a device containing 64-bits per word, since there are 15,625 words per 1M (mega), a separate memory is needed to count error bits, and the counting time and memory burden are large. You lose.

Therefore, the ECC test mode 200 of the memory device according to the present invention performs the ECC pattern test unit 220 on only words determined to be defective in the ECC bypass test unit 210, and determines the number of critical error bits based on the number of critical error bits. Since it determines a normal or defective state, no separate memory is required.

For example, in the semiconductor memory device 100 including an N-bit ECC circuit, when testing is performed using the (N-1) ECC test mode, the ECC bypass test unit 210 displays '0' in all cells. If one or more error bits are generated by recording and reading 'bits or '1' bits, it is quickly determined as a primary defect, and a plurality of errors are detected in the ECC pattern test unit 220 only for words determined to be primary error bits. If (N-1) error bits are generated using the pattern mode 221, it is determined as a final defect. That is, since the normal state or defective state can be determined based on the number of critical error bits using the ECC bypass test unit 210 and the ECC pattern test unit 220, the test time can be dramatically shortened.

Figure 6 is a flowchart briefly showing the test method of the ECC test mode of the present invention.

FIG. 7 is a flow chart showing the test method shown in FIG. 6.

Referring to Figures 6 and 7, the test method using the ECC test mode 200 of the present invention records bits in the first state or second state in all M bits using the ECC bypass test unit 210. and determining a normal state or a first defective word by reading (S310), and using the ECC pattern test unit 220 to test the word determined as a first defective word by the ECC bypass test unit 210. It includes a step (S320) of sequentially recording and reading an error detection pattern in bits to determine a normal state or a defective state.

In the step (S310) of determining a defective cell using the ECC bypass test unit 210, as shown in FIG. 7, the first state bit ('1' bit) is written and read in all M bits, Performing a first state bypass mode (#FF ECC bypass mode) 211 that determines a word to be defective when one or more error bits are detected, and a word determined to be in a normal state in the first state bypass mode 211 Targeting, the second state bypass mode (#00 ECC bypass mode) records and reads the second state bit ('0' bit) in all M bits, and determines it as defective when one or more error bits are detected. ) may include performing (212).

That is, if one or more error bits are found in the first state bypass mode 211, the corresponding word is determined to be failed and the ECC pattern test unit 220 is performed. If one or more error bits are not found in the first state bypass mode 211, the corresponding word is determined to be normal (pass), and the second state bypass mode 212 is performed.

If one or more error bits are found in the second state bypass mode 212, the corresponding word is determined to be failed and the ECC pattern test unit 220 is performed. If in the second state bypass mode 212 If one or more error bits are not found, the corresponding word is determined to be normal (pass), the final normal state is determined, and the test is terminated. At this time, it does not matter if the test is performed using bit ‘0’ as the first state bit in the first state bias mode, and using bit ‘1’ as the second state bit in the second state bias mode.

The step (S320) of determining a defective cell using the ECC pattern test unit 220 is performed on words determined to be defective by the ECC bypass test unit 210, using a plurality of error pattern modes 221. Thus, defectiveness can be determined. At this time, when one word has (M=2 ^L ) bits, the plurality of error pattern modes 221 may have (2L+2) different error pattern modes 221. Additionally, in the semiconductor memory device 100 including the N-bit ECC circuit 130, the ECC pattern test unit 220 may use an (N-1) ECC test mode.

First, the (N-1) ECC test mode for the first error pattern (pattern #1) is performed on words determined to be defective in the ECC bypass test unit 210. Accordingly, if more than (N-1) error bits are detected, the corresponding word is determined to be failed, is determined to be in a final failed state, and the test is terminated.

If (N-1) or less error bits are detected in the first error pattern (pattern #1), the corresponding word is determined to be normal (pass), and the second error pattern (pattern #2), which is the next pattern mode, is determined to be normal (pass). For (N-1) ECC test mode is performed.

In the same way, each error pattern mode is performed, and if fewer than (N-1) error bits are detected in the final (2L+2) error pattern mode (pattern #(2L+2)), the corresponding word is It is determined to be normal (pass), and the final normal state is determined and the test is ended.

Figure 8 is a diagram showing an example of determining defects using the 2-bit ECC test mode of the present invention.

Figure 9 is a diagram showing another example of determining defects using the 2-bit ECC test mode of the present invention.

Here, Figure 8 shows a test method when two error bits exist in a 16-bit word, and Figure 9 shows a test method when three error bits exist in a 16-bit word.

First, referring to FIG. 8, assuming that among the words consisting of 16 bits, cell 5 has a low defect and cell 12 has a high defect, the ECC bypass test unit 210 is first performed. Since high-defect of cell 12 is detected in the first state bypass mode (#FF ECC bypass mode) 211 of the ECC bypass test unit 210, it is determined to be defective. In addition, even if the second state bypass mode (#00 ECC bypass mode) 212 is performed first, since the row-defect of cell 5 is detected, it is determined to be a primary defect. Therefore, the corresponding word is tested using the ECC pattern test unit 220.

Since the corresponding word determined to be a primary defect contains 16-bits per word, the ECC pattern mode uses 10 error pattern modes 221 to perform (N-1) 1-bit (N=2) ECC test mode. ) ECC test mode is performed. That is, if there is one or less error bits, it is judged as normal (pass), and if there are two or more error bits, it is judged as failure.

First, only one error bit is detected in the 'FFFF' pattern mode, which is the first error pattern (pattern #1), and the '0000' pattern mode, which is the second pattern mode (pattern #2), and the third error pattern (pattern # 3) In the 'FF00' pattern mode, no error bits are detected, so all are judged as normal (pass). However, in the '00FF' pattern mode, which is the third error pattern (pattern #4), both the low-defect bit in cell 5 and the high-error bit in cell 12 can be detected, so more than two error bits are detected and the final error bit is detected. A defective state is determined and the test is terminated.

Referring to FIG. 9, assuming that among the words consisting of 16 bits, there is a high-defect in the 4th cell, a low-defect in the 5th cell, and a high-defect in the 12th cell, first, the ECC bypass test unit 210 is performed. In the first state bypass mode (#FF ECC bypass mode) 211 of the ECC bypass test unit 210, the high-defect of the 4th cell and the 12th cell are detected as defective. . In addition, even if the second state bypass mode (#00 ECC bypass mode) 212 is performed first, since the row-defect of cell 5 is detected, it is determined to be a primary defect. Therefore, the corresponding word is tested using the ECC pattern test unit 220.

Since the corresponding word determined to be a primary defect contains 16-bits per word, the ECC pattern mode uses 10 error pattern modes 221 to perform (N-1) 1-bit (N=2) ECC test mode. ) ECC test mode can be performed. That is, if there is one or less error bits, it is judged as normal (pass), and if there are two or more error bits, it is judged as failure.

In 'FFFF' pattern mode, which is the first error pattern (pattern #1), high-defect in cell 4 and high-defect in cell 12 are detected, so two or more error bits are detected to determine and test the final defective state. ends.

As described above, the semiconductor memory device including the ECC circuit and the test method using the same use the ECC test mode of the ECC circuit 130 to determine good or defective products based on the critical number of defects, rather than counting error bits in the conventional method. Since it can be determined, a separate memory to record and store the address of the defective cell is not required. Therefore, costs can be reduced and the configuration of the device can be simplified. In addition, in the ECC test mode 200, the test time can be significantly shortened because good or defective products can be determined simply based on the critical number of defects.

Meanwhile, the embodiments of the present invention disclosed in the specification and drawings are merely specific examples to aid understanding and are not intended to limit the scope of the present invention. It is obvious to those skilled in the art that in addition to the embodiments disclosed herein, other modifications based on the technical idea of the present invention can be implemented.

100: semiconductor memory device 110: memory cell array
120: memory controller 130: ECC circuit
200: ECC test mode 210: ECC bypass test unit
211: first state bypass mode 212: second state bypass mode
220: ECC pattern test unit 221: Error pattern mode

Claims (16)

A memory cell array including M bits (M is a positive integer) in one word among a plurality of words connected to the cell array; and
An N-bit ECC circuit that detects and corrects error bits of up to N bits (N is a positive integer) of the memory cell array,
The ECC circuit includes an ECC test mode that determines a normal state or a defective state based on the number of critical error bits of the memory cell array,
The ECC test mode is,
an ECC bypass test unit that records first-state or second-state bits in all of the M bits and reads them to determine a normal state or a primary defect; and
An ECC pattern test unit that sequentially records and reads an error detection pattern in the M bits to determine a normal state or a defective state,
If the one word has (M=2 ^L ) bits (L is a positive integer),
A semiconductor memory device including an ECC circuit in which the ECC pattern test unit has (2L+2) different error pattern modes. delete According to paragraph 1,
A semiconductor memory device including an ECC circuit, wherein the operation of the ECC pattern test unit is performed on a word determined to be a primary defect in the ECC bypass test unit. The method of claim 1, wherein the ECC bypass test unit,
a first state bypass mode that writes and reads bits of the first state in all of the M bits and determines the first defect when one or more error bits are detected; and
A semiconductor memory device comprising an ECC circuit including a second state bypass mode that writes and reads bits of the second state in all of the M bits and determines the first defect when one or more error bits are detected. According to clause 4,
A semiconductor memory device including an ECC circuit, wherein the second state bypass mode operation is performed on words determined to be normal in the first state bypass mode. According to clause 5,
A semiconductor memory device including an ECC circuit, wherein a word determined to be normal in the second state bypass mode is determined to be a final normal state. According to paragraph 1,
A semiconductor memory device including an ECC circuit, wherein the ECC pattern test unit determines a final defective state for words with more than (N-1) error bits. delete According to paragraph 1,
A semiconductor memory device including an ECC circuit in which each of the (2L+2) error pattern modes determines as normal only for words in which (N-1) or less error bits have occurred. The method of claim 1, wherein the (2L+2) error pattern modes are:
Based on a first error pattern in which all of the M bits have bits in the first state,
Odd-numbered error patterns excluding the first error pattern are sequentially formed of M bits in which half of the first or second state bits of the previous odd-numbered error pattern are maintained and the other half are inverted, and the even-numbered error patterns are A semiconductor memory device including an ECC circuit formed by inverting all the bits of the previous odd-numbered error pattern. ECC test using an N-bit ECC circuit that detects and corrects error bits of up to N-bits (N is a positive integer) from a memory cell array containing M bits (M is a positive integer) in one word. running the mode; and
and determining a normal state or a defective state based on the number of critical error bits of the memory cell array using the ECC test mode,
The step of using the ECC test mode is,
Writing first state or second state bits to all of the M bits using an ECC bypass test unit and reading them to determine a normal state or a first bad word; and
For the word determined to be the first defective in the ECC bypass test unit, sequentially recording and reading an error pattern mode in the M bits using an ECC pattern test unit to determine a normal state or a defective state. Includes,
In the step of using the ECC pattern test unit,
If the one word has (M=2 ^L ) bits (L is a positive integer),
A test method for a semiconductor memory device including an ECC circuit, wherein the ECC pattern test unit has (2L+2) different error pattern modes. delete The method of claim 11, wherein using the ECC bypass test unit comprises:
A first step of writing and reading bits in the first state in all of the M bits, and determining a first defect if one or more error bits are detected; and
A second step of writing and reading bits in the second state in all of the M bits for a word determined to be in a normal state in the first step and determining it as defective when one or more error bits are detected. Test method for semiconductor memory devices containing ECC circuits. delete The method of claim 11, wherein the (2L+2) error pattern modes are:
Based on a first error pattern in which all of the M bits have bits in the first state,
Odd-numbered error patterns excluding the first error pattern are sequentially formed of M bits in which half of the first or second state bits of the previous odd-numbered error pattern are maintained and the other half are inverted, and the even-numbered error patterns are A test method for a semiconductor memory device that is formed by inverting all the bits of the previous odd-numbered error pattern. The method of claim 11, wherein using the ECC pattern test unit comprises:
It includes determining a word containing an error bit using each of the (2L+2) error pattern modes,
A semiconductor including an ECC circuit that stops testing and determines a final defective state when more than (N-1) error bits occur in any one of the (2L+2) error pattern modes. How to test memory devices.