KR102680956B1 - Semiconductor Memory Device Having ECC Circuit and Test Method Thereof - Google Patents

Abstract

A semiconductor memory device including an ECC circuit capable of determining memory defects using an ECC test mode and a test method using the same are disclosed. This can be used to determine good or defective products based on the number of critical error bits using the ECC test mode of the ECC circuit, thereby reducing the burden on the memory and simplifying the device configuration. In addition, using the ECC test mode, test time can be significantly shortened because good or defective products can be determined by simply comparing the number of error bits and critical error bits.

Description

Semiconductor memory device having ECC circuit and test method using same {Semiconductor Memory Device Having ECC Circuit and Test Method Thereof}

The present invention relates to a semiconductor memory device including an ECC circuit and a test method using the same. More specifically, a semiconductor memory device including an ECC circuit capable of determining memory defects using an ECC test mode and a test using the same. It's about method.

After manufacturing a semiconductor memory device, tests are performed to select defective memory cells. Accurately detecting memory cells with such subtle defects during the test stage of a memory device is an important factor in the reliability of the memory device.

As one of the methods of detecting such defective cells and improving the yield of the memory device, an error check and correction (ECC) circuit with an error check and correction function is provided in the semiconductor memory device.

The ECC circuit allows the controller to detect and correct single or more bit errors per N-bit memory word.

Generally, if a single bit per word is corrected, it is called 1-bit ECC, if two bits are corrected, it is called 2-bit ECC, then 3-bit ECC, etc. For example, 2-bit ECC operates normally because if there are two error bits in a word, both error bits are corrected, but if there are three or more bits, the word is treated as defective. Additionally, 1-bit ECC operates normally because it corrects one error bit if there is one error bit in the word, but if there are two or more error bits, the word is treated as defective.

Therefore, from the user's perspective, in a 2-bit ECC device, 2-bit defects among words operate normally, but for reasons such as quality improvement, samples with words containing 2-bit defects are treated as defective, and samples with 1-bit defects or less per word are treated as defective. A test method that treats only good products as good is considered.

On the other hand, if the test program for selecting defective memory cells needs to count error bits per word, time to count error bits and a separate memory capable of counting are required. In other words, in order to count error bits, a memory that records and stores the address of the defective cell is required.

However, if numerous words are tested in a semiconductor memory device, the time required to count error bits and the burden on the memory increase. For example, a memory device containing 64 bits per word contains 15,625 words per 1M. For example, assuming that there are 100,000 error bits, all of them must be recorded, which requires a lot of test time and memory.

Korean registered patent 10-1912372

The technical problem to be achieved by the present invention is to provide a semiconductor memory device including an ECC circuit that can determine defective and good products by comparing error bits with the critical number of error bits using the ECC test mode of the ECC circuit, and a test method using the same. I'm doing it.

A semiconductor memory device including an ECC circuit of the present invention for achieving the above-described problem includes a memory cell array including M bits (M is a positive integer) in one word among a plurality of words connected to the cell array, and the and an N-bit ECC circuit that detects and corrects error bits of less than or equal to N-bits (N is a positive integer) of the memory cell array, wherein the ECC circuit detects and corrects error bits among the M bits of the memory cell array. It includes an ECC test mode that counts and compares the counted error bits with a critical number of error bits to determine a normal state or a defective state.

The ECC test mode includes an ECC bypass test unit that records bits in the first state or second state in all of the M bits, reads them, and determines a normal state or first defect, and It may include an ECC error count unit that records and reads bits in the first state or the second state, counts bits determined to be error bits, and determines a normal state or a defective state.

The operation of the ECC error count unit may be performed on words determined to be primary defects in the ECC bypass test unit.

The ECC bypass test unit writes and reads the first state bits in all of the M bits, and determines the first state defect when one or more error bits are detected, and the M bits. It may include a second state bypass mode in which bits of the second state are written and read throughout, and if one or more error bits are detected, the second state is determined to be defective.

The operation of the second state bypass mode may be performed on words determined to be normal in the first state bypass mode.

A word determined to be normal in the second state bypass mode may be determined to be in the final normal state.

The ECC error count unit may determine a final defective state for a word in which (N-1) error bits have occurred.

The ECC error count unit detects a first error bit by writing and reading the first state bits in all of the M bits, and counts the detected first error bits in a first state count mode, the M A second state count mode that detects a second error bit by writing and reading the second state bits in all bits, and counts the detected second error bits, and the number of the first error bits and the second error bit. It may include an integrated count mode that adds up the number of bits and determines a normal state or a defective state using the summed number of error bits.

The first state count mode and the second state count mode can be determined to be normal only for words in which (N-1) or fewer first error bits are detected.

The operation of the second state count mode may be performed on words determined to be normal in the first state count mode.

A test method for a semiconductor memory device including an ECC circuit of the present invention to achieve the above-described problem is to test N-bits (N is a positive integer) from a memory cell array containing M bits (M is a positive integer) in one word. (an integer of) executing an ECC test mode using an N-bit ECC circuit that detects and corrects the following error bits, and counting error bits of the memory cell array using the ECC test mode, and calculating the counted errors. Comparing the bits with a threshold number of error bits to determine a normal state or a defective state.

Writing and reading bits in a first state or a second state in all of the M bits using an ECC bypass test unit to determine a normal state or a first bad word; and determining a normal state or a first bad word in the ECC bypass test unit. For a word determined to be defective, bits in the first state or the second state are recorded and read in all of the M bits using an ECC error count unit, and bits determined to be error bits are counted to enter the normal state or defective state. It may include an ECC circuit including the step of determining the state.

The step of using the ECC bypass test unit includes a first step of recording and reading bits in the first state in all of the M bits and determining a first defect when one or more error bits are detected, and in the first step, It may include a second step of writing and reading bits in the second state in all of the M bits for a word determined to be in a normal state, and determining the word to be defective if one or more error bits are detected.

The step of using the ECC error count unit includes writing and reading the first state bits in all of the M bits, detecting (N-1) first error bits, and counting the detected first error bits. Performing a first state count mode, recording and reading bits of the second state in all of the M bits, detecting (N-1) second error bits, and counting the detected second error bits. It includes performing a two-state count mode and performing an integrated count mode of summing the number of the first error bits and the number of the second error bits and determining a normal state or a defective state using the summed number of error bits. can do.

The operation of the second state count mode may be performed on words determined to be normal in the first state count mode.

According to the present invention described above, since good or defective products can be determined using the critical number of error bits using the ECC test mode of the ECC circuit, the burden on the memory can be reduced and the configuration of the device can be simplified.

In addition, the ECC test mode can be used to determine whether a product is good or defective by simply comparing the number of error bits and the critical number of error bits, thereby significantly shortening the test time.

The technical effects of the present invention are not limited to those mentioned above, and other technical effects not mentioned will be clearly understood by those skilled in the art from the description below.

1 is a block diagram showing a semiconductor memory device of the present invention.
Figure 2 is a diagram showing an example of applying an error detection pattern to detect an error bit.
Figure 3 is a diagram showing the ECC test mode of the present invention.
Figure 4 is a flowchart briefly showing the test method of the ECC test mode of the present invention.
FIG. 5 is a flow chart showing the test method shown in FIG. 4.
Figure 6 is a diagram showing an example of determining defects using the 2-bit ECC test mode of the present invention.
Figure 7 is a diagram showing another example of determining defects using the 2-bit ECC test mode of the present invention.

Since the present invention can be subject to various changes and have various forms, specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, and should be understood to include all changes, equivalents, and substitutes included in the spirit and technical scope of the present invention. While describing each drawing, similar reference numerals are used for similar components.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by a person of ordinary skill in the technical field to which the present invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and unless explicitly defined in the present application, should not be interpreted in an ideal or excessively formal sense. No.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings.

1 is a block diagram showing a semiconductor memory device of the present invention.

Referring to FIG. 1, the semiconductor memory device 100 of the present invention may be any device including a memory for storing input data and using the stored data as output data. For example, a system-on-chip (SoC) such as an application processor (AP), dynamic random access memory (DRAM), magnetoresistive random access memory (MRAM), flash memory, etc., according to external commands. It may be a memory system that stores input data and outputs output data according to a host's request, such as a semiconductor memory device that stores input data and outputs output data, a solid state drive (SSD), or a memory card.

Additionally, the semiconductor memory device 100 of the present invention may include a memory cell array 110, a memory controller 120, and an ECC circuit 130.

The memory cell array 110 may include a plurality of memory cells (not shown) each disposed in areas where a plurality of first signal lines and a plurality of second signal lines intersect. For example, the first signal lines may be bit lines, and the second signal lines may be word lines. Additionally, each of the plurality of memory cells may be a single level cell (SLC) that stores one bit, or a multi-level cell (MLC) that can store at least 2 bits of data. there is.

For example, among a plurality of words, one word may include M bits (M is a positive integer). That is, each of the plurality of words can be connected to M cells.

The memory controller 120 reads data stored in the memory cell array 110 in response to a write/read request from the host, or operates the memory cell array 110 to write data to the memory cell array 110. can be controlled. Specifically, the memory controller may control program (or write), read, and erase operations for the memory cell array 110 by providing addresses, commands, and control signals to the memory cell array 110. Additionally, data to be written and read data may be transmitted and received between the memory controller 120 and the memory cell array 110.

Although not shown, the memory controller may include RAM, a host interface, and a memory interface. RAM can be used as the operating memory of the processor. The processor can control the overall operation of the memory controller. The host interface may include a protocol for exchanging data between the host and the memory controller. For example, the memory controller supports at least one of various interface protocols such as USB, MMC, PCI-E, ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI, ESDI, and IDE (Integrated Drive Electronics). It can be configured to communicate with the outside (HOST) through.

Additionally, the memory controller 120 may include an Error Correction Code (ECC) circuit. The ECC circuit 130 may perform error detection and correction operations on read data from the memory cell array 110.

The ECC circuit 130 can detect and correct error bits included in each of a plurality of words, and can have a correctable error amount. For example, when the ECC circuit 130 has 2-bit ECC, the ECC circuit 130 detects and corrects errors of 2-bit or less included in the received data, such as 1-bit errors and 2-bit errors. You can. That is, more than a 3-bit error can be treated as a defect. Additionally, when the ECC circuit 130 has 1-bit ECC, the ECC circuit 130 can only detect and correct errors of 1-bit or less, so errors of 2-bit or more can be treated as defects.

When the ECC circuit 130 has a correctable error amount of N-bits (N is a positive integer), the ECC circuit 130 may be referred to as ‘N-bit ECC’. For example, in a word containing M bits, N-bit ECC can detect and correct N errors per word. That is, out of M bits, there can be N correctable bits.

As described above, from the user's perspective, a 2-bit ECC device can detect and correct 1-bit errors and 2-bit errors, so it is possible to have a memory device that operates normally for 2-bit errors or less in a word. For reasons such as improving the quality of the device, an ECC test method may be considered in which samples with words containing 2-bit defects are treated as defective, and only samples with 1-bit defects or less per word are treated as good products.

Additionally, if all error bits in the memory cell array must be counted in an ECC test program to select defective memory cells, the time and memory burden for counting error bits increases.

Figure 2 is a diagram showing an example of applying an error detection pattern to detect an error bit.

Referring to FIG. 2, assuming that a word consisting of 8 bits has 2 error bits, a plurality of error pattern modes must be performed to determine the 2 error bits.

At this time, when a high bit ('1' bit) is recorded and the high bit is read, a defect in which the high bit cannot be recorded or read is referred to as a 'high-defect', and a low bit ( When a '0' bit) is written and a row bit is read, a defect in which the row bit cannot be written or read is referred to as a 'row-defect'.

As shown in Figure 2, assuming that among the words consisting of 8 bits, there is a high-defect (0_struck) in the 1st cell and a low-defect (1_stuck) in the 8th cell, '0' is present in all 8 bits. In the '00' error pattern mode, which writes and reads bits, and the 'FF' error pattern mode, which writes and reads '1' bits for all 8 bits, only one error bit is detected. That is, in ‘00’ error pattern mode, only cell number 8 with high-defect is detected as defective, and in ‘FF’ error pattern mode, only cell number 1 with low-defect is detected as defective.

Additionally, in the ‘0F’ error pattern mode, which records and reads ‘0’ bits from cells 1 to 4 and ‘1’ bits from cells 5 to 8, no error bits are detected at all. In the end, the two error bits are in the 'F0' error pattern mode, which records and reads '1' bits from cells 1 to 4, and '0' bits from cells 5 to 8, as shown in Figure 3. can be detected.

In other words, if a plurality of error bits exist in one word, all error bits can be checked only when all of the plurality of error pattern modes are operated.

For example, a memory device containing 64 bits per word contains 15,625 words per 1M, and assuming, for example, that the error bits are 100,000 bits, there is a burden of recording all of them in memory, which requires a lot of test time and a large amount of time. A large amount of memory is required.

Therefore, the semiconductor memory device 100 including the ECC circuit 130 according to the present invention counts error bits using the ECC test mode 200 and compares them with the critical number of error bits to determine whether the memory is in a normal state or a bad state. do. In other words, since the presence or absence of a defect can be determined based on the critical number of defects, the burden on memory can be reduced and the test time can be significantly shortened.

Figure 3 is a diagram showing the ECC test mode of the present invention.

Referring to FIG. 3, the ECC test mode 200 of the present invention uses an ECC bypass test unit 210 and an ECC error count unit 220 to determine whether a memory is in a normal state or a defective state using the critical number of error bits. may include.

At this time, among the ECC test modes 200 of the present invention, the ECC test mode in which errors of N-bit or less are determined as normal in the N-bit ECC device and errors exceeding N are determined as defective are called 'N- It can be referred to as 'bit ECC test mode', and in the same N-bit ECC device, an ECC test mode in which errors of (N-1) bits or less are judged as normal, and errors of more than N-bits are judged as defective. It may be referred to as ‘(N-1)-bit ECC test mode’ or ‘(N-1) ECC test mode’. Additionally, if even 1-bit error bit occurs regardless of ECC (ECC-off), the ECC test mode that determines the test to be in a defective state can be referred to as ‘ECC bypass test mode’.

The ECC bypass test unit 210 may determine a primary defect if one or more error bits are detected. That is, the ECC bypass test unit 210 may use the ECC bypass test mode. Therefore, the ECC bypass test unit 210 can determine a normal state only when no error bit is determined.

For example, in a memory having M bits per word, the ECC bypass test unit 210 can write and read bits in the first state or the second state for all M bits. Here, the bit in the first state may be a ‘1’ bit, and the bit in the second state may be a ‘0’ bit. Additionally, the bit in the first state may be a ‘0’ bit, and the bit in the second state may be a ‘1’ bit. That is, the ECC bypass mode writes and reads first-state bits or second-state bits in all M bits, and if one or more error bits are detected, it can be determined as defective.

In order to perform error bit detection using the ECC bypass test unit 210, the ECC bypass test unit 210 uses the first state bypass mode 211 and the second state bypass mode 212. It can be included.

The first state bypass mode 211 writes and reads first state bits from all of the M bits, and if one or more error bits are detected, it is determined to be a primary defect. For example, the first status bit may be a ‘1’ bit or a ‘0’ bit.

For example, if the first state bypass mode 211 is a bypass mode using the '1' bit, the first state bypass mode 211 is referred to as '#FF ECC bypass mode', and the '0' bit is referred to as '#FF ECC bypass mode'. In the case of a bypass mode using , the first state bypass mode 211 may be referred to as '#00 ECC bypass mode'.

For example, when the first state bypass mode 211 has a #FF ECC bypass mode, the first state bypass mode 211 writes and reads ‘1’ bit in all M bits per word. At this time, if one or more error bits are found among the M bits, it is determined as a primary defect. Additionally, when the first state bypass mode 211 has a #00 ECC bypass mode, the first state bypass mode 211 writes and reads ‘0’ bits in all M bits per word. At this time, if one or more error bits are found among the M bits, it is determined as a primary defect.

The second state bypass mode 212 writes and reads second state bits from all of the M bits, and if one or more error bits are detected, it is determined to be a primary defect. For example, the second status bit may be a ‘1’ bit or a ‘0’ bit.

For example, if the first state bypass mode 211 is a bypass mode using a ‘1’ bit, the second state bypass mode 212 may be a bypass mode using a ‘0’ bit. Additionally, when the first state bypass mode 211 is a bypass mode using a ‘0’ bit, the second state bypass mode 212 may be a bypass mode using a ‘1’ bit.

That is, when the first state bypass mode 211 is operated in the #FF ECC bypass mode, the second state bypass mode 212 can be operated in the #00 ECC bypass mode, and the first state bypass mode 212 is operated in the #00 ECC bypass mode. When mode 211 is operated in #00 ECC bypass mode, the second state bypass mode 212 may be operated in #FF ECC bypass mode.

At this time, the operation of the second state bypass mode 212 passes the first state bypass mode 211 because no error bit is detected in the operation of the first state bypass mode 211, that is, it is determined to be normal. ) can be performed on one word. Additionally, if an error bit is not detected in the second state bypass mode 212, the test may be terminated and the final normal state (good product) may be determined.

That is, the ECC bypass test unit 210 determines normal or first defective using the first state bit in the first state bypass mode 211, and the word that passed the first state bypass mode 211 The final normal state or the first defect can be determined using the second state bit in the second state bypass mode 212.

For example, when the first state bypass mode 211 is operated in #FF ECC bypass mode, '1' bit is written and read in all M bits per word to determine normal or primary defect, and normal The second state bypass mode 212 operates in the #00 ECC bypass mode for the word determined to be the final normal state or the first defect.

The ECC error counter 220 detects one or more error bits that are determined to be defective by the ECC bypass test unit 210, that is, in the first state bypass mode 211 or the second state bypass mode 212. A test can be performed on words that are determined to be primary defects.

Additionally, the ECC error count unit 220 can write and read bits in the first state or second state among all M bits, and count bits determined to be error bits to determine a normal state or a defective state.

The ECC error count unit 220 counts error bits for words determined to be first defective in the ECC bypass test unit 210 and uses a first state count mode 221 to determine a normal state or a defective state. It may include a second state count mode 222 and an integrated count mode 223.

The first state count mode 221 detects a first error bit by writing and reading first state bits from all of the M bits, and counts the detected first error bits to determine a normal or defective state. For example, the first status bit may be a ‘1’ bit or a ‘0’ bit.

For example, when the first state bit in the first state count mode 221 is bit '1', the first state count mode 221 is referred to as '#FF ECC count mode', and when bit '0' is used. , the first state count mode 221 may be referred to as '#00 ECC count mode'.

In addition, in an N-bit ECC device, the count mode that determines errors of (N-1) bits or less as normal and errors of N-bit or more as defective is called '#FF (N-1)ECC count mode'. Alternatively, it may be referred to as '#00 (N-1)ECC count mode'.

For example, when the first state count mode 221 has a #FF (N-1)ECC count mode, the first state count mode 221 records and reads '1' bit in all M bits per word. do. At this time, if more than N error bits are detected among the M bits, the corresponding word is determined to be in a final defective state and the test is terminated. However, if (N-1) or less error bits are detected among the M bits, it is determined as normal (Pass), and the detected error bits are counted. At this time, (N-1) or less error bits detected through the first state count mode 221 are referred to as ‘first error bits.’ That is, the first state count mode 221 counts the number of first error bits (Fail Bit Count1, FBC1).

Additionally, when the first state count mode 221 has a #00 (N-1) ECC count mode, the first state count mode 221 writes and reads '0' bits to all M bits per word. . #FF (N-1)ECC count mode Similarly, if more than N error bits are detected among M bits, it is determined as a final defective state and the test is terminated. If (N-1) or less error bits are detected among the M bits, it is determined as normal (Pass), and the detected error bits are counted.

That is, the first state count mode 221 can use #FF (N-1)ECC count mode or #00 (N-1)ECC count mode, and when N or more error bits are detected, it enters the final defective state. If a decision or (N-1) primary error bits are detected, the process passes to the next step, the second state count mode 222, and the primary error bits are counted.

The second state count mode 222 detects a second error bit by writing and reading second state bits from all of the M bits, and counts the detected second error bits to determine a normal or defective state. For example, the second status bit may be a ‘1’ bit or a ‘0’ bit.

For example, if the first state count mode 221 is a count mode using a ‘1’ bit, the second state count mode 222 may be a count mode using a ‘0’ bit. Additionally, when the first state count mode 221 is a count mode using a ‘0’ bit, the second state count mode 222 may be a count mode using a ‘1’ bit.

That is, when the first state count mode 221 is operated in the #FF (N-1) ECC count mode, the second state count mode 222 can be operated in the #00 (N-1) ECC count mode, , when the first state count mode 221 is operated in the #00 (N-1)ECC count mode, the second state count mode 222 may be operated in the #FF (N-1)ECC count mode.

At this time, the operation of the second state count mode 222 is determined to be normal when (N-1) or less error bits are detected in the first state count mode 221 operation. It can be performed on words that have passed.

For example, when the first state count mode 221 operates in #FF (N-1) ECC count mode and the second state count mode 222 operates in #00 (N-1) ECC count mode, The second state count mode 222 writes and reads '0' bits in all M bits per word, and determines a final defective state when more than N error bits are detected among the M bits. In addition, if (N-1) or less error bits are detected among the M bits, it is determined as normal (Pass), and the detected error bits are counted. At this time, (N-1) or less error bits detected through the second state count mode 222 are referred to as ‘second error bits.’ That is, the second state count mode 222 counts the number of second error bits (Fail Bit Count2, FBC2).

The integrated count mode 223 adds the number of first error bits (FBC1) and the number of second error bits (FBC2) and determines a normal state or a defective state using the summed number of error bits.

That is, the integrated count mode 223 is the number of first error bits (FBC1) counted in the first state count mode 221 and the number of second error bits counted in the second state count mode 222 (FBC2). By adding up, the final normal state or defective state can be determined based on the number of critical error bits. At this time, the critical number of error bits may be (N-1) or less error bits. For example, if the number of error bits calculated by adding the number of first error bits (FBC1) and the number of second error bits (FBC2) is more than N, the word will be It is judged to be in a final defective state. If the number of error bits calculated by adding the number of first error bits (FBC1) and the number of second error bits (FBC2) is (N-1) or less, it is included in (N-1), which is the critical number of error bits. Therefore, the word is determined to be in the final normal state and the test is terminated.

Figure 4 is a flowchart briefly showing the test method of the ECC test mode of the present invention.

FIG. 5 is a flow chart showing the test method shown in FIG. 4.

Referring to Figures 4 and 5, the test method using the ECC test mode 200 of the present invention records bits in the first state or second state in all M bits using the ECC bypass test unit 210. and reading to determine a normal state or a first bad word (S310), and using the ECC error count unit 220 to target the word determined to be the first bad word in the ECC bypass test unit 210. It includes a step (S320) of writing and reading bits in the first state or second state in all M bits, and counting bits determined to be error bits to determine a normal state or a defective state.

In the step (S310) of determining a defective cell using the ECC bypass test unit 210, as shown in FIG. 3, the first state bit ('1' bit) is written and read in all M bits, Performing a first state bypass mode (#FF ECC bypass mode) 211 that determines a word to be defective when one or more error bits are detected, and a word determined to be in a normal state in the first state bypass mode 211 Targeting, the second state bypass mode (#00 ECC bypass mode) records and reads the second state bit ('0' bit) in all M bits, and determines it as defective when one or more error bits are detected. ) may include performing (212).

That is, if one or more error bits are found in the first state bypass mode, the corresponding word is determined to be failed and the ECC error count unit 220 is performed. If one or more error bits are not found in the first state bypass mode, the corresponding word is determined to be normal (pass), and the second state bypass mode 212 is performed.

If one or more error bits are found in the second state bypass mode 212, the corresponding word is determined to be failed and the ECC error count unit 220 is performed. If one or more error bits are not found, the corresponding word is determined to be normal (pass), the final normal state is determined, and the test is terminated. At this time, it does not matter if the test is performed using bit ‘0’ as the first state bit in the first state bias mode, and using bit ‘1’ as the second state bit in the second state bias mode.

The step (S320) of determining a defective cell using the ECC error counter 220 is performed on words determined to be defective by the ECC bypass test unit 210, and counts the number of critical error bits to determine whether the cell is in the normal state or Defect status can be determined. Additionally, in a semiconductor memory device including an N-bit ECC circuit, the ECC error counter 220 may use an (N-1)-bit ECC test mode.

First, the first state count mode (#FF (N-1)ECC count mode) 221 is performed on words determined to be defective in the ECC bypass test unit 210. Accordingly, if more than (N-1) error bits are detected, the corresponding word is determined to be failed, is determined to be in a final failed state, and the test is terminated.

If (N-1) or less first error bits are detected in the first state count mode 221, the first error bits are counted, and it is determined to be normal (Pass), and the second state count mode 222 is activated. It is carried out.

In the same way, the second state count mode (#00 (N-1)ECC count mode) 222 is performed, and in the second state count mode 222, no more than (N-1) second error bits are detected. When detected, the second error bit is counted, it is determined to be normal (Pass), and the integrated count mode 223 is performed.

The word that passed the second state count mode 222 is calculated by adding the number of first error bits (FBC1) and the number of second error bits (FBC2) in the integrated count mode 223 and using the threshold number of error bits. Determine the final normal state or bad state.

For example, when testing is performed using the (N-1)-bit ECC test mode in a device including an N-bit (N=2) ECC circuit using the ECC test mode 200 shown in FIG. , If one or more error bits are not detected through the first state bypass mode (#FF ECC bypass mode) 211 and the second bypass mode (#00 ECC bypass mode) of the ECC bypass mode, normal The status is determined and the test ends. If one or more error bits are detected, the corresponding word is tested in the ECC error counter 220.

If two or more error bits are detected in the first state count mode (#FF (N-1)ECC count mode) 221 of the ECC error count unit 220, the corresponding word is determined to be in a final failure state. The test is terminated, and if there is less than one error bit, that is, no error bit is detected, or one error bit is detected, the corresponding word is determined to be normal (Pass), and the first detected error bit is counted.

For words determined to be normal in the first state count mode (#FF (N-1)ECC count mode) 221, the second state count mode (#00 (N-1)ECC count mode) 222 is performed. . If two or more error bits are detected in the second state count mode (#00 (N-1)ECC count mode) 222, the corresponding word is determined to be a final failure state and the test is terminated, and if an error If there is one or less bits, that is, no error bit is detected, or one error bit is detected, the corresponding word is determined to be normal (Pass), and the detected second error bit is counted.

For words determined to be normal in the second state count mode (#00 (N-1)ECC count mode) 222, the integrated count mode 223 is performed. The integrated count mode 223 sets the critical number of error bits to 1 (N-1) or less, and when the sum of the number of first error bits (FBC1) and the number of second error bits (FBC2) is 1 or less. The final normal state is determined and the test is terminated. If the sum of the number of error bits is 2, the final defective state is determined and the test is terminated.

That is, when testing is performed using the (N-1)-bit ECC test mode in a device including an N-bit (N=2) ECC circuit, the number of first error bits and the number of second error bits are The sum is 1 or 2. If there are no error bits in the word, it will be passed in ECC bypass mode and determined as the final normal state. If there are more than 3 error bits, the word will be in the first state count mode 221 or the second state count. This is because it is determined to be in a defective state in mode 222.

Accordingly, in the integrated count mode 223, the sum of the number of error bits is 1 or 2, of which 2 are determined to be in a defective state and 1 of which is determined to be in a normal state. That is, testing can be performed simply and quickly using the critical number of error bits through the ECC bypass test unit 210 and the ECC error counter 220.

Figure 6 is a diagram showing an example of determining defects using the 2-bit ECC test mode of the present invention.

Figure 7 is a diagram showing another example of determining defects using the 2-bit ECC test mode of the present invention.

Here, Figure 6 shows a test method when one error bit exists in a 16-bit word, and Figure 7 shows a test method when two error bits exist in a 16-bit word.

First, referring to FIG. 6, assuming that among the words consisting of 16 bits, cell 12 has a high defect, the ECC bypass test unit 210 is first performed. Since high-defect of cell 12 is detected in the first state bypass mode (#FF ECC bypass mode) 211 of the ECC bypass test unit 210, it is determined to be defective. In addition, even if the first state bypass mode 211 is performed using the first state bypass mode (#00 ECC bypass mode) 211 using the '0' bit, the first state bypass mode (# Although the error bit is not detected in the 00 ECC bypass mode (211), the high-failure of cell 12 is detected in the second state bypass mode (#FF ECC bypass mode) (212), so the final primary defect is It is judged as Accordingly, the corresponding word is tested using the ECC error counter 220.

First, in the first state count mode (#FF (N-1)ECC count mode) 221, the high-failure of cell 12 is detected as the first error bit, and one error bit is counted as the first error bit. . Since only one error bit is detected, it is determined to be normal and the second state count mode (#00 (N-1)ECC count mode) 222 is performed.

Since error bits are not detected in the second state count mode (#00 (N-1)ECC count mode) 222, the second error bits are counted as 0, and it is determined to be normal, so the integrated count mode (FBC1+FBC2) (223) is performed.

In integrated count mode (FBC1+FBC2) 223, since the sum of the number of first error bits (FBC1) and the number of second error bits (FBC2) is 1, the corresponding word is determined to be in the final normal state and the test is ended. do.

Referring to FIG. 7, if it is assumed that among the words consisting of 16 bits, cell number 5 has a low defect and cell number 12 has a high defect, the ECC bypass test unit 210 is first performed. Since high-defect of cell 12 is detected in the first state bypass mode (#FF ECC bypass mode) 211 of the ECC bypass test unit 210, it is determined to be defective. In addition, even if the first state bypass mode 211 is performed using the first state bypass mode (#00 ECC bypass mode) 211 using the '0' bit, low-defect in cell 5 Because it is detected, it is ultimately judged as a primary defect. Accordingly, the corresponding word is tested using the ECC error counter 220.

First, in the first state count mode (#FF (N-1)ECC count mode) 221, the high-failure of cell 12 is detected as the first error bit, and one error bit is counted as the first error bit. . Since only one error bit is detected, it is determined to be normal and the second state count mode (#00 (N-1)ECC count mode) 222 is performed.

In the second state count mode (#00 (N-1)ECC count mode) 222, a row-defect in cell 5 is detected as a second error bit, and one error bit is counted as the second error bit. Since only one error bit is detected, it is determined to be normal and the integrated count mode (FBC1+FBC2) (223) is performed.

In integrated count mode (FBC1+FBC2) 223, since the sum of the number of first error bits (FBC1) and the number of second defective errors (FBC2) is 2, the corresponding word is determined to be in the final defective state and the test is ended. do.

As described above, a semiconductor memory device including an ECC circuit and a test method using the same can determine good or defective products based on the number of critical error bits using the ECC test mode 200 of the ECC circuit, thereby reducing the burden on the memory. It can be reduced and the configuration of the device can be simplified. Additionally, since the ECC test mode 200 can determine whether a product is good or defective by simply counting the critical number of defects, the test time can be significantly shortened.

Meanwhile, the embodiments of the present invention disclosed in the specification and drawings are merely specific examples to aid understanding and are not intended to limit the scope of the present invention. It is obvious to those skilled in the art that in addition to the embodiments disclosed herein, other modifications based on the technical idea of the present invention can be implemented.

100: semiconductor memory device 110: memory cell array
120: memory controller 130: ECC circuit
200: ECC test mode 210: ECC bypass test unit
211: first state bypass mode 212: second state bypass mode
220: ECC error count unit 221: First state count mode
222: Second state count mode 223: Integrated count mode

Claims (15)

A memory cell array including M bits (M is a positive integer) in one word among a plurality of words connected to the cell array; and
It includes an N-bit ECC circuit that detects and corrects error bits of up to N-bits (N is a positive integer) of the memory cell array,
The ECC circuit includes an ECC test mode that counts error bits among the M bits of the memory cell array and compares the counted error bits with a critical number of error bits to determine a normal state or a defective state,
The ECC test mode is,
an ECC bypass test unit that records first-state or second-state bits in all of the M bits and reads them to determine a normal state or a primary defect; and
An ECC error count unit that writes and reads bits in the first state or the second state in all of the M bits and counts bits determined to be error bits to determine a normal state or a defective state,
The ECC error count unit,
a first state count mode for detecting a first error bit by writing and reading the first state bits in all of the M bits, and counting the detected first error bits;
a second state count mode for detecting a second error bit by writing and reading the second state bits in all of the M bits, and counting the detected second error bits; and
A semiconductor memory device including an ECC circuit including an integrated count mode that adds the number of the first error bits and the number of the second error bits and determines a normal state or a defective state using the summed number of error bits. . delete According to paragraph 1,
A semiconductor memory device including an ECC circuit, wherein the operation of the ECC error count unit is performed on a word determined to be primary defective by the ECC bypass test unit. The method of claim 1, wherein the ECC bypass test unit,
a first state bypass mode that writes and reads bits of the first state in all of the M bits and determines the first defect when one or more error bits are detected; and
A semiconductor memory device comprising an ECC circuit including a second state bypass mode that writes and reads bits of the second state in all of the M bits and determines the first defect when one or more error bits are detected. According to clause 4,
A semiconductor memory device including an ECC circuit, wherein the second state bypass mode operation is performed on words determined to be normal in the first state bypass mode. According to clause 5,
A semiconductor memory device including an ECC circuit, wherein a word determined to be normal in the second state bypass mode is determined to be a final normal state. According to paragraph 1,
A semiconductor memory device including an ECC circuit wherein the ECC error count unit determines a final defective state for a word in which (N-1) error bits have occurred. delete According to paragraph 1,
The first state count mode and the second state count mode determine as normal only for words in which (N-1) or less first error bits are detected. According to paragraph 1,
A semiconductor memory device including an ECC circuit, wherein the operation of the second state count mode is performed on words determined to be normal in the first state count mode. ECC test using an N-bit ECC circuit that detects and corrects error bits of up to N-bits (N is a positive integer) from a memory cell array containing M bits (M is a positive integer) in one word. running the mode; and
Counting error bits of the memory cell array using the ECC test mode and comparing the counted error bits with a critical number of error bits to determine a normal state or a defective state,
The step of using the ECC test mode is,
Writing first state or second state bits to all of the M bits using an ECC bypass test unit and reading them to determine a normal state or a first bad word; and
For the word determined to be the first defect in the ECC bypass test unit, bits in the first state or the second state are recorded and read in all of the M bits using an ECC error count unit, and converted to error bits. Counting the determined bits to determine a normal state or a defective state,
The step of using the ECC error count unit is,
performing a first state count mode of detecting (N-1) first error bits by writing and reading the first state bits in all of the M bits, and counting the detected first error bits;
performing a second state count mode of detecting (N-1) second error bits by writing and reading the second state bits in all of the M bits, and counting the detected second error bits; and
A semiconductor comprising an ECC circuit including performing an integrated count mode of summing the number of the first error bits and the number of the second error bits and determining a normal state or a defective state using the summed number of error bits. How to test memory devices. delete The method of claim 11, wherein using the ECC bypass test unit comprises:
A first step of writing and reading bits in the first state in all of the M bits and determining a first defect if one or more error bits are detected; and
A second step of writing and reading bits in the second state in all of the M bits for a word determined to be in a normal state in the first step and determining it as defective when one or more error bits are detected. Test method for semiconductor memory devices containing ECC circuits. delete According to clause 11,
A test method for a semiconductor memory device including an ECC circuit, wherein the operation of the second state count mode is performed on words determined to be normal in the first state count mode.