KR20240028176A - Apparatus for inspecting semi-conductor and system comprising the same - Google Patents

Abstract

The technical idea of the present invention is to include a socket unit including a plurality of sockets on which semiconductor devices are mounted; and a module portion connected to the socket and providing a signal to the socket, wherein the module portion is connected to a different socket and configured to transmit a signal to the socket. The plurality of switches are different from each other. a plurality of OR gates connected to the input terminals of the OR gates and configured to transmit a signal to the switch, and a plurality of output terminals connected to first input terminals of the different OR gates, and transmitting signals to the plurality of OR gates. A semiconductor device inspection device including a demux configured to transmit is provided.

Description

Semiconductor device inspection device and system including the same {Apparatus for inspecting semi-conductor and system comprising the same}

The present invention relates to a semiconductor device inspection device, and more specifically, to a semiconductor device inspection device that can include more sockets by reducing the number of channels.

In the production of semiconductor devices, a burn-in test is performed to measure the characteristics of each semiconductor device under harsher conditions than the general use environment (e.g., room temperature) (e.g., in a chamber where a constant temperature of 125°C or higher is maintained). By mounting the semiconductor device on a burn-in board designed for The purpose is to detect potential defects in semiconductor devices that may occur after they are shipped by quickly detecting initial defects in semiconductor devices.

Then, after the burn-in test is completed, an operation test is performed on the semiconductor device that passed the burn-in test. The operation test refers to a test performed after mounting the semiconductor device on an application set (application set) or mounting set. That is, the burn-in test and the operation test are separated from each other and performed in different devices. Therefore, it takes a lot of time to test semiconductor devices.

The problem to be solved by the present invention is to provide a semiconductor device inspection device that can provide signals for each semiconductor device.

The problem to be solved by the present invention is to provide a semiconductor device inspection device with a reduced number of channels for controlling semiconductor devices.

In addition, the problem to be solved by the technical idea of the present invention is not limited to the problems mentioned above, and other problems can be clearly understood by those skilled in the art from the description below.

In order to solve the above problem, the technical idea of the present invention is to include a socket unit including a plurality of sockets on which semiconductor devices are mounted; and a module portion connected to the socket and providing a signal to the socket, wherein the module portion is connected to a different socket and configured to transmit a signal to the socket. The plurality of switches are different from each other. a plurality of OR gates connected to the input terminals of the OR gates and configured to transmit a signal to the switch, and a plurality of output terminals connected to first input terminals of the different OR gates, and transmitting signals to the plurality of OR gates. A semiconductor device inspection device including a demux configured to transmit is provided.

In order to solve the above problem, the technical idea of the present invention is to include a socket unit including 2 ^N sockets on which semiconductor devices are mounted; and a module part connected to the socket and providing a signal to the socket; wherein the module part is connected to different sockets and configured to transmit signals to the sockets, 2 ^N switches, the 2 ^N different switches 2 ^{N OR gates connected to at least one input terminal of the switches and configured to transmit signals to the 2 N switches} , and 2 ^N output terminals connected to the first input terminals of the different 2 ^N OR gates. A demux configured to transmit a signal to the ^2N OR gates, a first channel connected to a second input terminal of the ^2N OR gates and transmitting the same signal to the ^2N OR gates, and It includes N second channels connected to different input terminals of the demux to transmit signals, and the demux forms 2 ^N output values, and the 2 ^N output values are connected to different first input terminals of the OR gate. and the 2 ^N OR gates are connected to different switches, the 2 ^N switches are connected to different sockets, and N is an integer of 2 or more.

In order to solve the above problem, the technical idea of the present invention is to include a burn-in chamber capable of controlling the voltage magnitude of the test signal input from the host and the internal temperature; and a burn-in board mounted in the burn-in chamber and receiving the test signal from the burn-in chamber, wherein the burn-in board includes a socket portion including a plurality of sockets on which semiconductor devices are mounted. and a module portion connected to the socket and providing a signal to the socket, wherein the module portion is connected to a different socket and configured to transmit a signal to the socket. The plurality of switches are different from each other. a plurality of OR gates connected to the input terminals of the OR gates and configured to transmit a signal to the switch, and a plurality of output terminals connected to first input terminals of the different OR gates, and transmitting signals to the plurality of OR gates. Provided is a semiconductor device inspection system comprising a demux configured to transmit.

The semiconductor device inspection device according to the technical idea of the present invention can provide signals to each or all semiconductor devices, so that more accurate inspection values can be obtained when inspecting semiconductor devices.

In the semiconductor device inspection device according to the technical idea of the present invention, the number of channels for controlling switches allocated to each semiconductor device is small, so the number of sockets mounted on one board can be increased.

1 is a block diagram schematically showing a semiconductor inspection device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram schematically showing the semiconductor inspection device of FIG. 1.
FIG. 3 shows an example of a truth table of demux of the semiconductor inspection device of FIG. 1.
Figure 4 is a circuit diagram schematically showing the operation of a semiconductor inspection device according to an embodiment of the present invention.
Figure 5 is a circuit diagram schematically showing the operation of a semiconductor inspection device according to an embodiment of the present invention.
Figure 6 is a block diagram schematically showing a semiconductor inspection device according to an embodiment of the present invention.
FIG. 7 is a circuit diagram schematically showing the semiconductor inspection device of FIG. 6.
8 is a block diagram schematically showing a semiconductor inspection device according to an embodiment of the present invention.

Since these embodiments can be subject to various changes and have various forms, some embodiments will be illustrated in the drawings and described in detail. However, this is not intended to limit the present embodiments to the specific disclosure form.

1 is a block diagram schematically showing a semiconductor inspection device according to an embodiment of the present invention. FIG. 2 is a circuit diagram schematically showing the semiconductor inspection device of FIG. 1.

Referring to FIGS. 1 and 2 , a semiconductor inspection device may include a socket portion and a module portion.

The socket unit 200 may include a plurality of sockets 210. In one embodiment, the socket unit 200 may include a plurality of sockets 210 arranged in an A x B grid. The socket 210 may be equipped with a semiconductor device. The socket unit 200 may include metal wires that electrically connect the plurality of sockets 210 to each other. In one embodiment, the socket unit 200 may include 256 sockets 210 in a 16 x 16 grid. In one embodiment, the socket unit 200 may include 320 sockets 210 in a 20 x 16 grid.

The module unit 100 may include a plurality of switches 110, a plurality of OR gates 120, a demux 130, a first channel 140, and a plurality of second channels 150. .

A plurality of switches 110 of the module unit 100 may be connected to the socket 210. Specifically, the output terminal of the switch may be connected to the input terminal of the socket 210. In some embodiments, the number of switches and the number of sockets 210 may be the same. A plurality of switches 110 may be connected to different sockets 210 . In other words, a switch is connected to each socket 210, so that a plurality of sockets 210 can be individually controlled. In one embodiment, when a HIGH signal is input to the switch, the HIGH signal may be transmitted to the socket 210. When a LOW signal is input to the switch, the LOW signal may be transmitted to the socket 210.

A plurality of OR gates 120 of the module unit 100 may be connected to a plurality of switches 110. Specifically, a plurality of OR gates 120 may be connected to a plurality of different switches 110. In other words, the output terminal of the OR gate and the input terminal of the switch can be connected. In some embodiments, the number of OR gates and the number of switches may be the same.

The plurality of OR gates 120 of the module unit 100 may each include a first input terminal and a second input terminal. In some embodiments, when a HIGH signal is input to the first or second input terminal of the OR gate, the OR gate may transmit the HIGH signal to the input terminal of the switch. When the OR gate receives a LOW signal from the first and second input terminals, it can transmit the LOW signal to the input terminal of the switch.

The first channel 140 of the module unit 100 may be connected to the OR gate of the module unit. Specifically, the first channel 140 may be connected to a plurality of OR gates 120. In other words, the first channel 140 may be connected to the second input terminal of the plurality of OR gates 120. The first channel 140 may input a HIGH signal or a LOW signal to a plurality of OR gates 120. That is, the first channel 140 can input the same signal to all OR gates. In some embodiments, when the first channel 140 inputs a HIGH signal to the plurality of OR gates 120, the plurality of OR gates 120 all output a HIGH signal, and all sockets 210 are connected through the switch. ) A HIGH signal can be transmitted.

The demux 130 of the module unit 100 may be connected to a plurality of OR gates 120. Specifically, the plurality of output terminals of the demux 130 may be connected to the first input terminal of the plurality of OR gates 120. That is, the plurality of output terminals of the demux 130 may be connected to the first input terminals of the plurality of different OR gates 120.

The plurality of second channels 150 of the module unit 100 may be connected to the demux 130 of the module unit 100. In other words, the plurality of second channels 150 may be connected to different input terminals of the demux 130. In some embodiments, the number of second channels may be the same as the number of input terminals of the demux 130. In some embodiments, the plurality of second channels 150 may input different signals to the demux 130. The demux may form different output values depending on signals input through the second channels. The output value of the demux will be described in more detail later in FIG. 3.

The module unit 100 may include a plurality of sub-modules. For example, when the socket unit is arranged in an A x B grid, the module unit may include B sub-modules. Specifically, the first sub-module may control sockets arranged in the first row of the socket unit, and the second sub-module may control sockets arranged in the second row. In some embodiments, the sub-module may include a plurality of switches, a plurality of OR gates, a demux, a first channel, and a second channel. Different signals can be transmitted to rows where multiple sockets are arranged through the submodule. That is, a plurality of sockets arranged in one row can receive signals from the same first channel. In other words, sockets arranged in different rows can receive signals from different first channels.

The semiconductor device inspection device of the present invention can individually control sockets through a switch, allowing individual inspection of semiconductor devices. Therefore, it is possible to prevent inspection errors caused by other factors. That is, if there is a malfunctioning semiconductor device, it is possible to prevent a phenomenon that affects the results of a normally operating semiconductor device when transmitting inspection data of the malfunctioning semiconductor device.

The semiconductor device inspection device of the present invention can reduce the number of channels for controlling a plurality of sockets through demux. Through demux, 2 ^N sockets can be controlled with N channels, so the number of channels for controlling sockets can be reduced. As the number of sockets that can be controlled through the same channel increases, the number of sockets that can be placed in the socket unit can increase.

The semiconductor device inspection device of the present invention can control all or only a portion of a plurality of sockets through an OR gate. In other words, by connecting a channel that can input the same signal to the OR gate, a plurality of sockets can receive a HIGH signal at the same time.

FIG. 3 shows an example of a truth table of demux of the semiconductor inspection device of FIG. 1. Figure 4 is a circuit diagram schematically showing the operation of a semiconductor inspection device according to an embodiment of the present invention. Figure 5 is a circuit diagram schematically showing the operation of a semiconductor inspection device according to an embodiment of the present invention.

Referring to FIGS. 3 to 5 , the semiconductor inspection device may include a socket portion and a module portion. With reference to FIGS. 3 to 5 , a semiconductor inspection device including a specific number of sockets will be described. Content that overlaps with the semiconductor inspection device previously described in FIG. 1 will be omitted, and the description will focus on differences.

The socket portion may include 2 ^N sockets. In one embodiment, the socket unit 200 may include 2 ^N sockets 210 arranged in an A x B grid. The socket 210 may be equipped with a semiconductor device. The socket unit 200 may include metal wires that electrically connect each of the ^2N sockets 210.

The module unit 100 may include 2 ^N switches 110, 2 ^N OR gates 120, a demux 130, a first channel 140, and N second channels 150. there is. N may be an integer of 2 or more.

The ^2N switches 110 of the module unit 100 may be connected to the socket 210. Specifically, the output terminal of the switch may be connected to the input terminal of the socket 210. ^2N switches 110 may be connected to different sockets 210. In other words, a switch is connected to each socket 210, so that 2 ^N sockets 210 can be individually controlled.

The ^2N OR gates 120 of the module unit 100 may be connected to the ^2N switches 110. Specifically, ^2N OR gates 120 may be connected to ^2N different switches 110. In other words, the output terminal of the OR gate and the input terminal of the switch can be connected.

The first channel 140 of the module unit 100 may be connected to the OR gate of the module unit. Specifically, the first channel 140 may be connected to 2 ^N OR gates 120. In other words, the first channel 140 may be connected to the second input terminal of the 2 ^N OR gates 120. That is, the first channel 140 can input the same signal to 2 ^N OR gates.

The demux 130 of the module unit 100 may be connected to ^2N OR gates 120. Specifically, the ^2N output terminals of the demux 130 may be connected to the first input terminals of the ^2N OR gates 120. That is, the ^2N output terminals of the demux 130 may be connected to the first input terminals of the different ^2N OR gates 120.

The N second channels 150 of the module unit 100 may be connected to the demux 130 of the module unit 100. In other words, the N second channels 150 may be connected to different input terminals of the demux 130. In some embodiments, the N second channels 150 may input different signals to the demux 130. The demux 130 may generate ^2N output values according to signals input through the N second channels 150. The demux 130 can transmit 2 ^N output values to the first input terminals of the different 2 ^N OR gates 120.

Figure 3 is an example showing the truth table of the demux 130 when N is 4. According to FIG. 3, the four second channels 150 may be connected to the input terminal of the demux 130. According to the signal input through the four second channels 150, the demux 130 may transmit a HIGH signal to the OR gate from one output terminal among the 16 output terminals of the demux 130. That is, the module unit 100 can individually control 16 sockets through 4 channels. In other words, many sockets can be individually controlled through the same number of channels.

Figure 4 shows the operation of the semiconductor device inspection device when the first channel 140 transmits a LOW signal to the OR gate. Figure 5 shows the operation of the semiconductor device inspection device when the first channel 140 transmits a HIGH signal to the OR gate.

In one embodiment, the OR gate can output a HIGH signal from the output terminal when a HIGH signal is input to one input terminal. Therefore, when the first channel 140 connected to the second input terminal of the OR gate transmits the same HIGH signal to the 16 OR gates 120, the 16 OR gates transmit the HIGH signal to the different switches 110. Thus, a HIGH signal can be transmitted to all sockets 210.

In one embodiment, when a LOW signal is input to one input terminal of the OR gate, the output signal of the OR gate may vary depending on the signal input from the other input terminal. Specifically, when a LOW signal is transmitted from the first channel 140 to the second input terminal of the OR gate, the output signal of the OR gate may vary depending on the signal transmitted to the first input terminal of the OR gate connected to the demux 130. there is. In other words, when a LOW signal is transmitted from the first channel 140 to the second input terminal of the OR gate, the module unit 100 can individually control the 16 OR gates 120 through the demux 130. . That is, the module unit 100 can control all or individually the plurality of sockets 210 through the first channel 140 and the plurality of OR gates 120.

Figure 6 is a block diagram schematically showing a semiconductor inspection device according to an embodiment of the present invention. FIG. 7 is a circuit diagram schematically showing the semiconductor inspection device of FIG. 6.

Referring to FIGS. 6 and 7 , the semiconductor inspection device may include a socket portion and a module portion. Overlapping parts between the semiconductor inspection device of FIG. 6 and the semiconductor inspection device of FIG. 1 described above will be omitted, and the description will focus on the differences.

The module unit 100 includes a plurality of switches 110, a plurality of OR gates 120, a demux 130, a first channel 140, a plurality of second channels 150, and a controller 160. may include.

The controller 160 of the module unit 100 may correct the first time. The first time may be the time it takes for a signal input through the first channel 140 or the second channel 150 to be transmitted to the socket 210. In other words, the module unit 100 can correct the time it takes for a signal input through the controller 160 to be transmitted to the socket 210. In some embodiments, the signal input through the second channels 150 is transmitted to the socket 210 through the demux 130, OR gate 120, and switch 110, so that the input signal is transmitted to the socket ( 210), a delay may occur. Additionally, since the signal input through the first channel 140 is transmitted to the socket 210 through the OR gate 120 and the switch 110, a delay may occur in transmitting the input signal to the socket. By measuring the delay occurring in the signal input through the first channel 140 or the second channel 150, the module unit 100 can compensate for the first time, which is the signal delay, through the regulator 160. The semiconductor inspection device can obtain accurate inspection results by compensating for delay through the regulator 160.

Figure 8 is a block diagram schematically showing a semiconductor inspection system 1000 according to an embodiment of the present invention.

Referring to FIG. 8, a semiconductor inspection system may include a burn-in chamber, a burn-in board, and a host.

Referring to FIG. 8, the burn-in chamber 1200 may be equipped with a plurality of burn-in boards (BIBs). The burn-in chamber 1200 can adjust the voltage magnitude of the test signal input from the host 1300 and the temperature inside the burn-in chamber. For example, the burn-in chamber 1200 may set its internal temperature to be higher than room temperature in the burn-in test mode. Additionally, the burn-in chamber 1200 may provide a test signal received from the host 1300 to the burn-in board 1100 in a burn-in test mode in which high temperature or high voltage is applied to the burn-in board 1100. The burn-in chamber 1200 of the present invention can perform operational tests on a plurality of semiconductor devices (Device Under Test (DUT)) connected to sockets of the burn-in board 1100 in the burn-in test mode. Subsequently, the burn-in chamber 1200 may transmit an output value for the test signal to the host 1300.

The burn-in chamber 1200 can select defective semiconductor chips generated in the process of artificially advancing the time at which initial defects reach the burn-in board 1100 by applying severe stress, such as high temperature and high voltage, to the burn-in board 1100. Additionally, while such severe stress is applied to the burn-in board 1100, an operation test can be performed by transmitting test signals to a plurality of DUTs connected to the sockets of the burn-in board 1100. Through this, the burn-in chamber 1200 of the present invention can reduce the time spent testing a semiconductor device and also reduce the cost spent testing the semiconductor device.

The host 1300 may provide the burn-in board 1100 with test signals for testing a plurality of DUTs mounted on the burn-in board 1100 in the burn-in chamber 1200.

The host 1300 includes an operation unit, a signal output unit, and a controller. The operation unit may include a central processing unit (CPU) or a field programmable gate array (FPGA) that processes commands. FPGA is a semiconductor device that contains programmable logic blocks and programmable internal lines. Programmable logic blocks can be programmed to replicate the functions of basic logic gates, such as AND, OR, XOR, NOT, or more complex combinations of decoder or calculation functions. The calculation unit generates a test signal and delivers it to the signal output unit. The test signal may include an address, data, and command, but the present invention is not limited thereto.

The signal output unit may convert the test signal received from the calculation unit and transmit it to the burn-in board 1100. For example, the signal output unit may convert the received test signal to have a voltage magnitude between VOH and VOL and provide the converted test signal to the burn-in board 1100. Additionally, the signal output unit may separately process the address, data, and command included in the test signal, and then provide them to the burn-in board 1100.

The controller can control the operation of the calculation unit. For example, the controller may control the calculation unit to transmit commands so that the calculation unit can generate an appropriate test signal and analyze the output value from the burn-in board 1100. However, the present invention is not limited to this.

The burn-in board 1100 may include a module portion 100 and a socket portion 200. The module unit 100 and the socket unit 200 of the semiconductor inspection system of FIG. 8 overlap with the semiconductor inspection device 10 of FIG. 1 described above, and thus description thereof will be omitted. The burn-in board may be mounted in the burn-in chamber. The burn-in chamber may include a slot on which a burn-in board can be mounted. The burn-in chamber may include a plurality of slots.

So far, the present invention has been described with reference to the embodiments shown in the drawings, but these are merely illustrative, and those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom. will be. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the attached patent claims.

10: Semiconductor device inspection device 1000: Semiconductor device inspection system
100: module part 110: switch
120: OR gate 130: Demux
140: 1st channel 150: 2nd channel
160: regulator 200: socket portion
210: Socket 1100: Burn-in board
1200: Burn-in chamber 1300: Host

Claims (10)

A socket portion including a plurality of sockets on which semiconductor devices are mounted; and
a module unit connected to the socket and providing a signal to the socket;
including
The module unit is connected to different sockets and includes a plurality of switches configured to transmit signals to the sockets,
A plurality of OR gates connected to different input terminals of the plurality of switches and configured to transmit signals to the switches, and
A demux comprising a plurality of output terminals connected to first input terminals of the plurality of different OR gates, and configured to transmit signals to the plurality of OR gates.
A semiconductor device inspection device including: According to claim 1,
The number of sockets and the plurality of switches is the same,
The plurality of switches are connected to different sockets.
A semiconductor device inspection device characterized by: According to claim 1,
The number of the plurality of switches and the plurality of OR gates are the same,
The module unit includes a first channel connected to second input terminals of the plurality of OR gates and transmitting the same signal to the plurality of OR gates,
The plurality of OR gates are connected to different switches to transmit signals.
A semiconductor device inspection device characterized by: According to claim 1,
The module unit is connected to different input terminals of the demux and includes a plurality of second channels for transmitting signals,
The demux forms a plurality of output values according to signals input through the plurality of second channels, and transmits the plurality of output values to the first input terminals of the plurality of different OR gates.
A semiconductor device inspection device characterized by: According to clause 4,
The module unit includes N second channels,
The demux forms 2 ^N output values,
A semiconductor device inspection device wherein N is an integer of 2 or more. According to claim 1,
The module unit includes a first channel connected to second input terminals of the plurality of OR gates; and
A plurality of second channels connected to different input terminals of the demux,
The module unit includes a controller that corrects a first time at which a signal input through the first channel or the second channel is transmitted to the socket;
A semiconductor device inspection device comprising: A socket portion including 2 ^N sockets on which semiconductor devices are mounted; and
a module unit connected to the socket and providing a signal to the socket;
including
The module unit is connected to different sockets and includes 2 ^N switches configured to transmit signals to the sockets,
2 ^N OR gates connected to at least one input terminal of the 2 N switches and ^{configured to transmit a signal to the 2 N switches} , and
A demux comprising 2 ^N output terminals connected to first input terminals of the 2 ^N OR gates, and configured to transmit signals to the 2 ^N OR gates,
A first channel connected to the second input terminal of the 2 ^N OR gates and transmitting the same signal to the 2 ^N OR gates, and
N second channels connected to different input terminals of the demux to transmit signals
Contains,
The demux forms 2 ^N output values and transmits the 2 ^N output values to different first input terminals of the OR gate,
The 2 ^N OR gates are connected to different switches,
The 2 ^N switches are connected to different sockets,
A semiconductor device inspection device wherein N is an integer of 2 or more. a burn-in chamber capable of controlling the voltage level of the test signal input from the host and the internal temperature; and
a burn-in board mounted in the burn-in chamber and receiving the test signal from the burn-in chamber;
Including,
The burn-in board includes a socket portion including a plurality of sockets on which semiconductor devices are mounted; and
It is connected to the socket and includes a module unit that provides a signal to the socket.
The module unit is connected to different sockets and includes a plurality of switches configured to transmit signals to the sockets,
A plurality of OR gates connected to different input terminals of the plurality of switches and configured to transmit signals to the switches, and
A demux comprising a plurality of output terminals connected to first input terminals of the plurality of different OR gates, and configured to transmit signals to the plurality of OR gates.
A semiconductor device inspection system comprising: According to clause 8,
The burn-in chamber includes a plurality of slots,
The plurality of slots are configured to be combined with the burn-in board.
Features a semiconductor device inspection system. According to clause 8,
The socket portion includes 2 ^N sockets,
The module unit includes 2 ^N switches and 2 ^N OR gates,
The module unit is connected to the second input terminal of the plurality of OR gates and transmits the same signal to the plurality of OR gates, and
Includes N second channels connected to different input terminals of the demux to transmit signals,
The demux forms 2 ^N output values and transmits the 2 ^N output values to first input terminals of the plurality of different OR gates,
The plurality of OR gates are connected to different switches,
The plurality of switches are connected to different sockets,
A semiconductor device inspection system wherein N is an integer of 2 or more.

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