KR20240007048A - Semiconductor memory device performing a multiplication and accumulation operation - Google Patents

Abstract

A semiconductor memory device according to the present technology includes a cell array including a plurality of memory cells connected between a bit line and a source line; An arithmetic control circuit that provides a constant current between the bit line and the source line during arithmetic operation; and an output circuit including an arithmetic capacitor whose charge amount changes by the arithmetic operation, wherein the amount of charge moving between the bit line and the source line during the arithmetic operation is the value stored in the memory cell corresponding to the first data and the second data. Correspondingly, it varies depending on the word line voltage connected to the memory cell.

Description

Semiconductor memory device that performs MAC operation {SEMICONDUCTOR MEMORY DEVICE PERFORMING A MULTIPLICATION AND ACCUMULATION OPERATION}

This technology relates to a semiconductor memory device that performs multiply and accumulate (MAC) operations.

NEURAL NETWORK is widely used in artificial intelligence fields such as image recognition and self-driving cars.

A neural network includes an input layer, an output layer, and one or two or more internal layers in between.

Each layer contains one or two or more neurons, and neurons included in adjacent layers are connected to each other through synapses, and each synapse is assigned a weight.

The weights assigned to synapses are determined through training operations.

The value of the neuron included in the input layer is determined from the input value, and the value of the neuron included in the inner layer and output layer is obtained from the result of the operation using the value of the neuron included in the previous layer and the weight assigned to the synapse.

In neural network operations, multiplication and accumulation (MAC) operations are frequently performed, and the importance of computational circuits that can perform them efficiently is increasing.

KR 10-2021-0029070 A US 11,061,646 B2 KR 10-2011-0111180 A

This technology provides a semiconductor memory device that performs MAC operations.

This technology provides a semiconductor memory device that can perform MAC operations without changing the structure of the cell array.

This technology provides a semiconductor memory device that supports multi-bit data and performs MAC operations.

A semiconductor memory device according to an embodiment of the present invention includes a cell array including a plurality of memory cells connected between a bit line and a source line; An arithmetic control circuit that provides a constant current between the bit line and the source line during arithmetic operation; and an output circuit including an arithmetic capacitor whose charge amount changes by the arithmetic operation, wherein the amount of charge moving between the bit line and the source line during the arithmetic operation is the value stored in the memory cell corresponding to the first data and the second data. Correspondingly, it varies depending on the word line voltage connected to the memory cell.

A semiconductor memory device according to an embodiment of the present invention includes a flash memory cell array including a first NAND string connected to a first bit line and a second NAND string connected to a second bit line; An output circuit including a first operation capacitor connected to a first bit line, a second operation capacitor connected to a second bit line, and a voltage calculation circuit that calculates the charging voltage of the first operation capacitor and the charging voltage of the second operation capacitor. ; and an operation control circuit that provides a constant current to the first bit line and the second bit line during an operation operation, wherein the first NAND string and the second NAND string store input data, and a weight is applied to the first NAND string during the operation operation. A word line voltage is provided according to first weight data corresponding to a positive weight among the data, and a word line voltage is provided to the second NAND string according to second weight data corresponding to a negative weight among the weight data.

This technology can perform the MAC operation function without changing the structure of a conventional memory cell array.

A semiconductor memory device using this technology can perform MAC operation operations using multi-bit data.

A semiconductor memory device using this technology can perform MAC calculation operations considering negative weights.

1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention.
2 is a circuit diagram showing a semiconductor memory device according to an embodiment of the present invention.
3 is an explanatory diagram showing a read operation of a NAND flash memory device.
4 is a waveform diagram showing a MAC operation operation of a semiconductor memory device according to an embodiment of the present invention.
5 is a circuit diagram showing a semiconductor memory device according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be disclosed with reference to the attached drawings.

Figure 1 is a block diagram showing a semiconductor memory device 1000 according to an embodiment of the present invention.

Hereinafter, a semiconductor memory device will be described using a NAND flash memory device as an example.

The semiconductor memory device 1000 includes a flash cell array 10, an input circuit 20, an output circuit 30, a source line control circuit 40, and a command decoder 50.

The flash cell array 10 includes a plurality of NAND strings, and the structure of the NAND strings will be described in detail with reference to FIG. 2.

The input circuit 20 provides word line voltages of flash memory cells included in multiple NAND strings.

In this embodiment, the semiconductor memory device 1000 can perform the same read and write operations as those performed in a conventional flash memory device.

Accordingly, in order to program data to the requested address, the input circuit 20 generates a word line voltage and the operation of programming data corresponding to the input signal in the flash cell array 10 is the same as the prior art. Detailed explanations are omitted.

In addition, in order to read data at the requested address, the operation of generating a word line voltage in the input circuit 20 and outputting the data provided from the flash cell array 10 to the outside through the output circuit 30 is the same as the prior art. Therefore, detailed description of this will be omitted.

This embodiment is a technology to perform MAC operation of first data and second data, and the first data and second data are vector data each including a plurality of elements.

In the MAC operation, the corresponding elements of the first data and the second data are multiplied and the multiplication result is accumulated.

Hereinafter, the first data may be referred to as input data (Input) and the second data may be referred to as weight data (Weight). In this embodiment, each element of input data is assumed to be 2 bits, and each element of weight data is assumed to be 1 bit.

In this embodiment, first data corresponding to input data is pre-programmed into the flash memory cell array through a write operation prior to performing an operation operation.

In this embodiment, the second data corresponding to the weight data is input during the process of performing the MAC operation operation.

The MAC operation operation is similar to the read operation for flash cells. However, during the MAC operation operation, an input signal corresponding to the second data is provided to the input circuit 20, and the input circuit 20 generates a word line voltage according to the input signal.

As described above, in this embodiment, each element of the second data is 1-bit data. That is, the ith element (Weight _i ) of the second data and the corresponding ith input signal (X _i ) have a value of 0 or 1.

For example, if the value of the i-th element (Weight _i ) in the second data is 1, a normal read voltage pulse is provided as the voltage of the i-th word line. However, if the value of the element is 0, the ith word line voltage is maintained as the ground voltage.

The method of controlling the word line voltage according to weight data in the MAC operation process will be described in detail again below.

The output circuit 30 provides the data stored in the flash cell array 30 as output data (DOUT), which is the same as the conventional technology.

The output circuit 30 in this embodiment differs from the conventional output circuit in that it further outputs the MAC operation result, which will be described in detail below.

The output circuit 30 can set the bit line BL to a ground voltage or power voltage or to a floating state during a read or write process, which is the same as conventional technology.

The source line control circuit 40 is a circuit that controls the source line SL connected to the flash cell array 10.

The command decoder 50 controls data input/output operations by controlling the flash cell array 10, input circuit 20, output circuit 30, and source line control circuit 40 according to commands and addresses provided from the host. do.

As described above, data input/output operations are the same as in the prior art, so description thereof will be omitted.

The operation control circuit 60 controls the MAC operation operation, and to perform this, it uses a flash cell array 10, an input circuit 20, an output circuit 30, a source line control circuit 40, and a command decoder 50. can be controlled.

As described above, the MAC operation operation in this embodiment can be performed using a read operation of a conventional memory device, which will be described in detail below.

Figure 2 is a circuit diagram showing a semiconductor memory device according to an embodiment of the present invention.

The flash cell array 10 includes a plurality of NAND strings 100 arranged in two or three dimensions as in the related art.

The NAND string 100 is connected between the first node (N1) and the second node (N2).

The first node (N1) is connected to the bit line (BL). One bit line BL may be connected to multiple NAND strings 100 through the first node N1.

The second node N2 is connected to the source line SL, and the source line SL may be connected to the ground power source GND through the switch MN4.

The voltage of the first node (N1) is expressed as a bit line voltage (V _BL ), and the current flowing through the first node (N1) is expressed as a bit line current (I _BL ).

The NAND string 100 includes a first switch (MN1) connected between the first node (N1) and the third node (N3).

In this embodiment, the first switch (MN1) is an NMOS transistor whose gate is controlled by the drain select line (DSL), and the drain and source are connected to the first node (N1) and the third node (N3), respectively.

A plurality of flash memory cells (FC ₀ , ..., FC _n-2 , FC _n-1 ) are connected in series between the second node (N2) and the third node (N3).

A word line (WL<i>) is connected to the control gate of the flash memory cell (FC _i , i = 0, 1, ..., n-1).

The output circuit 30 includes a second switch (MP) connected between the first power source (VDD) and the fourth node (N4), and a third switch (MN2) connected between the fourth node (N4) and the first node (N1). ) includes. A third switch (MN3) is included between the fourth node (N4) and the second power source (GND) and can be used to set the bit line (BL) to the ground voltage.

In this embodiment, the second switch (MP) is a PMOS transistor (MP) to which a precharge signal (PC) is applied to the gate, and the third switch (MN2) is an NMOS transistor to which a selection signal (SEL) is applied to the gate. And the fourth switch (MN3) is an NMOS transistor to which a pull-down signal (PD) is applied to the gate.

In a read or write operation for the flash cell array 100, controlling the bit line voltage by controlling the second switch (MP), third switch (MN2), and fourth switch (MN3) is the same as in the prior art.

The output circuit 30 includes a comparator 301 and a latch 302 and provides output data (DOUT) during a typical read operation of a flash memory device.

The comparator 301 compares the output voltage of the fourth node N4 and the threshold voltage (V _TH ) according to the activation signal (EN), and the latch 302 latches the output of the comparator 301 to produce output data (DOUT) ) is created.

In this embodiment, the output circuit 30 includes an operational capacitor 310 connected between the fourth node N4 and the second power source GND.

In this embodiment, at the beginning of the MAC operation operation, the precharge signal (PC) and the selection signal (SEL) are set to low level, the second switch (MP) is turned on, and the third switch (MN2) is turned off. The operation capacitor 310 is charged.

After the MAC calculation operation is completed, the calculation result can be tracked using the charging voltage of the calculation capacitor 310, which will be described in detail again below.

The output circuit 30 further includes an analog-to-digital converter 320 and converts the charging voltage (V _SO ) of the operation capacitor 310 into a digital signal to provide an operation output (MOUT).

The source line control circuit 40 includes a fifth switch (MN4) connected between the second node (N2) and the second power source (GND).

In this embodiment, the fifth switch (MN4) is an NMOS transistor whose gate is applied with a source line selection signal (SSL).

The operation control circuit 60 includes a voltage selection circuit 61, a constant current source 62, a diode-coupled transistor 63, and a selection control circuit 64.

The voltage selection circuit 61 provides the selected voltage as the source line selection signal SSL to the gate of the fifth switch MN4 according to the selection control signal SELC provided from the selection control circuit 64.

The selection control circuit 64 provides 0 or 1 as a selection control signal (SELC) during MAC operation operation, and provides 2 as a selection control signal (SELC) during general memory operation.

The voltage provided as a source line control signal (SSL) during read, erase, and write operations of a flash memory device is expressed as the memory operating voltage (Vm).

The memory operating voltage (Vm) may be provided differently depending on the type of operation, and since it is the same as the conventional technology as shown in Patent Document 3, detailed description will be omitted.

Figure 3 is a graph explaining a read operation of a flash memory device.

FIG. 3(A) corresponds to a case in which a flash memory cell stores 2-bit data, and FIG. 3(B) corresponds to a case in which a flash memory cell stores 3-bit data.

First, a pass voltage (V _PASS ) is applied to the word line connected to the remaining flash memory cells except for the flash memory cell selected in the NAND string.

Next, a read voltage is sequentially provided as a word line voltage to the word line connected to the selected flash memory cell, and changes in the output signal are detected.

For example, in Figure 3(A), pulse-shaped voltages with sizes of V _RD1 , V _RD2 , and V _RD3 are sequentially provided as read voltages.

If the data stored in the flash memory cell is "10", all high level signals are output as the output signal (DOUT) until V _RD1 and V _RD2 are provided as the read voltage, but when V _RD3 is provided as the read voltage, the low level signal is output. The signal is output as an output signal (DOUT). Accordingly, it is determined that the data stored in the flash memory cell is “10”.

Likewise, in FIG. 3(B), pulse-shaped voltages with sizes of V _RD1 , V _RD2 , V _RD3 , V _RD4 , V _RD5 , V _{RD6, and} V _RD7 are sequentially provided as read voltages.

If the data stored in the flash memory cell is “100”, all high level signals are output as the output signal (DOUT) until V _RD1 , V _RD2 , V _RD3 , and V _RD4 are provided as the read voltage. Providing V _RD5 , V _RD6 , and V _RD7 changes the output signal (DOUT) to low level. Accordingly, it is determined that the data stored in the flash memory cell is “100”.

Hereinafter, it is assumed that 2-bit data is stored in the flash memory cell as shown in FIG. 3(A), and V _RD1 is indicated as the first read voltage, V _RD2 is indicated as the second read voltage, and V _RD3 is indicated as the third read voltage. do.

In this embodiment, the MAC operation operation applies a read operation to these flash memory cells. Hereinafter, the MAC operation operation will be described with reference to FIGS. 2 and 4.

Figure 4 is a timing diagram showing MAC operation operation according to an embodiment of the present invention.

As described above, before performing the MAC operation, each of the plurality of flash memory cells included in the NAND string 100 pre-stores first data, that is, a value corresponding to each element of input data.

In FIG. 4, the MAC operation operation includes a precharge operation performed between T0 and T1 and a current discharge operation performed between T1 and T65.

In the precharge operation, the precharge signal (PC) is set to a low level for a certain period of time and the second switch (MP) is turned on to charge the operation capacitor 310.

Additionally, both the selection signal (SEL) and the drain selection signal (DSL) are set to low level, so that the first switch (MN1) and the third switch (MN2) are also turned off.

The fourth switch (MN3) maintains the turned-off state during the MAC operation operation. Accordingly, the pull-down signal (PD), which is fixed at a low level, is not shown.

The capacity of the operation capacitor 310 is expressed as C _SO , and the charging voltage of the operation capacitor 310 is expressed as V _SO .

During the precharge operation, the selection control circuit 64 selects 0 as the selection control signal SELC, and accordingly the fifth switch MN4 is turned off.

In the current discharge operation, the second switch (MP) is turned off, and the first switch (MN1), the third switch (MN2), and the fifth switch (MN4) are turned on.

During the current discharge operation, the selection control circuit 64 selects 1 as the selection control signal SELC, and the fifth switch MN4 operates as a current mirror accordingly.

Accordingly, during the current discharge operation, the bit line current (I _BL ) mirrors the cell current (I _C ) provided by the constant current source 62.

Afterwards, a read operation is sequentially performed on the flash memory cells included in the NAND string.

Between T1 and T2, a read operation is performed on flash cells (FC _n-1 , FC ₆₃ ).

The 63rd element of the input data is “11”, and the flash memory cell (FC ₆₃ ) stores “11”.

In addition, since the 63rd element (Weight ₆₃ ) of the weight data is “1”, the first read voltage (V _RD1 ), the second read voltage (V RD2), and the third read voltage (V _RD1 ) are used as word line voltages for the selected word line. V _RD3 ) are provided sequentially.

That is, for a read operation, the first read voltage (V _RD1 ), the second read voltage (V _RD2 ), and the third read voltage (V _RD3 ) are sequentially provided to the control gate of the flash memory cell (FC ₆₃ ), A pass voltage (V _PASS ) is applied to the control gates of the remaining flash memory cells.

In FIG. 4, the word line connected to the flash memory cell where a read operation is performed is indicated as a selected word line, and the word line connected to the remaining flash memory cells is indicated as an unselected word line.

In this embodiment, the first switch (MN1) and the third switch (MN2) are turned on only when the first to third read voltages are provided, and the bit line current (I _BL ) flows only in this section.

Referring to FIG. 3, when the data of the flash memory cell FC ₆₃ is “11”, all of the first to third read voltages are turned on.

When the flash memory cell is turned on, a certain amount of bit line current (I _BL = I _C ) flows, and accordingly, a certain amount of charge (Q) is discharged from the operation capacitor 310.

Accordingly, the charge of 3Q is discharged during a read operation on the flash memory cell (FC ₆₃ ) between T1 and T2.

Between T2 and T3, a read operation is performed on the flash memory cell (FC ₆₂ ).

The 62nd element of the input data is “10”, and the flash cell (FC ₆₂ ) is storing “10”.

Additionally, since the 62nd element (Weight ₆₂ ) of the weight data is “0”, the ground voltage is provided as the word line voltage for the selected word line.

That is, for a read operation, a ground voltage is applied to the control gate of the flash memory cell (FC ₆₂ ), and a pass voltage (V _PASS ) is applied to the control gate of the remaining flash memory cells.

Accordingly, the flash memory cell FC ₆₂ is maintained in a turned-off state and charge is not discharged from the operation capacitor 310.

Between T64 and T65, a read operation on the flash cell (FC ₀ ) is performed.

Since the 0th element of the input data is "01", the flash memory cell (FC ₀ ) is storing "01".

In addition, since the 0th element (Weight ₀ ) of the weight data is “1”, for the selected word line, the first read voltage (V _RD1 ), the second read voltage (V _{RD2), and the third read voltage (V RD1} ) are used as word line voltages. V _RD3 ) are provided sequentially.

That is, for a read operation, a first read voltage (V _RD1 ), a second read voltage (V _RD2 ), and a third read voltage (V _RD3 ) are sequentially provided to the control gate of the flash memory cell (FC ₀ ), A pass voltage (V _PASS ) is applied to the control gates of the remaining flash memory cells.

Referring to FIG. 3, when the data of the flash memory cell (FC ₀ ) is “01”, it is turned on only for the first read voltage (V _RD1 ).

Accordingly, the charge of Q is discharged during a read operation on the flash memory cell (FC ₀ ) between T64 and T65.

After T65, the first switch (MN1), the second switch (MP), the third switch (MN2), and the fifth switch (MN4) are turned off, and the operation capacitor 310 is in a floating state.

At this time, the charging voltage of the operation capacitor 310 is expressed as Equation 1.

In Equation 1, Input represents input data, Weight represents weight data, and T represents the time during which the read voltage is provided.

In Equation 1, the result of the MAC operation between the input data and the weight data corresponds to the second term in the numerator.

Accordingly, the MAC operation result between input data and weight data can be calculated using the calculation output (MOUT) in the precharge state and the calculation output (MOUT) after the current discharge operation.

Figure 5 shows a semiconductor memory device according to another embodiment of the present invention.

In the embodiment shown in Figure 2, each element of the weight data is given as 0 or 1. In contrast, in the embodiment of FIG. 5, each element of the weight data is given as 1 or -1.

The embodiment of FIG. 5 uses first and second NAND strings 110 and 120 connected to different bit lines, and the first NAND string 110 and the second NAND string 120 store the same input data. do.

For example, assume that n = 4, the weight vector is {1, 1, -1, -1}, and the input data is {d1, d2, d3, d4}.

At this time, the first NAND string 110 and the second NAND string 120 store input data {d1, d2, d3, d4} in advance.

To this end, the host may generate a first write request and a second write request with write data {d1, d2, d3, d4} and provide them to the first NAND string 110 and the second NAND string 120. .

As described above, since the writing operation itself for the first NAND string 110 and the second NAND string 120 is a conventional technology, detailed description will be omitted.

The first NAND string 110 and the second NAND string 120 have the same structure as the NAND string 100 of FIG. 2.

Accordingly, in the first NAND string 110 and the second NAND string 120, the same reference symbols as those in FIG. 2 are used, and subscripts are used for distinction.

From the weight data, first weight data provided to the first NAND string 110 and second weight data provided to the second NAND string are determined.

In this embodiment, the values with negative elements in the weight data are set to 0 as first weight data, the values with positive elements in the weight data are set to 0, and the values with negative elements are set to 1 as the second weight data. Set as weighted data.

Accordingly, the first weight data provided to the first NAND string 110 is {1, 1, 0, 0}, and the second weight data provided to the second NAND string 120 is {0, 0, 1, 1}.

Performing a MAC operation while providing a word line voltage according to the first weight data to the first NAND string 110 where the input data is stored is the same as that described with reference to FIG. 4 .

Additionally, performing a MAC operation operation while providing a word line voltage according to the second weight data to the second NAND string 120 where the input data is stored is the same as that described with reference to FIG. 4 .

The output circuit 300 is an extension of the output circuit 30 of FIG. 2 and further includes a voltage calculation circuit 311.

In the output circuit 300 of FIG. 5, the configuration corresponding to the output circuit 20 of FIG. 2 uses the same reference sign, but different subscripts are used to distinguish the corresponding NAND string.

That is, the output circuit 300 includes a second switch (MP ₁ ), a third switch (MN2 ₁ ), a fourth switch (MN3 ₁ ), and an operation capacitor 310 ₁ corresponding to the first NAND string 110. and includes a second switch (MP ₂ ), a third switch (MN2 ₂ ), a fourth switch (MN3 ₂ ), and an operation capacitor (310 ₂ ) corresponding to the second NAND string 120 .

The capacity of the two operation capacitors 310 ₁ and 310 ₂ is the same as C _SO , and the charging voltage of the operation capacitor 310 ₁ is set to the first output voltage (V _OUTP ) and the charging voltage of the operation capacitor 310 ₂ is set to the second output voltage. When expressed as (V _OUTN ), the voltage operation circuit 311 generates an output voltage (V _OUT ) obtained by subtracting the first output voltage (V _OUTP ) from the second output voltage (V _OUTN ).

The configuration of the source line control circuit 400 and the operation control circuit 60 is substantially the same as that of FIG. 2 .

Except that the source line control circuit 400 includes a fifth switch (MN4 ₁ ) corresponding to the first NAND string 110 and a fifth switch (MN4 ₂ ) corresponding to the second NAND string 120. It is substantially the same as the source line control circuit 40 in FIG. 2.

When the MAC operation operation as shown in FIG. 4 is completed for the first NAND string 110 and the second NAND string 120, the first output voltage (V _OUTP ) is expressed as Equation 2, and the second output voltage ( V _OUTN ) is expressed as Equation 3.

In Equation 2, the relationships W1 _i = Weight _i (if Weight _i = 1) and W1 _i = 0 (if Weight _i = -1) are established.

In Equation 3, the relationships W2 _i = -Weight _i (if Weight _i = -1) and W2 _i = 0 (if Weight _i = 1) are established.

From Equations 2 and 3, the output voltage (V _OUT ) of the voltage subtraction circuit 311 is expressed as Equation 4.

Through Equation 4, it can be seen that when the weight data is 1 or -1, the output voltage (V _OUT ) of the voltage operation circuit 311 corresponds to the result of the MAC operation using input data (Input) and weight data (Weight). there is.

The scope of rights of the present invention is not limited to the above disclosure. The scope of rights of the present invention should be interpreted based on the scope literally stated in the claims and the scope of equivalents thereof.

10: Flash cell array
100: NAND string, 110: first NAND string, 120: second NAND string
20: input circuit
30, 300: output circuit
40, 400: Source line control circuit
50: Command decoder
60: Operational control circuit
61: Voltage selection circuit
62: constant current source
64: selection control circuit

Claims (12)

A cell array including a plurality of memory cells connected between a bit line and a source line;
an operation control circuit that provides a constant current between the bit line and the source line during an operation operation; and
An output circuit including an arithmetic capacitor whose charge amount is changed by the arithmetic operation.
Including,
A semiconductor memory in which the amount of charge that moves between the bit line and the source line during the operation operation varies depending on a value stored in the memory cell corresponding to first data and a word line voltage connected to the memory cell corresponding to second data. Device. The semiconductor memory device of claim 1, wherein the output circuit includes a switch connecting the first power source and the operation capacitor according to a precharge signal, and a switch connecting the bit line and the operation capacitor according to a selection signal. The semiconductor memory device of claim 2, wherein the output circuit further includes an analog-to-digital converter that converts the charging voltage of the operation capacitor into a digital signal. The semiconductor memory device of claim 2, wherein during an operation operation, the operation capacitor is precharged and then the bit line and the operation capacitor are connected to provide a constant current to the bit line. The semiconductor memory device of claim 1, further comprising a switch that controls the voltage of the source line according to a source line control signal, and the operation control circuit mirrors the constant current to the switch during an operation operation. In claim 1,
Each of the plurality of memory cells performs the calculation operation while reading the value of the corresponding element of the first data stored in advance using a word line voltage determined according to the value of the element corresponding to the second data,
After the operation, the operation capacitor provides a charging voltage corresponding to a result of a multiplication and accumulation (MAC) operation of the first data and the second data. The method according to claim 6, wherein the cell array includes a NAND string including a plurality of flash memory cells connected in series and a switch connecting one end to the bit line according to a drain selection signal,
A semiconductor memory device in which a voltage signal is provided to a control gate of each of the plurality of flash memory cells included in the NAND string according to the value of a corresponding element of the second data. The semiconductor memory device of claim 7 , further comprising an input circuit that controls a word line voltage connected to a control gate of the plurality of flash memory cells according to the second data. A flash memory cell array including a first NAND string connected to a first bit line and a second NAND string connected to a second bit line;
A first operation capacitor connected to the first bit line, a second operation capacitor connected to the second bit line, and a voltage calculation circuit that calculates the charging voltage of the first operation capacitor and the charging voltage of the second operation capacitor. an output circuit comprising; and
an operation control circuit that provides constant current to the first bit line and the second bit line during an operation operation;
Including,
The first NAND string and the second NAND string store input data,
During the operation, a word line voltage is provided to the first NAND string according to first weight data corresponding to a positive weight among the weight data, and a word line voltage is provided to the second NAND string according to a negative weight among the weight data. A semiconductor memory device that provides word line voltage according to weight data. The method of claim 9, wherein the output circuit includes a switch connecting the first power source and the first operation capacitor, a switch connecting the first bit line and the first operation capacitor, and the first power source and the second operation capacitor. A semiconductor memory device including a switch connecting the second bit line and the second operation capacitor. The method of claim 9, wherein during an operation operation, after precharging the first operation capacitor, the first bit line and the first operation capacitor are connected to provide a constant current to the first bit line, and the second operation capacitor is precharged. After connecting the second bit line and the second operation capacitor, a semiconductor memory device provides a constant current to the second bit line. The method according to claim 9, further comprising a switch connecting the other end of the first NAND string and the second power source and a switch connecting the other end of the second NAND string and the second power source, wherein the operation control circuit generates the constant current during an operation operation. A semiconductor memory device that provides mirroring to the first bit line and the second bit line.

Images