JP2000090677A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory in which reliability can be enhanced by suppressing the effect of AGL noise significantly thereby ensuring the margin of data retaining characteristics easily. SOLUTION: A shift cell detecting circuit 6 is provided between a circuit 3 for latching a write data and a latch control circuit 4 of an NAND type flash memory. In the shift cell detecting circuit 6, a memory cell transistor where a low threshold voltage is distributed between the word line voltage during verify operation and the word line voltage during normal read operation is detected and a resultant data sequence identical to the write data sequence is stored in the latch circuit 3. Consequently, rewrite is performed only for such a memory cell transistor as a decision is made that reliability can not be ensured because of insufficient writing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device suitable for use as a recording medium for digital recording of images and audio signals.

[0002]

2. Description of the Related Art In recent years, flash memories, which have better electrical characteristics than various recording devices and hard disk devices, have become widespread as recording media in video / audio equipment, portable information equipment, and the like. A flash memory is an electrically rewritable nonvolatile semiconductor memory device including, for example, one transistor per bit, and is roughly classified into a NOR type and a NAND type according to the connection relationship and structure of its memory cells.

[0003] In the NOR type flash memory, each memory cell is connected to a bit line, and although it is disadvantageous in size and cost, random access is possible. Further, the NAND flash memory is connected to a bit line via a select transistor for each predetermined memory cell connected in series called a memory string, so that the occupied area per bit is small and the cost per bit is low. Although it has the advantage of being low, there are limitations and characteristic obstacles regarding writing and reading.

[0004] For example, as one of the obstacles in its characteristics,
As described above, since the NAND flash memory is configured by a memory string including predetermined memory cells connected in series, when writing to a certain memory cell on one memory string, It is structurally affected by memory cells other than those to be written and memory cells of other memory strings. The effect of a memory cell other than a write target on a memory cell to be written will be briefly described below.

FIG. 9 shows a configuration of a memory cell array of a NAND flash memory as an example. Usually NAN
In the D-type flash memory, one memory cell array is composed of a plurality of blocks, and one block is composed of a plurality of pages in word line units. FIG.
In the example shown in (1), one block = 16 pages. In FIG. 9, reference numeral 101 denotes a memory cell array. The memory cell array 101 has memory cells arranged in a matrix, and as shown in FIG. 9, each memory cell has a common word line WL0-W.
It has memory strings A0 to An connected to L15. These memory strings A0 to An share the source line 102. One block is composed of a plurality of groups of memory strings sharing a source line.

One memory string has, for example, a floating gate, and a plurality of MOS transistors, each functioning as, for example, a 1-bit memory cell, are connected in series. Memory string A0
_Are composed of memory cell transistors M _{0-0 to} M _15-0 . The drain of the memory cell transistor _M15-0 is connected to the source of the selection transistor DS0, and the drain of the selection transistor DS0 is connected to the bit line BL0. Further, the source of the memory cell transistor M _0-0 is connected to the drain of the selection transistor SS0, and the source of the selection transistor SS0 is connected to the source line 102. Further, the gates of the memory cell transistors M _{0-0 to} M _15-0 are connected to the word lines WL0 to WL15, respectively. Thus, the memory string A
0 is connected to each line, and the other memory strings A1 to A
The same connection relationship is applied to n.

Therefore, one ends of the memory strings A0 to An are connected to the bit lines BL0 to BLn via the selection transistors DS0 to DSn, and the other ends of the memory strings A0 to An are connected to the selection transistors SS0 to SSn.
Is connected to the source line 102 via the. The gates of the selection transistors DS0 to DSn are connected to a common drain-side selection gate line DSG, and the selection transistors SS
0-SSn are common source side select gate lines SS
Connected to G.

The source line 102 to which the other ends of the memory strings A0 to An are connected via the selection transistors SS0 to SSn is actually connected to the selection transistors SS0 to SSn.
It is composed of a source diffusion layer shared by n and has a certain degree of resistance. The source line 102 is in contact with a metal bypass line (Al wiring pattern) 103 having an extremely small resistance. Source line 1
02 is biased to a predetermined potential, for example, a ground level as needed by the metal bypass line 103.

The memory cell array 1 thus configured
For example, the memory cell transistors M _0-n to 104 shown in FIG. 9 connected to the word lines WL0 to WL14 and connected to the bit line BLn are connected to the bit lines BLn.
It is assumed that all data "0" is written to M14 _-n to be in a write state with a positive threshold value, and is connected to word lines WL0 to WL14 and bit line BL
9 connected to BL (n-1).
5, the memory cell transistors M _{0-0 to} M
It is assumed that all data “1” has been written to _{14- (n−1)} and the data has been erased with a negative threshold value.

In this state, it is assumed that data "0" is written to all the memory cell transistors connected to the word line WL15, that is, the memory cell transistors _{M15-0 to} M15 _-n . How the non-target memory cells affect the target memory cell will be specifically described. As for writing, it is assumed that writing is performed to some extent and a verify operation is performed, and when the cell current is equal to or less than a predetermined value, it is determined that writing is completed, and the determined memory cell transistors are sequentially put in a write-inhibited state. Also, each of the memory cell transistors M _15-0 ~M _15-n, if conditions are the same, specifically, the memory cell transistors M _15-k
(K = ₀ to n), the memory cell transistors M _0-k
When the data patterns of .about.M14 _-k are the same and the source line resistance is negligible, the write speeds are assumed to be substantially the same.

First, when there is no memory cell transistor that has reached the write level in the read operation in the verify operation after the first write, a cell current equal to or greater than the determination current flows through all the memory cell transistors. In this state, a voltage that cannot be ignored is generated in the source line 102 made of the diffusion layer due to the cell current, and the voltage increases as the distance from the metal bypass line 103 increases. That is, in the case shown in FIG.
The voltage of No. 2 becomes higher as it moves rightward in the drawing from the connection point with the memory string A0, and becomes the highest at the connection point with the memory string An.

Further, since the memory cell transistors M _0-n ~M _14-n is represented by 104 in FIG. 9, and all the data "0" is written, the memory cell transistors M _0-n ~M _14- the drain of each transistor of the _n - source voltage VDS is the drain of each transistor of the memory cell transistors M _0-0 ~M erased state _{14- (n-1)} - higher than the source voltage VDS.

Due to these two factors, the source voltage of the memory cell transistor M _{15 -n} indicated by reference numeral 106 in FIG. 9 is changed to the memory cell transistors M _{15-0 to} M _15-(n− It is higher than the source voltage of each transistor in ₁₎ . For this reason, even if the injection amount of electrons at the time of writing is the same, the cell current of the memory cell transistor M _15-n is reduced by the back bias effect, and the cell current of each of the memory cell transistors M _{15-0 to} M _{15- (n-1)} is reduced. As a result, the memory cell transistor M _{15 -n} is determined to be sufficiently written and is set in the write-inhibited state by another memory cell transistor, that is, the memory cell transistor M _15-0.
~ M _{15- (n-1)} . Then, the writing and verifying operations are repeatedly performed on the other memory cell transistors determined to be insufficiently written, and the writing operation ends when all the memory cell transistors are determined to be sufficiently written.

However, focusing on the memory cell transistor M _{15 -n} indicated by reference numeral 106 in FIG.
When it is determined that writing is sufficient, reference numeral 1 in FIG.
07 memory cell transistors M _{15-0 to} M
Regarding _{15- (n-1)} , the cell current still flows due to insufficient writing, and the source current of the diffusion layer 10
In the state where the voltage of No. 2 was raised, it was determined that the cell current of the memory cell transistor M15 _-n was equal to or less than the determination current. However, with respect to the memory cell transistors _{M15-0 to} M15- _(n-1) indicated by the reference numeral 107 in FIG. 9, the writing and the verifying operation are repeatedly performed, and the writing becomes sufficient, and the cell current stops flowing. Therefore, the voltage at the connection point between the memory string An and the source line 102 does not rise, and the threshold voltage Vth of the memory cell transistor M15 _-n is Vth when it is determined that writing is sufficient.
lower than th.

Such a change in Vth due to the resistance of the source line 102 is called AGL (Array Ground Line) noise. The combination of the write data in the above description is the worst combination in which the AGL noise is maximum, but the other combinations are affected by the AGL noise to a certain extent. As a method of reducing the influence of the AGL noise, the size of the nonvolatile semiconductor memory device is increased as a whole to increase the number of metal bypass lines, or structural measures are taken to shorten the distance between the source lines 102 as much as possible. Unless the voltage change level is suppressed to a negligible level, the influence of the AGL noise cannot be avoided.

On the other hand, the threshold voltage V of a memory cell transistor in a conventional binary nonvolatile semiconductor memory device
FIG. 10 shows the distribution of th. In FIG. 10, the vertical axis represents the threshold voltage Vth, and the horizontal axis represents the distribution frequency of the memory cell transistors. In FIG. 10, reference numeral 110 indicates the distribution of the memory cell transistors in which data “0” is written to be in a positive threshold write state, and reference numeral 111 in FIG. This is the distribution of the memory cell transistors in which “1” is written and in the erased state of the negative threshold value.
In FIG. 10, the selected word line voltage at the time of reading in the verify operation is indicated by VVF, and the selected word line voltage at the time of normal reading is indicated by VRD.

As shown in FIG. 10, in the conventional nonvolatile semiconductor memory device, the selected word line voltage VVF at the time of reading in the verify operation and the selected word line voltage VRD at the time of normal reading have a certain width. It is set to have a margin. This is to cope with a memory cell transistor in which the threshold voltage Vth decreases due to defective data retention characteristics or the like.
Care is taken so that reading can be performed correctly even when th decreases.

[0018]

However, the memory cell transistors distributed below the selected word line voltage VVF at the time of reading in the verify operation immediately after writing due to the above-described AGL noise may be caused by poor data retention characteristics or the like. The value that allows the threshold voltage Vth to decrease decreases. That is, assuming that the reference numeral 112 in FIG. 10 indicates the distribution of the memory cell transistors in which the threshold voltage Vth is shifted by the AGL noise, the lower limit value due to the influence of the AGL noise indicated by the reference numeral 113 in FIG. And the difference between the selected word line voltage VRD and the memory cell transistor decreases the reliability of the entire device.

Recently, with the demand for increasing the capacity of a semiconductor memory device, a multi-valued nonvolatile semiconductor memory device that records at least three or more values of data in one memory cell transistor has been proposed. In the case of a multi-level nonvolatile semiconductor memory device, since the margin allocated to each data is further reduced, the conditions become severe and it becomes difficult to guarantee the reliability. In particular, the aforementioned memory cell transistor M _15-n (reference numeral 106 in FIG. 9)
), The write speed of the gate of the memory cell transistor M _15-0 on the same word line is high.
It is determined that the writing is sufficient in a state where the cell current becomes the largest when writing to _{M15- (n-1)} is hardly completed, and the connection point between the source line 102 and the memory string An is the highest. Would. When all the memory cell transistors are determined to be sufficiently written, such memory cell transistors are distributed below the determination level at the time of normal reading, and may be erroneously read.

Accordingly, it is an object of the present invention to provide a nonvolatile semiconductor memory device which can greatly reduce the influence of AGL noise and can easily secure a margin of data retention characteristics to improve reliability. Is to do.

[0021]

In order to achieve the above object, according to the present invention, the amount of charge accumulated in a charge accumulating portion changes according to a voltage applied to a word line and a bit line. The threshold voltage changes, and has a memory cell for storing data of a value corresponding to the threshold voltage. Prescribed data is written to the memory cell in page units, and sufficient writing is performed to the memory cell. During a verify operation for confirming whether or not data has been written, the voltage applied to the word line is set to the first read voltage to read data stored in the memory cell, and the voltage is applied to the word line during normal reading of the memory cell. In a nonvolatile semiconductor memory device for reading data stored in a memory cell by setting the voltage to be read to a second read voltage lower than the first read voltage, the data is stored in the memory cell. Data holding means for holding data to be stored, control means for determining data stored in the memory cell based on the voltage state of the bit line, and controlling the determination result to be stored in the data holding means; Detecting the memory cell having a threshold voltage distributed between the first read voltage and the second read voltage after the completion of the data writing, and detecting the first read voltage and the second read voltage by the detecting means. 2 with respect to a memory cell having a threshold voltage distributed between
Writing means for rewriting data so that the threshold voltage becomes equal to or higher than the first read voltage.

According to the present invention, the shift cell detection circuit is provided between the latch circuit holding the write data and the latch control circuit. In the shift cell detection circuit, memory cell transistors distributed between the word line voltage in the verify operation and the word line voltage in normal reading are detected, and the same data string as the write data is formed as a detection result. The detection result of the circuit is stored in the latch circuit, and rewriting is performed only on the memory cell transistor determined to be insufficiently written, thereby reducing the influence of AGL noise.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing an embodiment of the present invention, FIG. 1, FIG. 2, FIG. 3, and FIG. It will be described with reference to FIG. FIG. 1 shows an example of a configuration of a main part of a quaternary NAND flash memory capable of recording 4-bit data composed of 2 bits for one memory cell transistor.

As shown in FIG. 1, this NAND flash memory comprises a memory cell array 1, a data write control circuit 2, a latch circuit 3, a latch control circuit 4, a verify judgment circuit 5, and the like. This NAN
In the D-type flash memory, one memory cell array is composed of a plurality of blocks, and one block is composed of a plurality of pages in word line units. FIG.
In the example shown in (1), one block = 16 pages. The memory cell array 1 includes memory cells arranged in a matrix, and has a plurality of memory strings A0 to An each connected to a common word line WL0 to WL15 as shown in FIG. FIG.
, The memory string A2 and thereafter are omitted. These memory strings A0 to An share a source line. One block is made up of a plurality of groups of memory strings sharing a source line, and has, for example, m (m> n) memory strings in total.

One memory string has, for example, a floating gate and a plurality of MOS transistors, each of which functions as a 2-bit memory cell, connected in series. Memory string A0 is composed of the memory cell transistors M _0-0 ~M _15-0. The drain of the memory cell transistor _M15-0 is connected to the source of the selection transistor DS0, and the drain of the selection transistor DS0 is connected to the bit line BL0. In addition, the source of the memory cell transistor M _0-0 is connected to the drain of the selection transistor SS0, and the source of the selection transistor SS0 is connected to the source line SL. Further, the gates of the memory cell transistors M _{0-0 to} M _15-0 are connected to the word lines WL0 to WL15, respectively.

The memory string A1 is composed of memory cell transistors M _{0-1 to} M _15-1 . The drain of the memory cell transistor _M15-1 is connected to the source of the selection transistor DS1, and the drain of the selection transistor DS1 is connected to the bit line BL1. Further, the source of the memory cell transistor M _0-1 is the selection transistor S
The drain of S1 is connected, and the source of the selection transistor SS1 is connected to the source line SL. Further, the respective gates of the memory cell transistors M _{0-1 to} M _15-1 are connected to the word lines WL0 to WL15, respectively. Thus, the memory strings A0 and A1 are connected to the respective lines, and the other memory strings have the same connection relationship.

Therefore, one ends of the memory strings A0 to An are connected to the bit lines BL0 to BLn via the selection transistors DS0 to DSn, and the other ends of the memory strings A0 to An are connected to the selection transistors SS0 to SSn.
Are connected to a common source line SL. The gates of the select transistors DS0 to DSn are connected to a common drain side select gate line DSG, and the gates of the select transistors SS0 to SSn are connected to a common source side select gate line SSG.

Note that the common source line SL to which the other ends of the memory strings A0 to An are connected through the selection transistors SS0 to SSn is connected to the selection transistors SS0 to SSn.
n and a source diffusion layer shared by
Is in contact with a metal bypass line (not shown) made of an Al wiring pattern exhibiting an extremely small resistance value. The source line SL is biased to a predetermined potential, for example, a ground level as needed by a metal bypass line.

The write control circuit 2 provided corresponding to the bit lines BL0 and BL1 includes transistors H1 to H4 composed of high-breakdown-voltage n-channel MOS transistors.
, A transistor P1 formed of a p-channel MOS transistor, and transistors N1 to N8 formed of n-channel MOS transistors. Note that the write control circuits corresponding to the bit lines BL2 and thereafter have the same configuration, and a description of these portions will be omitted for simplicity. Also, regarding other circuit portions, only portions corresponding to the bit lines BL0 and BL1 are noted, and only the portions will be described.

In FIG. 1, reference numerals 16, 17, and 18 denote Vcc power supply terminals, for example, (Vcc = 3.3
V). Transistor P is connected to Vcc power supply terminal 16.
1 is connected, and the drain of the transistor P1 is connected to the drain of the transistor N2 whose source is grounded. The reset signal RST1 is supplied to the gate of the transistor N2, and the signal Vref is supplied to the gate of the transistor P1.

The transistor H3 is inserted between the node SA, which is the connection point of the drain of the transistor P1 and the drain of the transistor N2, and the bit line BL0, and the transistor H4 is inserted between the node SA and the bit line BL1. I have. Also, the Vcc power supply terminal 17 and the bit line B
The transistor H1 is inserted between the bit line L0 and the transistor H1, and the transistor H2 is inserted between the Vcc power supply terminal 18 and the bit line BL1.

The signal AnB is supplied to the gate of the transistor H3, and the signal AnN is supplied to the gate of the transistor H4. Further, the signal IN is applied to the gate of the transistor H1.
HB is supplied, and the signal IN is supplied to the gate of the transistor H2.
HN is supplied.

The drain of transistor N1 is connected to node SA, and transistors N3 and N4 connected in series between the source of transistor N1 and ground are inserted.
The source of the transistor N1 and the bit line voltage VB1
N5, N5 connected in series between the supply lines
6 are further inserted, and transistors N7 and N8 connected in series between the source of the transistor N1 and the supply line of the bit line voltage VB2 are inserted. Transistor N
The signal PGM is supplied to one gate. Note that the magnitude relationship between the bit line voltages VB1 and VB2 is (VB2>VB1>
0) and a predetermined voltage value.

The latch circuit 3 includes inverter circuits 11 to 1
4, the output terminal of the inverter circuit 11 is connected to the input terminal of the inverter circuit 12, and the common connection point is the Q2 terminal. The input terminal of the inverter circuit 11 is connected to the output terminal of the inverter circuit 12, and the common connection point is the / Q2 (/ indicates inversion) terminal. On the other hand, the output terminal of the inverter circuit 13 and the input terminal of the inverter circuit 14 are connected,
This common connection point is the Q1 terminal. The input terminal of the inverter circuit 13 is connected to the output terminal of the inverter circuit 14, and the common connection point is the / Q1 (/ indicates inversion) terminal.

The gate of the transistor N4 is connected to the gate of the transistor N6, the common connection point is connected to the / Q2 terminal of the latch circuit 3, and the gate of the transistor N3 is connected to the gate of the transistor N7. The connection point and the / Q1 terminal of the latch circuit 3 are connected. Further, the gate of the transistor N5 is connected to the Q1 terminal of the latch circuit 3, and the gate of the transistor N8 is connected to the Q2 terminal of the latch circuit 3. Each of the Q1, / Q1, Q2, and / Q2 terminals of the latch circuit 3 is connected to a data bus as needed.

The latch control circuit 4 is composed of transistors N9 to N19 formed of n-channel MOS transistors. Transistors N9, N13, N14 connected in series between the / Q2 terminal of the latch circuit 3 and the ground are inserted, and a transistor N15 is connected in parallel with the transistor N13.
Is connected. Further, a transistor N11 is inserted between the Q2 terminal of the latch circuit 3 and the ground. On the other hand, transistors N10, N18, N19 connected in series between the / Q1 terminal of the latch circuit 3 and the ground are inserted, and the transistor N1 connected in series between the connection point between the source of the transistor N10 and the drain of the transistor N18 and the ground.
6, N17 are inserted.

The gate of the transistor N9 and the gate of the transistor N10 are connected, and this common connection point is connected to a node SA which is a connection point between the drain of the transistor P1 and the drain of the transistor N2. Also,
The / Q2 terminal of the latch circuit 3 is connected to the gate of the transistor N16, and the Q2 terminal of the latch circuit 3 is connected to the gate of the transistor N18. Further, the gate of the transistor N11 and the gate of the transistor N12 are connected.

A reset signal RST is applied to a common connection point between the gate of the transistor N11 and the gate of the transistor N12.
2 are supplied. The signal φ is applied to the gate of the transistor N19.
LAT1 is supplied, the signal φLAT2 is supplied to the gate of the transistor N17, the signal φLAT3 is supplied to the gate of the transistor N14, and the signal φLAT4 is supplied to the gate of the transistor N13.

The verify determination circuit 5 includes, for example, an inverter circuit 15, transistors N21 and N22 formed of n-channel MOS transistors, and a determination circuit 22. The input terminal of the inverter circuit 15 is grounded, and the output terminal of the inverter circuit 15 is connected to the determination circuit 22. A transistor N21 and a transistor N22 are inserted in parallel between the output terminal of the inverter circuit 15 and the ground. Further, the gate of the transistor N21 is connected to the / Q2 terminal of the latch circuit 3, and the gate of the transistor N22 is connected to the / Q1 terminal of the latch circuit 3. The determination circuit 22 determines whether or not the writing has been completed for all the memory cell transistors during the writing operation based on the potential of the output line of the inverter circuit 15.

Specifically, when writing is completed, the Q1 and Q2 terminals of the latch circuit 3 go to the power supply voltage Vcc level, and the / Q1 and / Q2 terminals of the latch circuit 3 go to the low level. As a result, the transistors N21, N21
22 is not turned on, and the output of the inverter circuit 15 is held at the high level. Thus, it is determined that the writing has been completed.

On the other hand, if there is a memory cell transistor that is not sufficiently written, one or both of the Q1 terminal and the Q2 terminal of the latch circuit 3 becomes low level, and the / Q1 terminal and / Q2 terminal of the latch circuit 3 become low. , Or both become the power supply voltage Vcc level. As a result, one or both of the transistors N21 and N22 are turned on, and the output of the inverter circuit 15 is held at a low level. Thus, it is determined that there is a memory cell transistor with insufficient writing. The judgment circuit 22
Is output via a terminal 19 and supplied to another control circuit.

In the NAND flash memory configured as described above, one memory cell transistor records two-bit quaternary data. FIG.
The threshold voltage V of data consisting of two bits and taking four values
The relationship between the distribution of th and the data content is shown. As shown in FIG. 2, the threshold voltage Vth of the memory cell transistor takes four states. In FIG. 2, the vertical axis indicates the threshold voltage Vth of the memory cell transistor. The horizontal axis indicates the distribution frequency of the memory cell transistors.

In FIG. 2, reference numeral 31 denotes a distribution of the memory cell transistors in which data "00" is written and brought into a third positive threshold write state.
In FIG. 2, reference numeral 32 indicates a distribution of memory cell transistors in which data “01” is written and the writing state of the second positive threshold is set, and reference numeral 33 in FIG. This is a distribution of the memory cell transistors in which the data “10” is written and the first positive threshold is written. Also, in FIG.
The distribution indicated by 4 is the distribution of the memory cell transistors in which the data “11” is written and the erased state of the negative threshold voltage is set. In FIG. 2, the selected word line voltage for each state at the time of reading in the verify operation is V
VF1, VVF2, and VVF3 are shown, and the selected word line voltages for each state during normal reading are shown as VRD1, VRD2, and VRD3. The magnitude relation is (VVF3>VRD3>VVF2> VRD
2>VVF1> VRD1).

The write, read and verify operations in the above-described NAND flash memory will be described below. First, the write operation will be specifically described.

At the time of standby, the signal PGM is set to the low level (ground level), the transistor N1 is turned off, and the bit lines BL0, BL1 are disconnected from the write control circuit 2. Then, while the signal RST1 is set to the high level (Vcc level), the signals AnB, An
N is set to (Vcc-Vth). This turns on transistors H3, H4 and transistor N2, and sets bit lines BL0, BL1 to the ground level.

When writing is started in this state, the writing data is transferred to the latch circuit 3 via the data bus.
, And the write data is taken into the latch circuit 3 and held. Thereafter, the signal RST1 is switched to the low level, and the bit lines BL0 and BL1 are disconnected from the ground line. Then, the signal Vref is set to low level, the transistor P1 is turned on, and all the bit lines are charged to Vcc.

At this time, signal PGM and signals φLAT1 to φLAT for controlling the read / verify operation are provided.
4 is at a low level so as not to affect the latch data, and the transistors N1, N13, N14, N17, N1
9 is off. Further, the drain-side selection gate line DSG of the memory cell array 1 is set to a high level, and the source-side selection gate line SSG is set to a low level.

Thereafter, the memory strings to be written are selected by the signals AnB and AnN. For example, when the memory string A0 is selected as a write target, the signal AnN is set to low level, the transistor H4 is turned off, and the unselected bit line BL
1 is maintained in a state charged to Vcc. When the memory string A1 is selected as a writing target, the signal AnB is set to low level, the transistor H3 is turned off, and the unselected bit line BL0 is maintained in a state charged to Vcc. . Thus, the signal A
Either one is selected by nB and AnN.

Then, the signal Vref is switched to the Vcc level, the transistor P1 is turned off, the signal PGM is set to the high level, and the transistor N1 is turned on. As a result, the selected bit line BL0 or BL
1 is connected to the write control circuit 2, and the selected bit line B
L0 or BL1 is set to a voltage according to the write data.

For example, when the signal AnB is set to P5V (a voltage of about 5 to 6V) and the signal AnN is set to a low level, the memory string A0 is selected as a write target, and the write data is "00". In this case, both the Q2 terminal and the Q1 terminal of the latch circuit 3 are set to the low level, and the / Q2 terminal and the / Q1 terminal are set to the high level. Therefore, the transistors N3 and N4 are turned on, and the bit line BL0 is discharged to the ground level.

When the write data is "01", the terminals Q2 and Q1 of the latch circuit 3 are (Q2, Q1)
= (0, 1), (0: low level, 1: high level), the / Q2 terminal goes high, and / Q2
One terminal goes low. Therefore, transistor N
5, N6 is turned on, and the bit line BL0 is set to the bit line voltage VB.
1 (for example, 1.2 V).

When the write data is "10", the terminals Q2 and Q1 of the latch circuit 3 are (Q2, Q1)
= (1, 0), the / Q2 terminal goes low, and the / Q1 terminal goes high. Therefore, the transistors N7 and N8 are turned on, and the bit line BL0 is set to the bit line voltage VB2 (for example, 1.4 V).

When the write data is "11", the terminals Q2 and Q1 of the latch circuit 3 are (Q2, Q1)
= (1, 1), and both the / Q2 terminal and the / Q1 terminal are at low level. Therefore, the transistors N4,
N6 and N7 are not turned on and the bit line bit line B
L0 is not connected to any bit line voltage supply line, and bit line BL0 is held at the Vcc level which is the precharge voltage.

After the bit line BL0 connected to the memory string A0 selected as described above is set to a voltage corresponding to the write data, the word lines WL0 to WL
The selected word line connected to the memory cell transistor to be written in 15 is set to the write voltage VPGM, and the unselected word line connected to the memory cell transistor not to be written is set to the write pass voltage. Vpass (<VPGM) is set, and data is written to a predetermined memory cell transistor.

At this time, when the write data is other than "11", Fowler-Nordheim tunneling (Fowler-Null tunneling) occurs due to the electric field between the word line voltage VPGM and the channel voltage.
-Nordheim Tunneling (hereinafter referred to as FN tunneling) phenomenon occurs, and writing is performed. In addition, in the case of the write data “11”, the channel of the memory string A1 on the non-selected side is separated from the bit lines BL0 and BL1 by the selection transistors DS0 and DS1, and
The voltage is boosted to the non-write potential by the coupling capacitance with the word line, and no write is performed.

Next, the normal read operation will be specifically described. FIG. 3 shows the state of signals at various parts in the NAND flash memory described above. It is assumed that the signal AnB is set to (Vcc-Vth) and the signal AnN is set to the low level, so that the memory string A0 is selected as a read target.

At the time of standby, the signal PGM is set to a low level (ground level), the transistor N1 is turned off, and the bit line BL0 is disconnected from the write control circuit 2. Further, the signal AnN is set to the low level, the transistor H4 is turned off, and the bit line BL1 is disconnected from the latch control circuit 4. Further, the signal IN
HB and INHN are both set to low level, and the transistors H1 and H2 are turned off. When the signal Vref is Vcc
Level, the signal RST1 is set to the high level, the transistor N2 is turned on, and the bit line B
L0 is set to the ground level.

When the normal read operation is started, the reset signal RST2 is set to a high level for a certain period before the read operation, and the data held in the latch circuit 3 is reset to a low level. The read operation is performed after the reset of the latch circuit 3 is completed, that is, after both the signal RST1 and the signal RST2 are switched to the low level.
The selected word line voltage VWL is changed, for example, from VRD3 → VRD2 → VRD1.
(Refer to FIG. 2 and FIG. 3, the uppermost stage).

As a pre-process for determining the actual write threshold voltage Vth at each word line voltage, the signal Vre
f is set to the low level, the transistor P1 is turned on, and the bit line BL0 is charged with the power supply voltage Vcc. After a certain period of time, the voltage of the bit line BL0 increases, and the transistor H3 is automatically turned off when the potential difference between the gate and the source of the transistor H3 becomes equal to or lower than the threshold voltage Vth '. Therefore, the bit line BL0
Is charged to (Vcc-Vth-Vth '), and the node SA goes to the Vcc level.

In the above-described state, the selected word line voltage is set to a predetermined value, and the write threshold voltage Vth is determined by reflecting the presence or absence of the cell current on the voltage of the bit line BL0 and the node SA. That is, when a voltage equal to or higher than the threshold voltage Vth of a predetermined memory cell transistor is supplied to its gate and a cell current flows, the voltage of the bit line BL0 drops and the transistor H3 turns on. Therefore, the voltage of the node SA substantially drops to the voltage VBL0 of the bit line BL0. When a voltage lower than the threshold voltage Vth of a predetermined memory cell transistor is supplied to its gate, no cell current flows and the voltage of the bit line BL0 does not drop. The voltage is V
Held at cc level. The write threshold voltage Vth is determined based on this relationship.

When the charging of the bit line BL0 is completed, the signal Vref is set to a predetermined level (for example, 2 V) at which the transistor P1 can supply a current sufficient to compensate for the leak current of the bit line BL0. In addition, the drain side select gate line DSG and the source side select gate line S
SG is set to the same predetermined high-level voltage as the non-selected word line voltage.

First, the write threshold voltage Vth is determined while the selected word line voltage VWL is set to VRD3. When the threshold voltage Vth of the memory cell transistor has the distribution 31, (Vth> VRD3), no cell current flows, and the voltage of the node SA is maintained at the Vcc level.

When pulse-like signals φLAT3 and φLAT4 are set to a high level after a lapse of a predetermined time, transistors N13 and N14 and transistor N13
9 are turned on, the / Q2 terminal of the latch circuit 3 is set to the low level, and the Q2 terminal is inverted from the low level to the high level. At this time, the gate of the transistor N18 connected to the Q2 terminal becomes high level. When the pulse-like signal φLAT1 is set to the high level, the transistors N19, N18 and the transistor N10 are turned on, the / Q1 terminal of the latch circuit 3 is set to the low level, and the Q1 terminal is changed from the low level to the high level. Invert.

On the other hand, when the threshold voltage Vth of the memory cell transistor is other than the distribution 31, (VRD3> Vth)
, A cell current larger than the leak compensation current flows, the voltage of the node SA drops, the transistor H3 turns on, and the capacitance CBL of the bit line BL0 and the capacitance C of the node SA are increased.
Redistribution of charge occurs between SA (<< CBL) and the voltage of the node SA becomes a low level (for example, 1 V) substantially equal to the bit line voltage VBL0. Therefore, even if the transistors N13 to N19 connected to the sources of the transistors N9 and N10 are turned on by the signals φLAT1 to φLAT4, the gates of the transistors N9 and N10 are at a low level (for example, 1 V). Since the resistance between the drain and the source of each of the transistors N9 and N10 is in a high resistance state, a current necessary for inverting the Q2 terminal and the Q1 terminal of the latch circuit 3 cannot flow, and as a result, the low level of the reset state is maintained. The level state is maintained.

When the determination of the write threshold voltage Vth in a state where the selected word line voltage VWL is set to VRD3 is completed, the signal Vref is set to the low level again, the transistor P1 is turned on, and the bit line BL0 is On the other hand, charging is performed at the power supply voltage Vcc. When the charging of the bit line BL0 is completed, the signal Vref becomes a voltage of a predetermined level (for example, 2
V).

Next, the write threshold voltage Vth is determined while the selected word line voltage VWL is set to VRD2. When the threshold voltages Vth of the memory cell transistors are distribution 31 and distribution 32, (Vth> VRD2)
Therefore, no cell current flows, and the voltage of the node SA becomes
It is kept at Vcc level.

When pulse-like signals .phi.LAT3 and .phi.LAT4 are set to a high level after a lapse of a predetermined time, if threshold voltage Vth of memory cell transistor is distribution 32, transistors N13 and N14 and transistor N9 Are turned on, the / Q2 terminal of the latch circuit 3 is set to the low level, and the Q2 terminal is inverted from the low level to the high level. When the threshold voltage Vth of the memory cell transistor has the distribution 31, the / Q of the latch circuit 3 is determined in the determination of the write threshold voltage Vth in a state where the selected word line voltage VWL is already set to VRD3.
Since the two terminals are set to the low level and the Q2 terminal is inverted from the low level to the high level, there is no change.

On the other hand, when the threshold voltages Vth of the memory cell transistors are distributions 33 and 34, (VRD
2> Vth), a cell current larger than the leakage compensation current flows, the voltage of the node SA drops, the transistor H3 turns on, and the voltage of the node SA becomes the bit line voltage VBL.
It becomes a low level (for example, 1 V) having substantially the same potential as 0.
For this reason, a current necessary for inverting the Q2 terminal of the latch circuit 3 cannot flow through the transistor N9, and as a result, a low level state of reset is maintained.

When the determination of the write threshold voltage Vth in a state where the selected word line voltage VWL is set to VRD2 is completed, the signal Vref is set to the low level again, the transistor P1 is turned on, and the bit line BL0 is turned on. On the other hand, charging is performed at the power supply voltage Vcc. When the charging of the bit line BL0 is completed, the signal Vref becomes a voltage of a predetermined level (for example, 2
V).

Finally, the write threshold voltage Vth is determined with the selected word line voltage VWL set to VRD1. Threshold voltage Vth of memory cell transistor
Are distributions 31 to 33, since (Vth> VRD1), no cell current flows, and the voltage of the node SA becomes V
Held at cc level.

When the pulse-like signal φLAT2 is set to a high level after a lapse of a predetermined time, when the threshold voltage Vth of the memory cell transistor has a distribution 33,
Transistors N16 and N17 and transistor N10
Are turned on, the / Q1 terminal of the latch circuit 3 is set to the low level, and the Q1 terminal is inverted from the low level to the high level. When the threshold voltages Vth of the memory cell transistors are distributions 31 and 32, the latch circuit is used in the determination of the write threshold voltage Vth which has already been performed with the selected word line voltage VWL set to VRD3 and VRD2. The Q1 terminal does not change because the / Q2 terminal of No. 3 is set to low level and the transistor N16 is turned off.

On the other hand, when the threshold voltage Vth of the memory cell transistor is distribution 34, since (VRD1> Vth), a cell current larger than the leakage compensation current flows, and the voltage of the node SA drops and the transistor H3 turns on,
The voltage of the node SA becomes a low level (for example, 1 V) having substantially the same potential as the bit line voltage VBL0. For this reason, a current necessary for inverting the Q1 terminal of the latch circuit 3 cannot flow through the transistor N10, and as a result, the low level state of the reset state is maintained.

The read operation is performed in this manner. When the read operation is completed, the Q2 terminal of the latch circuit 3 and the Q1 terminal
An output corresponding to the write threshold voltage Vth of the memory cell transistor is held at each of the terminal, the / Q2 terminal, and the / Q1 terminal. That is, when the threshold voltage Vth has the distribution 31, (Q2, Q1, / Q2, / Q1) = (1,
1,0,0), and when the threshold voltage Vth is distribution 32, (Q2, Q1, / Q2, / Q1) = (1, 0,
0, 1), and when the threshold voltage Vth is distribution 33, (Q2, Q1, / Q2, / Q1) = (0, 1, 1,
0), and when the threshold voltage Vth is distribution 34,
(Q2, Q1, / Q2, / Q1) = (0, 0, 1, 1)
Becomes

Next, the verify operation will be specifically described. FIG. 4 shows the states of signals at various parts in the NAND flash memory described above. It is assumed that the signal AnB is set to (Vcc-Vth) and the signal AnN is set to the low level, so that the memory string A0 is selected as a verification target.

After the end of the write operation, the signal PGM is set to low level (ground level) and the transistor N1
Is turned off, and the bit line BL0 is disconnected from the write control circuit 2. Also, the signal AnN is set to low level, the transistor H4 is turned off, and the bit line BL1
And the latch control circuit 4 are separated. Further, the signals INHB and INHN are both set to low level, and the transistors H1 and H2 are turned off. Also, the signal Vref
Are set to the Vcc level, the signal RST1 is set to the high level, the transistor N2 is turned on, and the bit line BL0 is set to the ground level.

In the verify operation, a write threshold voltage Vth corresponding to data "00", "01", and "10" is determined each time one write is completed. The determination of the write threshold voltage Vth is performed stepwise in the order of, for example, VVF3 → VVF2 → VVF1 (see FIG. 2 and FIG. 4, the uppermost stage) after the signal RST1 is switched to the low level. This is done while lowering the voltage.

First, as a pre-process for determining the actual write threshold voltage Vth at each word line voltage, the signal Vref is set to low level, the transistor P1 is turned on, and the power supply voltage Vcc is applied to the bit line BL0. Is charged. After a certain period of time, the voltage of the bit line BL0 increases, and the transistor H3 is automatically turned off when the potential difference between the gate and the source of the transistor H3 becomes equal to or lower than the threshold voltage Vth '. Therefore, the bit line BL0 is
(Vcc−Vth−Vth ′), and the node SA becomes Vcc
Level.

In the above state, the selected word line voltage is set to a predetermined value, and the determination of the write threshold voltage Vth is performed by reflecting the presence or absence of the cell current on the voltages of the bit line BL0 and the node SA. That is, when a voltage equal to or higher than the threshold voltage Vth of a predetermined memory cell transistor is supplied to its gate and a cell current flows, the voltage of the bit line BL0 drops and the transistor H3 turns on. Therefore, the voltage of the node SA substantially drops to the voltage VBL0 of the bit line BL0. When a voltage lower than the threshold voltage Vth of a predetermined memory cell transistor is supplied to its gate, no cell current flows and the voltage of the bit line BL0 does not drop. The voltage is V
Held at cc level. The write threshold voltage Vth is determined based on this relationship.

When the charging of the bit line BL0 is completed, the signal Vref is set to a predetermined level (for example, 2 V) at which the transistor P1 can supply a current sufficient to compensate for the leakage current of the bit line BL0. In addition, the drain side select gate line DSG and the source side select gate line S
SG is set to the same predetermined high-level voltage as the non-selected word line voltage.

First, the selected word line voltage VWL is set to VVF3, and the write threshold voltage Vth corresponding to the write data "00" is determined. When the threshold voltage Vth of the memory cell transistor has the distribution 31, (Vth
> VVF3), no cell current flows and the node SA
Is held at the Vcc level.

When pulse-like signals φLAT3 and φLAT4 are set to a high level after a lapse of a predetermined time, transistors N13 and N14 and transistor N13
9 are turned on, the / Q2 terminal of the latch circuit 3 is set to the low level, and the Q2 terminal is inverted from the low level to the high level. At this time, the gate of the transistor N18 connected to the Q2 terminal becomes high level. When the pulse-like signal φLAT1 is set to the high level, the transistors N19, N18 and the transistor N10 are turned on, the / Q1 terminal of the latch circuit 3 is set to the low level, and the Q1 terminal is changed from the low level to the high level. Invert.

On the other hand, when the threshold voltage Vth of the memory cell transistor is other than the distribution 31, (VVF3> Vth)
, A cell current larger than the leak compensation current flows, the voltage of the node SA drops, the transistor H3 turns on, and the capacitance CBL of the bit line BL0 and the capacitance C of the node SA are increased.
Redistribution of charge occurs between SA (<< CBL) and the voltage of the node SA becomes a low level (for example, 1 V) substantially equal to the bit line voltage VBL0. Therefore, even if the transistors N13 to N19 connected to the sources of the transistors N9 and N10 are turned on by the signals φLAT1 to φLAT4, the gates of the transistors N9 and N10 are at a low level (for example, 1 V). Since the resistance between the drain and source of each of the transistors N9 and N10 is in a high resistance state, a current required to invert the Q2 terminal and the Q1 terminal of the latch circuit 3 cannot flow, and as a result, the set state is maintained. You.

When the determination of the write threshold voltage Vth in a state where the selected word line voltage VWL is set to VVF3 is completed, the signal Vref is set to the low level again, the transistor P1 is turned on, and the bit line BL0 is turned on. On the other hand, charging is performed at the power supply voltage Vcc. When the charging of the bit line BL0 is completed, the signal Vref becomes a voltage of a predetermined level (for example, 2
V).

Next, the selected word line voltage VWL is set to VVF2, and the write threshold voltage Vth corresponding to the write data "01" is determined. When the threshold voltages Vth of the memory cell transistors are distributions 31 and 32, (Vth> VVF2), no cell current flows, and the voltage of the node SA is maintained at the Vcc level.

When the pulse-like signal φLAT3 is set to a high level after a lapse of a predetermined time, when the threshold voltage Vth of the memory cell transistor is distribution 32 and the write data is "01", the transistor N15 , N1
4 and the transistor N9 are both turned on, and the latch circuit 3
/ Q2 terminal is set to low level, and the Q2 terminal is inverted from low level to high level. When the threshold voltage Vth of the memory cell transistor is distribution 32 and the write data is “00”, the latch data does not change because the transistor N15 is off.

On the other hand, when the threshold voltages Vth of the memory cell transistors are distributions 33 and 34, (VVF
2> Vth), a cell current larger than the leakage compensation current flows, the voltage of the node SA drops, the transistor H3 turns on, and the voltage of the node SA becomes the bit line voltage VBL.
It becomes a low level (for example, 1 V) having substantially the same potential as 0.
Therefore, a current required to invert the Q2 terminal of the latch circuit 3 cannot flow through the transistor N9, and as a result, the set state is maintained.

When the determination of the write threshold voltage Vth in the state where the selected word line voltage VWL is set to VVF2 is completed, the signal Vref is set to the low level again, the transistor P1 is turned on, and the bit line BL0 is On the other hand, charging is performed at the power supply voltage Vcc. When the charging of the bit line BL0 is completed, the signal Vref becomes a voltage of a predetermined level (for example, 2
V).

Finally, the selected word line voltage VWL is set to VVF1, and the write threshold voltage Vth corresponding to the write data "10" is determined. When the threshold voltages Vth of the memory cell transistors are in the distributions 31 to 33, since (Vth> VVF1), no cell current flows, and the voltage of the node SA is kept at the Vcc level.

When the pulse-like signal φLAT1 is set to a high level after a lapse of a predetermined time, when the threshold voltage Vth of the memory cell transistor is distribution 33 and the write data is "10", the transistor N18 , N1
9 and the transistor N10 are both turned on, the / Q1 terminal of the latch circuit 3 is set to the low level, and the Q1 terminal is inverted from the low level to the high level. When the threshold voltage Vth of the memory cell transistor is distribution 33 and the write data is “00” or “01”, the latch circuit 3
Q2 terminal is set to low level and the transistor N1
Since 8 is off, the latch data does not change.

On the other hand, when the threshold voltage Vth of the memory cell transistor has the distribution 34, since (VVF1> Vth), a cell current larger than the leakage compensation current flows, and the voltage of the node SA drops to reduce the transistor voltage. H3 turns on,
The voltage of the node SA becomes a low level (for example, 1 V) having substantially the same potential as the bit line voltage VBL0. Therefore, a current required to invert the Q1 terminal of the latch circuit 3 cannot flow through the transistor N10, and as a result, the set state is maintained.

The verify operation is performed as described above.
Upon completion of the verify operation, the Q2 terminal of the latch circuit 3
An output corresponding to the result of checking the write threshold voltage Vth of the memory cell transistor is held at each of the Q1, / Q2, and / Q1 terminals. That is, if it is confirmed that the writing is sufficient, the Q2 terminal of the latch circuit 3
Each of the Q1, / Q2, and / Q1 terminals is (Q2, Q1, / Q2, / Q1) =
(1,1,0,0).

Therefore, by monitoring the output of the determination circuit 22 of the verify determination circuit 5, it is determined whether or not the writing has been sufficiently completed for all the memory cell transistors, and it is determined that the writing is not sufficient. In this case, the write operation and the verify operation are repeated again. Then, a series of operations ends when it is determined that all the memory cell transistors are sufficiently written.

As described above, in the conventional NAND flash memory, write, read and verify operations are performed. The selected word line voltages (VVF3, VVF2, VVF1) at the time of reading and the selected word line voltages (VRD3, VRD2, VRD1) at the time of normal reading in the verify operation, which are important in the read and verify operations, each have a certain width. Is set to have a margin. This is to cope with a memory cell transistor in which the threshold voltage Vth is reduced due to a defect in data retention characteristics or the like. Even when the threshold voltage Vth is reduced, it is considered that data can be read correctly. .

However, actually, there is a memory cell transistor whose threshold voltage Vth shifts due to the above-mentioned AGL noise. In FIG. 2, reference numeral 36 denotes a distribution of memory cell transistors shifted from the distribution 31 due to the influence of AGL noise, and reference numeral 37 denotes a distribution 32 due to the influence of AGL noise.
Is the distribution of memory cell transistors shifted from
In FIG. 2, reference numeral 38 denotes the distribution of the memory cell transistors shifted from the distribution 33 due to the AGL noise. As shown in FIG. 2, the difference between the lower limit of the distribution shifted due to the influence of the AGL noise and the selected word line voltage (VRD3, VRD2, VRD1) at the time of normal reading becomes small, and these memory cell transistors are used in the device. Decreases overall reliability. In view of such a problem, the present invention has been made, and a detecting means for detecting a memory cell transistor distributed between a selected word line voltage VVFn at the time of reading in a verify operation and a selected word line voltage VRDn at the time of normal reading is provided. The reliability is improved by rewriting the memory cell transistor which is determined to have low reliability based on the output of the detection means.

Hereinafter, the first embodiment of the present invention applied to a quaternary NAND flash memory capable of recording quaternary data consisting of two bits for one memory cell transistor. An embodiment will be described with reference to FIGS. FIG. 5 shows the configuration of the main part of the NAND flash memory according to the first embodiment. FIG. 6 shows the NA according to the first embodiment.
The state of the signal of each part in the ND type flash memory is shown. Note that the same reference numerals are given to portions corresponding to the above-described conventional four-level NAND flash memory,
A detailed description of that portion will be omitted for simplicity.

The quaternary NAND flash memory according to the first embodiment of the present invention has a memory cell array 1, a data write control circuit 2, a latch circuit 3, a latch control circuit 4, a verify judgment circuit as shown in FIG. 5 and a shift cell detection circuit 6 and the like. Therefore, regarding circuits other than the shift cell detection circuit 6, FIG.
Is the same as the conventional four-level NAND flash memory shown in FIG.

The shift cell detection circuit 6 includes transistors N30 to N30 each formed of, for example, an n-channel MOS transistor.
The shift cell detection circuit 6 includes a latch circuit 3 including inverter circuits 11, 12, 13, and 14 and transistors N9 to N including n-channel MOS.
19 is connected to the latch control circuit 4. Specifically, a transistor N30 is inserted between the / Q2 terminal of the latch circuit 3 and the drain of the transistor N9, and a transistor N32 is inserted between the Q2 terminal of the latch circuit 3 and the drain of the transistor N9.
Further, the / Q1 terminal of the latch circuit 3 and the transistor N10
The transistor N31 is inserted between the drain of the latch circuit 3 and the transistor N33 between the Q1 terminal of the latch circuit 3 and the drain of the transistor N10.

The gate of the transistor N30 and the gate of the transistor N31 are commonly connected, and the control signal RDVF is supplied to this common connection point. The transistor N
The gate of the transistor 32 and the gate of the transistor N33 are commonly connected, and a control signal CPYBCK is supplied to this common connection point. The shift cell detection circuit 6 outputs the two control signals R
The selected word line voltages (VVF3, VVF2, VVF) in the verify operation are controlled by DVF and CPYBCK.
1: see FIG. 2) and the memory cell transistors distributed between the selected word line voltages (VRD3, VRD2, VVRD1: see FIG. 2) at the time of normal reading, and the detection result is stored in the latch circuit 3. You. If the control signal RDVF is set to a high level and the control signal CPYBCK is set to a low level, the connection relationship is the same as that of the above-described NAND flash memory, and the above-described write operation and verify operation can be performed.

The operation of the shift cell detection circuit 6 in the above-described embodiment will be described below. The shift cell detection operation is performed in a state where the control signal RDVF is set to the high level and the control signal CPYBCK is set to the low level, for example, after the writing in page units is completed, that is, the normal write operation and the verify operation are performed. After the operation is performed and all the memory cells to be written are determined to be sufficiently written, the operation is continuously performed, and all the terminals Q2 and Q1 of the latch circuit 3 are (Q2, Q1).
= (1, 1). It is also assumed that the signal AnB is set to (Vcc-Vth) and the signal AnN is set to the low level, so that the memory string A0 is selected as a shift cell detection target.

After the end of the write operation, the signal PGM is set to the low level (ground level) and the transistor N1
Is turned off, and the bit line BL0 is disconnected from the write control circuit 2. Also, the signal AnN is set to low level, the transistor H4 is turned off, and the bit line BL1
And the latch control circuit 4 are separated. Further, the signals INHB and INHN are both set to low level, and the transistors H1 and H2 are turned off. Also, the signal Vref
Are set to the Vcc level, the signal RST1 is set to the high level, the transistor N2 is turned on, and the bit line BL0 is set to the ground level.

When the shift cell detection operation is started, the signal RST1 and the control signal RDVF are both switched to low level and the control signal CP is turned off.
After the YBCK is switched to the high level, the selected word line voltage VWL is changed stepwise in the order of, for example, VRD3 → VRD2 → VRD1 (see the top row of FIGS. 2 and 6), and then the control signal RDVF is After the high level and the control signal CPYBCK are switched to the low level, the selected word line voltage VWL is changed to, for example, VVF3 → VVF2 → VVF1 (FIG. 2).
And the voltage is changed stepwise in the order shown in FIG. 6).

As a preprocessing for shift cell detection, the signal Vref is set to low level, the transistor P1 is turned on, and the bit line BL0 is charged with the power supply voltage Vcc. After a certain period of time, the bit line BL
When the voltage of 0 increases and the potential difference between the gate and the source of the transistor H3 becomes equal to or lower than the threshold voltage Vth ', the transistor H3 is automatically turned off. Therefore, the bit line BL
0 is charged to (Vcc-Vth-Vth ') and the node SA
Becomes the Vcc level.

In the state described above, the selected word line voltage is set to a predetermined value, and the presence or absence of the cell current is reflected on the voltages of the bit line BL0 and the node SA to detect a shift cell. That is, when a voltage equal to or higher than the threshold voltage Vth of a predetermined memory cell transistor is supplied to its gate and a cell current flows, the voltage of the bit line BL0 drops and the transistor H3 turns on. Therefore, node SA
Falls substantially to the voltage VBL0 of the bit line BL0. When a voltage lower than the threshold voltage Vth of a predetermined memory cell transistor is supplied to its gate, no cell current flows and the voltage of the bit line BL0 does not drop. The voltage is kept at the Vcc level. The shift cell is detected based on this relationship.

When the charging of the bit line BL0 is completed, the signal Vref is set to a predetermined voltage (for example, 2 V) at which the transistor P1 can supply a current sufficient to compensate for the leakage current of the bit line BL0. In addition, the drain side select gate line DSG and the source side select gate line S
SG is set to the same predetermined high-level voltage as the non-selected word line voltage.

First, the write threshold voltage Vth is determined while the selected word line voltage VWL is set to VRD3. When the threshold voltage Vth of the memory cell transistor is distribution 31 or distribution 36, (Vth> VRD3
), No cell current flows, and the voltage of the node SA is maintained at the Vcc level.

When the pulse-like signals φLAT3 and φLAT4 are set to a high level after a predetermined time has elapsed, all of the transistors N14, N13, N9 and N32 are turned on, and the Q2 terminal of the latch circuit 3 is set to a low level. As a result, the / Q2 terminal is inverted from low level to high level. At this time, the gate of the transistor N16 connected to the / Q2 terminal goes high. When the pulse-like signal φLAT2 is set to the high level, the transistors N17, N16, N10 and N33 are turned on, the Q1 terminal of the latch circuit 3 is set to the low level, and the / Q1 terminal is changed from the low level to the high level. Flip to

On the other hand, when the threshold voltage Vth of the memory cell transistor is other than distribution 31 or distribution 36,
Since (VRD3> Vth), a cell current larger than the leakage compensation current flows, the voltage of the node SA drops, the transistor H3 turns on, and the capacitance CBL of the bit line BL0 and the capacitance CSA of the node SA (<< CBL) And the charge at the node SA becomes a low level (for example, 1 V) substantially equal to the bit line voltage VBL0. Therefore, the transistors N13 to N19 connected to the sources of the transistors N9 and N10 output signals φLAT1 to φLAT.
Even if turned on by LAT4, transistors N9 and N10
Is at a low level (for example, 1 V), the drains of the transistors N9 and N10
A high resistance state is set between the sources, and a current necessary for inverting the Q2 terminal and the Q1 terminal of the latch circuit 3 cannot flow. As a result, the set state is maintained.

When the determination of the write threshold voltage Vth in a state where the selected word line voltage VWL is set to VRD3 is completed, the signal Vref is set to the low level again, the transistor P1 is turned on, and the bit line BL0 is turned on. On the other hand, charging is performed at the power supply voltage Vcc. When the charging of the bit line BL0 is completed, the signal Vref becomes a voltage of a predetermined level (for example, 2
V).

Next, the write threshold voltage Vth is determined while the selected word line voltage VWL is set to VRD2. In the case where the threshold voltage Vth of the memory cell transistor is one of the distribution 31, the distribution 36, the distribution 32, and the distribution 37, since (Vth> VRD2), no cell current flows and the voltage of the node SA becomes It is kept at Vcc level.

When the pulse-like signals φLAT3 and φLAT4 are set to a high level after a lapse of a predetermined time, when the threshold voltage Vth of the memory cell transistor is distribution 32 or distribution 37, the transistor N1
4, N13, N9, and N32 are all turned on, and the latch circuit 3
Is set to low level, and the / Q2 terminal is inverted from low level to high level. If the threshold voltage Vth of the memory cell transistor is distribution 31 or distribution 36, the determination of the write threshold voltage Vth in a state where the selected word line voltage VWL has already been set to VRD3 indicates that the latch circuit 3 Is not changed because the / Q2 terminal is set to the low level and the / Q2 terminal is inverted from the low level to the high level.

On the other hand, when the threshold voltages Vth of the memory cell transistors are distributions 33 and 38, (VRD
2> Vth), a cell current larger than the leakage compensation current flows, the voltage of the node SA drops, the transistor H3 turns on, and the voltage of the node SA becomes the bit line voltage VBL.
It becomes a low level (for example, 1 V) having substantially the same potential as 0.
Therefore, a current required to invert the Q2 terminal of the latch circuit 3 cannot flow through the transistor N9, and as a result, the set state is maintained.

When the determination of the write threshold voltage Vth in a state where the selected word line voltage VWL is set to VRD2 is completed, the signal Vref is set to low level again, the transistor P1 is turned on, and the bit line BL0 is On the other hand, charging is performed at the power supply voltage Vcc. When the charging of the bit line BL0 is completed, the signal Vref becomes a voltage of a predetermined level (for example, 2
V).

Next, the write threshold voltage Vth is determined while the selected word line voltage VWL is set to VRD1. The threshold voltages Vth of the memory cell transistors are distribution 31, distribution 36, distribution 32, distribution 37, distribution 33,
In any of the distributions 38, since (Vth> VRD1), no cell current flows, and the voltage of the node SA becomes Vcc
Retained on level.

When the pulse-like signal φLAT1 is set to a high level after a lapse of a predetermined time, when the threshold voltage Vth of the memory cell transistor has the distribution 33 or the distribution 38, the gate of the transistor N18 is written. Since the transistors are still at the high level at the end, the transistors N19, N18, N10, and N33 are all turned on, and the Q1 terminal of the latch circuit 3 is set to the low level, and / Q1
The terminal is inverted from low level to high level. Note that the threshold voltage Vth of the memory cell transistor has a distribution 31,
In the case of any one of the distribution 36, the distribution 32, and the distribution 37,
In the determination of the write threshold voltage Vth performed by setting the selected word line voltage VWL to VRD3 and VRD2, the Q1 terminal of the latch circuit 3 is set to low level and the transistor N18 is turned off, It does not change.

On the other hand, when the threshold voltage Vth of the memory cell transistor is distribution 34, since (VRD1> Vth), a cell current larger than the leakage compensation current flows, and the voltage of the node SA drops and the transistor H3 turns on,
The voltage of the node SA becomes a low level (for example, 1 V) having substantially the same potential as the bit line voltage VBL0. Therefore, a current required to invert the Q1 terminal of the latch circuit 3 cannot flow through the transistor N10, and as a result, the set state is maintained.

At this point, the Q2 terminal of the latch circuit 3 and the Q2 terminal
The same data string as the write data to be written to the corresponding memory cell is stored in each of the one terminal, the / Q2 terminal, and the / Q1 terminal. That is, when the threshold voltages Vth are the distributions 31 and 36, (Q2, Q1, / Q
2, / Q1) = (0,0,1,1), and when the threshold voltage Vth is distribution 32 or distribution 37, (Q2,
Q1, / Q2, / Q1) = (0, 1, 1, 0),
When the threshold voltages Vth are distributions 33 and 38, (Q2, Q1, / Q2, / Q1) = (1, 0, 0,
1), and when the threshold voltage Vth is distribution 34,
(Q2, Q1, / Q2, / Q1) = (1, 1, 0, 0)
Becomes

When the determination of the write threshold voltage Vth with the selected word line voltage VWL set to VRD1 is completed, the control signal RDVF is switched to the high level and the control signal CPYBCK is switched to the low level. Thereafter, the signal Vref is set to the low level again, the transistor P1 is turned on, and the bit line BL0 is charged with the power supply voltage Vcc. When the charging of the bit line BL0 is completed, the signal Vref is set to a voltage of a predetermined level (for example, 2 V).

Next, shift cells (distribution 36) are detected in a state where the selected word line voltage VWL is set to VVF3. When the threshold voltage Vth of the memory cell transistor has the distribution 31, (Vth> VVF3), no cell current flows, and the voltage at the node SA is maintained at the Vcc level.

When the pulse-like signals φLAT3 and φLAT4 are set to a high level after a lapse of a predetermined time, all of the transistors N14, N13, N9 and N30 are turned on, and the / Q2 terminal of the latch circuit 3 goes to a low level. When set, the Q2 terminal is inverted from low level to high level. At this time, the gate of the transistor N18 connected to the Q2 terminal becomes high level. When the pulse-like signal φLAT1 is set to the high level, the transistors N19, N18, N10, and N31 are turned on, the / Q1 terminal of the latch circuit 3 is set to the low level, and the Q1 terminal is changed from the low level to the high level. Flip to

On the other hand, when the threshold voltage Vth of the memory cell transistor is other than the distribution 31, (VVF3> Vth)
, A cell current larger than the leak compensation current flows, the voltage of the node SA drops, the transistor H3 turns on, and the capacitance CBL of the bit line BL0 and the capacitance C of the node SA are increased.
Redistribution of charge occurs between SA (<< CBL) and the voltage of the node SA becomes a low level (for example, 1 V) substantially equal to the bit line voltage VBL0. Therefore, even if the transistors N13 to N19 connected to the sources of the transistors N9 and N10 are turned on by the signals φLAT1 to φLAT4, the gates of the transistors N9 and N10 are at a low level (for example, 1 V). Since the resistance between the drain and source of each of the transistors N9 and N10 is in a high resistance state, a current required to invert the Q2 terminal and the Q1 terminal of the latch circuit 3 cannot flow, and as a result, the set state is maintained. You.

When the detection of the shift cell in the state where the selected word line voltage VWL is set to VVF3 is completed, the signal Vref is set to the low level again, the transistor P1 is turned on, and the power supply voltage Vcc is applied to the bit line BL0. Is charged. When the charging of the bit line BL0 is completed, the signal Vref is set to a predetermined level voltage (for example, 2 V).

Next, shift cells (distribution 37) are detected in a state where the selected word line voltage VWL is set to VVF2. When the threshold voltage Vth of the memory cell transistor is one of the distribution 31, the distribution 36, and the distribution 32,
Since (Vth> VVF2), no cell current flows, and the voltage of the node SA is maintained at the Vcc level.

When the pulse-like signal φLAT3 is set to a high level after a lapse of a predetermined time, when the threshold voltage Vth of the memory cell transistor has a distribution 32,
Since the gate of the transistor N15 is at the high level, the transistors N14, N15, N9, and N30 are all turned on, the / Q2 terminal of the latch circuit 3 is set to the low level, and the Q2 terminal is inverted from the low level to the high level. I do. The threshold voltage Vth of the memory cell transistor
Is the distribution 31, the selected word line voltage VWL is already V
In the determination of the write threshold voltage Vth in the state set to VF3, no change occurs because the / Q2 terminal of the latch circuit 3 is set to the low level and the Q2 terminal is inverted from the low level to the high level. In the case of the distribution 36, in the determination of the write threshold voltage Vth in a state where the selected word line voltage VWL is already set to VRD3, the Q1 terminal of the latch circuit 3 is set to low level, and the transistor N15 is turned on. Since it is off, the setting state is maintained as it is.

On the other hand, when the threshold voltages Vth of the memory cell transistors are distribution 37, distribution 33 and distribution 38,
Since (VVF2> Vth), a cell current larger than the leakage compensation current flows, the voltage of the node SA drops, the transistor H3 turns on, and the voltage of the node SA becomes a low level having substantially the same potential as the bit line voltage VBL0. (For example, 1 V). Therefore, a current required to invert the Q2 terminal of the latch circuit 3 cannot flow through the transistor N9, and as a result, the set state is maintained.

When the detection of the shift cell in the state where the selected word line voltage VWL is set to VVF2 is completed, the signal Vref is set to the low level again, the transistor P1 is turned on, and the power supply voltage Vcc is applied to the bit line BL0. Is charged. When the charging of the bit line BL0 is completed, the signal Vref is set to a predetermined level voltage (for example, 2 V).

Finally, the shift cells (distribution 38) are detected with the selected word line voltage VWL set to VVF1. In the case where the threshold voltage Vth of the memory cell transistor is any of the distribution 31, the distribution 36, the distribution 32, the distribution 37, and the distribution 33, since (Vth> VVF1), no cell current flows and the node SA The voltage is kept at the Vcc level.

When the pulse-like signal φLAT1 is set to a high level after a lapse of a predetermined time, when the threshold voltage Vth of the memory cell transistor has a distribution 33,
Since the gate of the transistor N18 is at the high level, the transistors N19, N18, N10, and N31 are all turned on, the / Q1 terminal of the latch circuit 3 is set to the low level, and the Q1 terminal is inverted from the low level to the high level. I do. The threshold voltage V of the memory cell transistor
When th is the distribution 31 or the distribution 32, the / Q1 terminal of the latch circuit 3 is set to low level and the Q1 terminal is set to the low level in the detection of the shift cell which has already been performed by setting the selected word line voltage VWL to VVF3 and VVF2. The Q1 terminal does not change because it is inverted from low level to high level. Also, the threshold voltage Vth of the memory cell transistor
Is distribution 36, the selected word line voltage VWL is already
In the detection of the shift cell set to RD3, since the Q2 terminal of the latch circuit 3 is set to the low level and the transistor N18 is turned off, the set state is maintained as it is. Further, when the threshold voltage Vth of the memory cell transistor has the distribution 37, the Q2 terminal of the latch circuit 3 is set to the low level in the detection of the shift cell which has already been performed by setting the selected word line voltage VWL to VRD2. Since the transistor N18 is off, the set state is maintained as it is.

On the other hand, when the threshold voltage Vth of the memory cell transistor has the distribution 34, since (VVF1> Vth), a cell current larger than the leak compensation current flows, and the voltage of the node SA drops to reduce the transistor voltage. H3 turns on,
The voltage of the node SA becomes a low level (for example, 1 V) having substantially the same potential as the bit line voltage VBL0. Therefore, a current required to invert the Q1 terminal of the latch circuit 3 cannot flow through the transistor N10, and as a result, the set state at the time of standby is maintained.

The shift cell detection operation is performed in this manner. When the detection operation is completed, the write threshold voltage Vth of the memory cell transistor is applied to each of the Q2, Q1, / Q2, and / Q1 terminals of the latch circuit 3. Is stored. That is, the threshold voltage Vth
Is (Q2, Q1, / Q2, / Q1) = in any case of the distribution 31, the distribution 32, the distribution 33, and the distribution.
(1,1,0,0). When the threshold voltage Vth has a distribution 36, (Q2, Q1, / Q2, / Q1)
= (0,0,1,1), and when the threshold voltage Vth is distribution 37, (Q2, Q1, / Q2, / Q1) =
(0,1,1,0), and the threshold voltage Vth is distributed 3
In the case of 8, (Q2, Q1, / Q2, / Q1) =
(1, 0, 0, 1).

That is, at this stage, the data stored in the latch circuit 3 is determined to be (Q2, Q1) = (1, 1), and it is determined that the memory cell transistor is determined to be sufficiently written. The write operation and the verify operation are performed again only on the memory cell transistors other than (Q2, Q1) = (1, 1). At this time, in the first embodiment described above, at the time of writing, the Q
Since the same data string as the write data at the time of setting the two terminals and the Q1 terminal is stored in the latch circuit 3, the processing procedure of the conventional NAND flash memory is not changed, and other data is stored. The control unit connected via the data bus can shift to the rewrite operation and the verify operation without involving the determination process and the control process.

Therefore, the output of the judgment circuit 22 of the verification judgment circuit 5 is monitored, and when it is judged that the writing is not sufficient, the memory cell transistors not set to (Q2, Q1) = (1, 1) are used. Only conventional NAND
The write operation and the verify operation are repeated again in the same processing flow as the type flash memory, and it is determined that all the memory cell transistors are sufficient for the write operation, or the write operation and the verify operation are repeated a predetermined number of times. A series of operations ends at the stage when the operation is completed.

By repeating the shift cell detection operation, the write operation and the verify operation again,
The effect of AGL noise is greatly reduced, and reliability is improved. Note that even if rewriting is performed, if there are a plurality of memory cell transistors to be rewritten in the memory string sharing the source line, it is determined that the writing operation is not sufficient again by the shift cell detection operation due to a difference in writing speed. However, the lower limit of AGL noise can be increased by performing at least one rewrite, and the source potential of the memory cell transistor to be rewritten rises during verification. And the lower limit of the distribution of the AGL noise, and the fact that the difference in the number of times until the writing is determined to be sufficient is small, and the voltage of the selected word line during normal reading is small. The voltage difference between the data and the It is improved.

Next, a second embodiment in which the present invention is applied to a binary flash memory capable of recording data having two values in one memory cell transistor will be described with reference to FIGS. This will be described with reference to FIG. FIG. 7 shows a configuration of a main part of the NAND flash memory according to the second embodiment. FIG. 8 shows a signal state of each part in the NAND flash memory according to the second embodiment.

As shown in FIG. 7, the binary NAND flash memory according to the second embodiment of the present invention has a memory cell array 51, a data write control circuit 52, a latch circuit 53, and a transistor N54 comprising an n-channel MOS transistor. , N55 and N58, a latch control circuit 54, a verify determination circuit 55, and transistors N56 and N
And a shift cell detection circuit 56 composed of a shift cell detection circuit 57. In this NAND flash memory,
One memory cell array is composed of a plurality of blocks, and one block is composed of a plurality of pages in word line units. In the example shown in FIG. 7, one block = 16 pages. The memory cell array 51 has memory cells arranged in a matrix. As shown in FIG. 7, each memory cell is connected to a common word line WL.
A plurality of memory strings A0 connected to 0 to WL15
To An. In FIG. 7, the memory string A1
The rest is omitted. These memory strings A0
To An share a source line. One block is made up of a plurality of groups of memory strings sharing a source line, and has, for example, m (m> n) memory strings in total.

The memory string A0 is composed of memory cell transistors M _{0-0 to} M _15-0 . The drain of the memory cell transistor _M15-0 is connected to the source of the selection transistor DS0, and the drain of the selection transistor DS0 is connected to the bit line BL0. Further, the source of the memory cell transistor M _0-0 is the selection transistor S
The drain of S0 is connected, and the source of select transistor SS0 is connected to source line SL. Further, the gates of the memory cell transistors M _{0-0 to} M _15-0 are connected to the word lines WL0 to WL15, respectively. As described above, the memory string A0 is connected to each line, and the other memory strings have the same connection relationship.

Therefore, one ends of the memory strings A0 to An are connected to the bit lines BL0 to BLn via the selection transistors DS0 to DSn, and the other ends of the memory strings A0 to An are connected to the selection transistors SS0 to SSn.
Are connected to a common source line SL. The gates of the select transistors DS0 to DSn are connected to a common drain-side select gate line DSG, and the gates of the select transistors SS0 to SSn are connected to a common source-side select gate line SSG.

Note that the common source line SL to which the other ends of the memory strings A0 to An are connected via the selection transistors SS0 to SSn is connected to the selection transistors SS0 to SS
n and a source diffusion layer shared by
Is in contact with a metal bypass line (not shown) made of an Al wiring pattern exhibiting an extremely small resistance value. The source line SL is biased to a predetermined potential, for example, a ground level as needed by a metal bypass line.

The write control circuit 52 provided corresponding to the bit line BL0 includes a transistor H51 composed of an n-channel MOS transistor with a high breakdown voltage, a transistor P51 composed of a p-channel MOS transistor, and n
Transistor N5 composed of a channel MOS transistor
1 to N53. Note that bit line B
The write control circuits corresponding to L1 and thereafter have the same configuration, and description of these portions will be omitted for simplicity. Also, regarding other circuit portions, attention is paid only to a portion corresponding to the bit line BL0, and only the portion will be described.

In FIG. 7, reference numeral 66 denotes Vcc.
A power supply terminal to which, for example, (Vcc = 3.3 V) is supplied. The source of the transistor P51 is connected to the Vcc power supply terminal 66, and the drain of the transistor P51 is connected to the drain of the transistor N51 whose source is grounded. The reset signal RST1 is supplied to the gate of the transistor N51, and the signal Vref is supplied to the gate of the transistor P51.

A node SA2 which is a connection point between the drain of the transistor P51 and the drain of the transistor N51
And a bit line BL0, a transistor H51 is inserted, and transistors N52 and N53 connected in series between the node SA2 and the ground are inserted. Transistor N5
2 is supplied with the signal PGM to the gate of the transistor H5.
The signal PGMH is supplied to one gate.

The latch circuit 53 includes an inverter circuit 57,
The output terminal of the inverter circuit 58 is connected to the input terminal of the inverter circuit 57, and the common connection point is the / Q terminal. The input terminal of the inverter circuit 58 is connected to the output terminal of the inverter circuit 57, and the common connection point is the Q terminal.

The gate of the transistor N53 and the / Q terminal of the latch circuit 53 are connected. Further, transistors N56, N54 and N55 connected in series between the / Q terminal of the latch circuit 53 and the ground are inserted, and a transistor N58 is inserted between the Q terminal of the latch circuit 53 and the ground. Further, a transistor N57 is inserted between the drain of the transistor N54 and the Q terminal of the latch circuit 53.

A control signal R is applied to the gate of the transistor N56.
DVF is supplied. The control signal CPYBCK is supplied to the gate of the transistor N57. A node S which is a connection point between the gate of the transistor N54, the drain of the transistor P51, and the drain of the transistor N51
A2 is connected. The signal φLAT is supplied to the gate of the transistor N55, and the transistor N58
Is supplied with a signal RST2.

The verify determination circuit 55 includes, for example, an inverter circuit 65, a transistor N71 comprising an n-channel MOS transistor, and a determination circuit 72. The input terminal of the inverter circuit 65 is grounded, and the output terminal of the inverter circuit 65 is connected to the determination circuit 72. A transistor N71 is inserted between the output terminal of the inverter circuit 65 and the ground. The gate of the transistor 71 and the / Q terminal of the latch circuit 53 are connected.
The determination circuit 72 determines whether or not the writing has been completed for all the memory cell transistors during the writing operation based on the potential of the output line of the inverter circuit 65. In addition,
The judgment output of the judgment circuit 72 is taken out via a terminal 69 and supplied to another control circuit.

A binary NAN configured as described above
In a D-type flash memory, one-bit binary data is recorded in one memory cell transistor. FIG. 10 shows the relationship between the distribution of the threshold voltage Vth of binary data consisting of one bit and the data content. FIG.
As shown by 0, the threshold voltage Vth of the memory cell transistor takes two states.

In FIG. 10, reference numeral 110 indicates the distribution of memory cell transistors in which data "0" is written and which is in a write state with a positive threshold value.
Reference numeral 111 at 0 indicates the distribution of the memory cell transistors into which the data “1” is written and the erased state of the negative threshold voltage is set.

The write, read, verify, and shift cell detection operations in the above-described NAND flash memory will be described below. First, the write operation will be specifically described.

At the time of standby, signal PGM is set to low level (ground level), transistor N52 is turned off, and bit line BL0 is disconnected from write control circuit 52. Then, the signal RST1 becomes high level (Vcc
Level). Thereby, the transistor N51
Is turned on, and the bit line BL0 is set to the ground level.
Further, the control signal RDVF is set to a high level, and the control signal CPYBCK is set to a low level.

When writing is started in this state, write data is transferred to the latch circuit 5 via the data bus.
3, and the write data is taken into the latch circuit 53 and held. Thereafter, the signal RST1 is switched to the low level, and the bit line BL0 is disconnected from the ground line. Then, the signal PGMH is set to P5V (voltage of 5 to 6V), the signal Vref is set to low level, the transistor P1 is turned on, and the bit line BL0 is charged to Vcc.

At this time, signal PGM and signal φLAT and signal R for controlling the read / verify operation are provided.
ST2 is at a low level so that the latch data is not affected, and the transistors N52, N55, and N58 are off. Further, the drain-side selection gate line DSG of the memory cell array 1 is set to a high level, and the source-side selection gate line SSG of the memory cell array 1 is set to a low level.

Then, the signal Vref is switched to the Vcc level, the transistor P51 is turned off, the signal PGM is set to the high level, and the transistor N52 is switched on. Thus, the selected bit line BL0 is connected to the write control circuit 52, and the selected bit line BL0 is set to a voltage according to the write data.

For example, when the memory string A0 is selected as a write target and the write data is “0”, the Q terminal of the latch circuit 53 is set to low level,
The / Q terminal goes high. Therefore, transistor N
53 turns on, and the bit line BL0 is discharged to the ground level.

When the write data is "1", the Q terminal of the latch circuit 53 is set to the high level, and the / Q terminal is set to the low level. Therefore, the transistor N53 is not turned on, and the bit line BL0 is kept at the Vcc level which is the precharge voltage.

After the bit line BL0 connected to the selected memory string A0 is set to the voltage corresponding to the write data, the word lines WL0 to WL
The selected word line connected to the memory cell transistor to be written in 15 is set to the write voltage VPGM, and the unselected word line connected to the memory cell transistor not to be written is set to the write pass voltage. Vpass (<VPGM) is set, and data is written to a predetermined memory cell transistor.

At this time, if the write data is "0", the FN tunneling phenomenon occurs due to the electric field between the word line voltage VPGM and the channel voltage, and the write is performed. In the case of write data "1", the channel is disconnected from the bit line BL0 by the selection transistor DS0, and is boosted to a non-write potential by the coupling capacitance with the word line, and is not written.

Next, the normal read operation will be specifically described. It is assumed that the memory string A0 has been selected as a read target. During standby,
The signal PGM is set to the low level (ground level), the transistor N52 is turned off, and the bit line BL0 is disconnected from the write control circuit 52. Also, the signal Vre
f is set to the Vcc level, the signal RST1 is set to the high level, and the transistor N51 is turned on.
Bit line BL0 is set to the ground level. Further, the control signal RDVF is set to a high level, and the control signal CPYBCK is set to a low level.

When the normal read operation is started, the read operation is performed by resetting the latch circuit 53 by clocking the signal RST2 and switching the signal RST1 to the low level, and then changing the selected word line voltage VWL to, for example, VRD. Set and done. Further, as a pre-process for determining the actual write threshold voltage Vth at the word line voltage VRD, the signal Vref is set to a low level, the transistor P51 is turned on, and the bit line BL0 is charged with the power supply voltage Vcc. Is made. After a certain period of time, the bit line B
When the voltage of L0 rises and the potential difference between the gate and source of the transistor H51 becomes equal to or lower than the threshold voltage Vth ', the transistor H51 is automatically turned off. Accordingly, the bit line BL0 is charged to (Vcc-Vth-Vth '), and the node SA2 goes to the Vcc level.

In the above state, the selected word line voltage is set to V
The write threshold voltage Vth is determined by reflecting the presence or absence of the cell current on the voltage of the bit line BL0 and the node SA2. When the charging of the bit line BL0 is completed,
The signal Vref is set to a voltage of a predetermined level (for example, 2 V) at which the transistor P51 can flow a current enough to compensate for the leak current of the bit line BL0, and
The drain-side selection gate line DSG and the source-side selection gate line SSG are set to the same predetermined high-level voltage as the non-selected word line voltage.

Then, the write threshold voltage Vth is determined with the selected word line voltage VWL set to VRD. When the threshold voltage Vth of the memory cell transistor has a distribution 110 (see FIG. 10), (Vth> VRD)
Therefore, no cell current flows, and the voltage of the node SA2 is maintained at the Vcc level.

When the pulse-like signal φLAT is set to a high level after a lapse of a predetermined time, the transistor N
55, N54 and transistor N56 are both turned on,
When the / Q terminal of the latch circuit 53 is set to low level,
The terminal is inverted from low level to high level.

On the other hand, when the threshold voltage Vth of the memory cell transistor has a distribution 111 (see FIG. 10), (V
Since RD> Vth), a cell current larger than the leakage compensation current flows, the voltage of the node SA2 drops, the transistor H51 turns on, and the capacitance CBL of the bit line BL0 and the capacitance CSA of the node SA2 (<< CBL) , The voltage of the node SA2 becomes a low level (for example, 1 V) substantially equal to the bit line voltage VBL0. Therefore, even if the transistor N55 connected to the source side of the transistor N54 is turned on by the signal φLAT,
When the gate of the transistor N54 is at a low level (for example, 1
V), a high resistance state is established between the drain and the source of the transistor N54, and the Q
The current required to reverse the terminal cannot be passed,
As a result, the setting state is maintained.

The normal read operation is performed in this manner. When the normal read operation is completed, the Q
An output corresponding to the write threshold voltage Vth of the memory cell transistor is held at each of the terminal and the / Q terminal.
That is, the threshold voltage Vth is distributed 110 (see FIG. 10).
, (Q, / Q) = (1,0), and when the threshold voltage Vth has a distribution 111 (see FIG. 10),
(Q, / Q) = (0, 1).

Next, the verify operation will be specifically described. It is assumed that the memory string A0 has been selected as a verification target. At the end of writing, the signal PGM is set to low level (ground level), the transistor N52 is turned off, and the bit line BL0 is disconnected from the write control circuit 52. Further, the signal Vref is set to the Vcc level, and the signal RST1 is set.
Is set to the high level, the transistor N51 is turned on, and the bit line BL0 is set to the ground level. Further, the control signal RDVF is set to a high level, and the control signal CPYBCK is set to a low level.

In the verify operation, each time one write is completed, the write threshold voltage Vth corresponding to data "0" is determined. This write threshold voltage V
The determination of th is made by setting the selected word line voltage VWL to, for example, VVF after the signal RST1 is switched to the low level.

First, as a pre-process for determining the actual write threshold voltage Vth at each word line voltage, the signal Vref is set to low level to turn on the transistor P51,
The bit line BL0 is charged with the power supply voltage Vcc. After a certain period of time, the voltage of the bit line BL0 increases, and when the potential difference between the gate and the source of the transistor H51 becomes equal to or lower than the threshold voltage Vth ', the transistor H51 is automatically turned off. Therefore, the bit line BL0
Is charged to (Vcc−Vth−Vth ′), and the node SA2
Becomes the Vcc level.

In the above state, the selected word line voltage is set to V
The write threshold voltage Vth is determined by reflecting the presence or absence of the cell current on the voltage of the bit line BL0 and the node SA2. When the charging of the bit line BL0 is completed,
The signal Vref is set to a voltage of a predetermined level (for example, 2 V) at which the transistor P51 can flow a current enough to compensate for the leak current of the bit line BL0, and
The drain-side selection gate line DSG and the source-side selection gate line SSG are set to the same predetermined high-level voltage as the non-selected word line voltage.

First, the selected word line voltage VWL is set to VVF, and the write threshold voltage Vth corresponding to the write data "0" is determined. When the threshold voltage Vth of the memory cell transistor has a distribution 110 (see FIG. 10), since (Vth> VVF), no cell current flows, and
The voltage of node SA2 is maintained at Vcc level.

When a pulse-like signal φLAT is set to a high level after a lapse of a predetermined time, the transistor N
55, N54 and transistor N56 are both turned on,
When the / Q terminal of the latch circuit 53 is set to low level,
The terminal is inverted from low level to high level.

On the other hand, when the threshold voltage Vth of the memory cell transistor has the distribution 111 (see FIG. 10), (V
Since VF> Vth), a cell current larger than the leakage compensation current flows, the voltage of the node SA2 drops, the transistor H51 turns on, and the capacitance CBL of the bit line BL0 and the capacitance CSA of the node SA2 (<< CBL) , The voltage of the node SA2 becomes a low level (for example, 1 V) substantially equal to the bit line voltage VBL0. Therefore, even if the transistor N55 connected to the source side of the transistor N54 is turned on by the signal φLAT,
When the gate of the transistor N54 is at a low level (for example, 1
V), a high resistance state is established between the drain and the source of the transistor N54, and the Q
The current required to reverse the terminal cannot be passed,
As a result, the setting state is maintained.

The verify operation is performed as described above.
When the verify operation is completed, the Q terminal of the latch circuit 53,
An output corresponding to the result of checking the write threshold voltage Vth of the memory cell transistor is held at each of the / Q terminals. That is, when it is confirmed that the writing is sufficient, the Q terminal and the / Q terminal of the latch circuit 53 are connected to (Q,
/ Q) = (1, 0).

The operation of the shift cell detection circuit 56 according to the second embodiment will be described below. In addition,
In this case, the shift cell detection operation is performed by the control signal R
DVF is set to a high level and the control signal CP
In a state where YBCK is set to the low level, for example, after the writing in page units is completed, that is, after the normal write operation and the verify operation are performed and it is determined that all the memory cells to be written are sufficiently written, the operation is continuously performed. And all the Q terminals of the latch circuit 53 have Q = 1.
It is assumed that the processing is started from the state set in. It is also assumed that the memory string A0 has been selected as a shift cell detection target.

At the end of writing, the signal PGM is set to low level (ground level), the transistor N52 is turned off, and the bit line BL0 is disconnected from the write control circuit 52. Further, the signal Vref is set to the Vcc level, the signal RST1 is set to the high level, the transistor N51 is turned on, and the bit line BL0 is set to the ground level.

When the shift cell detection operation is started, the signal RST1 and the control signal RDVF are both switched to low level, and the control signal CP is turned off.
After YBCK is switched to the high level, reading is performed by setting the selected word line voltage VWL to, for example, VRD, and then the control signal RDVF is at the high level and the control signal CPYB
After CK is switched to the low level, reading is performed by setting the selected word line voltage VWL to, for example, VVF (see FIGS. 10 and 8).

As a pre-process for detecting a shift cell, the signal Vref is set to a low level and the transistor P51
Is turned on, and the bit line BL0 is charged with the power supply voltage Vcc. After a certain period of time, the voltage of the bit line BL0 rises and the gate of the transistor H51
When the potential difference between the sources becomes equal to or lower than the threshold voltage Vth ', the transistor H51 is automatically turned off. Accordingly, the bit line BL0 is charged to (Vcc-Vth-Vth '), and the node SA2 goes to the Vcc level.

In the above state, the selected word line voltage is set to a predetermined value, and the presence or absence of the cell current is reflected on the voltages of the bit line BL0 and the node SA2, thereby detecting a shift cell. That is, when a voltage equal to or higher than the threshold voltage Vth of a predetermined memory cell transistor is supplied to its gate and a cell current flows, the voltage of the bit line BL0 drops and the transistor H51 turns on. Therefore, node S
The voltage of A2 substantially drops to the voltage VBL0 of the bit line BL0. When a voltage lower than the threshold voltage Vth of a predetermined memory cell transistor is supplied to its gate, no cell current flows and the voltage of the bit line BL0 does not drop. The voltage is V
Held at cc level. The shift cell is detected based on this relationship.

When the charging of bit line BL0 is completed, signal Vref is set to a voltage of a predetermined level (for example, 2 V) at which transistor P51 can supply a current sufficient to compensate for the leakage current of bit line BL0. At the same time, the drain-side selection gate line DSG and the source-side selection gate line SSG are set to the same predetermined high-level voltage as the non-selected word line voltage.

First, the write threshold voltage Vth is determined with the selected word line voltage VWL set to VRD. When the threshold voltage Vth of the memory cell transistor is distribution 110 or distribution 112 (see FIG. 10), since (Vth> VRD), no cell current flows, and the voltage of the node SA2 is maintained at the Vcc level. Is done.

When the pulse-like signal φLAT is set to a high level after a lapse of a predetermined time, the transistor N
Both 55, N54 and N57 are turned on, the Q terminal of the latch circuit 53 is set to low level, and the / Q terminal is inverted from low level to high level.

On the other hand, when the threshold voltage Vth of the memory cell transistor has the distribution 111, since (VRD> Vth), a cell current larger than the leakage compensation current flows, and the voltage of the node SA2 drops to reduce the transistor voltage. H51 is turned on, and the capacitance CBL of the bit line BL0 and the capacitance C
Redistribution of charge occurs between SA (<< CBL) and the voltage of the node SA2 becomes a low level (for example, 1 V) substantially equal to the bit line voltage VBL0. For this reason, the transistor N connected to the source side of the transistor N54
55 is turned on by the signal φLAT, the transistor N
Since the gate of the transistor 54 is at a low level (for example, 1 V), a high resistance state is set between the drain and the source of the transistor N54, and a current necessary for inverting the / Q terminal of the latch circuit 53 flows. Cannot be performed, and as a result, the setting state is maintained.

At this point, the Q terminal of the latch circuit 53, /
Each of the Q terminals stores the same data string as the write data to be written to the memory cell to be detected.
That is, when the threshold voltage Vth is equal to the distribution 110 and the distribution 11
2, (Q, / Q) = (0,1), and when the threshold voltage Vth is distribution 111, (Q, / Q) =
(1, 0).

When the determination of the write threshold voltage Vth in a state where the selected word line voltage VWL is set to VRD is completed, the control signal RDVF is switched to a high level, and the control signal CPYBCK is switched to a low level. Again, the signal Vref is set to low level, the transistor P51 is turned on, and the bit line BL0 is charged with the power supply voltage Vcc. When the charging of the bit line BL0 is completed, the signal Vref becomes a voltage of a predetermined level (for example,
2V).

Next, shift cells are detected in a state where the selected word line voltage VWL is set to VVF. The threshold voltage Vth of the memory cell transistor is distributed 110 (FIG. 1).
In the case of (0), since (Vth> VVF), no cell current flows, and the voltage of the node SA2 is kept at the Vcc level.

When the pulse-like signal φLAT is set to a high level after a predetermined time has elapsed, the transistor N
Both 55, N54 and N56 are turned on, the / Q terminal of the latch circuit 53 is set to low level, and the Q terminal is inverted from low level to high level.

On the other hand, when the threshold voltage Vth of the memory cell transistor is distribution 112 or distribution 111,
Since (VVF> Vth), a cell current larger than the leakage compensation current flows, the voltage of the node SA2 drops, the transistor H51 turns on, and the capacitance CBL of the bit line BL0 and the capacitance CSA of the node SA2 (<< CBL) Between the bit line voltage VBL and the bit line voltage VBL.
It becomes a low level (for example, 1 V) having substantially the same potential as 0.
Therefore, even if the transistor N55 connected to the source side of the transistor N54 is turned on by the signal φLAT, the gate of the transistor N54 is at a low level (for example, 1 V). The latch circuit 5 is set to a high resistance state.
The current necessary for inverting the Q terminal of No. 3 cannot be passed, and as a result, the set state is maintained.

Thus, the shift cell detection operation is performed. When the detection operation is completed, the determination result corresponding to the write threshold voltage Vth of the memory cell transistor is stored in each of the Q terminal and / Q terminal of the latch circuit 53. Is done. That is, when the threshold voltage Vth is the distribution 110 or the distribution 111, (Q, /
Q) = (1,0), and when the threshold voltage Vth is the distribution 112, (Q, / Q) = (0,1).

That is, at this stage, the reliability of the memory cell transistor in which the data stored in the latch circuit 53 is determined to be (Q, / Q) = (1, 0) and it is determined that writing is sufficient should be sufficiently ensured. The write operation and the verify operation are performed again only on the memory cell transistor where (Q, / Q) = (0, 1). At this time, in the other embodiment described above, the same data string as the write data when the Q terminal of the latch circuit 53 is set at the time of writing is stored in the latch circuit 53.
It is possible to shift to the rewrite operation and the verify operation without changing the processing procedure of the ND type flash memory and without involving the determination processing and the control processing in the control unit connected via another data bus. It is possible.

Therefore, the output of the judgment circuit 72 of the verify judgment circuit 55 is monitored, and when it is judged that the writing is not sufficient, the conventional NAND circuit is used only for the memory cell transistors not set to (Q = 1). The write operation and the verify operation are repeated again in the same processing flow as the type flash memory, and it is determined that all the memory cell transistors are sufficient for the write operation, or the write operation and the verify operation are repeated a predetermined number of times. A series of operations ends at the stage when the operation is completed.

According to the second embodiment, the binary type N
In the AND-type flash memory, the same advantages as in the first embodiment can be obtained.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above embodiments, and various modifications based on the technical concept of the present invention are possible. For example, in the above-described first and second embodiments, the shift cell detection operation is performed after the writing in page units is completed. However, the shift cell detection operation is performed after the writing of all the blocks is completed. It may be performed for each page. When the shift cell detection operation is performed after the writing of all the blocks is completed, the operation is performed after setting all the data of the Q1 and Q2 terminals of the latch circuit 3 or the data of the Q terminal of the latch circuit 53 to high level. .

In the above-described first and second embodiments, the present invention is applied to a NAND flash memory capable of storing 2-bit and 1-bit data in one memory cell transistor. Although the case has been described, the present invention can also be applied to a NAND flash memory capable of storing data of three bits or more in one memory cell transistor.

[0191]

According to the present invention, since the influence of AGL noise is greatly reduced, a margin for data retention characteristics can be easily secured, and reliability can be improved. Further, according to the present invention, the shift cell detection result becomes the same data string as the write data, and the shift cell detection result obtained for the latch circuit storing the write data can be stored. Thus, the circuit can be simplified and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a main part of a conventional NAND flash memory.

FIG. 2 is a schematic diagram showing a relationship between a threshold voltage and data content when storing 4-bit data composed of 2 bits in one memory cell transistor;

FIG. 3 is a timing chart for explaining a normal read operation in the NAND flash memory shown in FIG. 1;

FIG. 4 is a timing chart for explaining a verify operation in the NAND flash memory shown in FIG. 1;

FIG. 5 is a circuit diagram showing a configuration of a main part of the NAND flash memory according to the first embodiment of the present invention;

FIG. 6 is a timing chart for explaining a shift cell detection operation in the NAND flash memory according to the first embodiment of the present invention;

FIG. 7 is a circuit diagram showing a configuration of a main part of a NAND flash memory according to a second embodiment of the present invention;

FIG. 8 is a timing chart for explaining a shift cell detection operation in a NAND flash memory according to a second embodiment of the present invention;

FIG. 9 is a circuit diagram showing an example of a configuration of a memory cell array of a NAND flash memory.

FIG. 10 is a schematic diagram showing a relationship between a threshold voltage and data contents when one-bit binary data is stored in one memory cell transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Write control circuit, 3 ... Latch circuit, 4 ... Latch control circuit, 5
... Verify judgment circuit, 6 ... Shift cell detection circuit, A0, A1 ... Memory string, WL0-WL
15 ... word line, BL0, BL1 ... bit line,
SL: Source line

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 29/792

Claims (10)

[Claims] An amount of charge stored in a charge storage unit changes according to a voltage applied to a word line and a bit line, and a threshold voltage changes according to the change. A memory cell for storing value data, writing predetermined data into the memory cell in page units, and performing a verify operation to check whether sufficient writing has been performed on the memory cell; Is set to a first read voltage to read data stored in the memory cell, and at the time of normal reading of the memory cell, the voltage applied to the word line is set lower than the first read voltage. 2. A nonvolatile semiconductor memory device that reads data stored in the memory cell by setting the read voltage to 2 is a data holding data to be stored in the memory cell. Control means for determining data stored in the memory cell based on the voltage state of the bit line, and controlling the determination result to be stored in the data storage means; Detecting means for detecting a memory cell having a threshold voltage distributed between the first read voltage and the second read voltage after completion of data writing; Rewriting data in a memory cell having a threshold voltage distributed between a voltage and the second read voltage so that the threshold voltage is equal to or higher than the first read voltage. A non-volatile semiconductor storage device comprising: 2. The non-volatile semiconductor memory device according to claim 1, wherein said detecting means comprises a plurality of switching elements inserted between said data holding means and said control means. 3. The detecting means sets a voltage applied to a word line to the second read voltage and reads the memory cell, thereby setting a threshold voltage equal to or higher than the second read voltage. After detecting the memory cells having
By setting the voltage applied to the word line to the first read voltage and reading the memory cell, of the memory cells detected as having a threshold voltage equal to or higher than the second read voltage, A memory cell having a threshold voltage equal to or higher than the first read voltage is separated from a memory cell having a threshold voltage distributed between the first read voltage and the second read voltage. 2. The non-volatile semiconductor storage device according to claim 1, wherein the detection is performed. 4. The data holding means comprises: a first node for storing data to be stored in the memory cell;
And a second node for storing an inverted signal of the second node, and the detecting means is inserted between the first node and the second node of the data holding means and the control means, respectively. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising a plurality of switching elements for controlling a connection state between said data holding means and said control means. 5. The reading means sets a voltage applied to a word line to the second read voltage and reads the memory cell, thereby setting a threshold voltage equal to or higher than the second read voltage. After detecting the memory cells having
By setting the voltage applied to the word line to the first read voltage and reading the memory cell, of the memory cells detected as having a threshold voltage equal to or higher than the second read voltage, A memory cell having a threshold voltage equal to or higher than the first read voltage is separated from a memory cell having a threshold voltage distributed between the first read voltage and the second read voltage. Detect
At this time, when reading the memory cell by setting the voltage applied to the word line to the second read voltage, the control means is connected to the first node of the data holding means so as to be connected to the first node. The switching state of the plurality of switching elements is controlled, and the voltage applied to the word line is controlled by the first voltage.
When reading out the memory cell by setting the read voltage to a predetermined value, the control means controls the open / close state of the plurality of switching elements so as to be connected to the second node of the data holding means. 5. The nonvolatile semiconductor memory device according to claim 4, wherein 6. The memory according to claim 1, wherein said detecting means detects a memory cell having a threshold voltage distributed between said first read voltage and said second read voltage, and outputs the detected result to said memory. The data is stored in the data holding means so as to become the same data string as the data to be stored in the cell, and a detection result obtained when a memory cell having a threshold voltage equal to or higher than the first read voltage is detected is obtained. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said memory cell is stored in said data holding means so as to be in the same data row as data in which said memory cell is in a non-writing state. 7. The non-volatile semiconductor storage device according to claim 6, wherein said non-volatile semiconductor storage device further comprises a determination unit for determining whether or not to perform rewriting based on an output of said data holding unit. Storage device. 8. The nonvolatile semiconductor memory according to claim 1, wherein said detecting means and said writing means perform a detecting operation and a rewriting operation for each page after writing in page units is completed. apparatus. 9. The apparatus according to claim 1, wherein said detecting means and said writing means perform a detecting operation and a rewriting operation for each page in the block after writing of all blocks is completed. Nonvolatile semiconductor memory device. 10. The nonvolatile semiconductor memory device according to claim 1, wherein said memory cell stores multi-valued data of three or more values.