KR20120042274A - Flash memory device and operating method thereof - Google Patents

Flash memory device and operating method thereof Download PDF

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Publication number
KR20120042274A
KR20120042274A KR1020100103891A KR20100103891A KR20120042274A KR 20120042274 A KR20120042274 A KR 20120042274A KR 1020100103891 A KR1020100103891 A KR 1020100103891A KR 20100103891 A KR20100103891 A KR 20100103891A KR 20120042274 A KR20120042274 A KR 20120042274A
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KR
South Korea
Prior art keywords
bit line
voltage
sensing
level
read
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KR1020100103891A
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Korean (ko)
Inventor
조가영
Original Assignee
에스케이하이닉스 주식회사
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Priority to KR1020100103891A priority Critical patent/KR20120042274A/en
Publication of KR20120042274A publication Critical patent/KR20120042274A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes

Abstract

A read operation method of a flash memory device is disclosed. The read operation method may include: a first precharge step of precharging a bit line to a high level; a first sensing step of sensing a voltage change of the bit line by applying a first read voltage to a selected word line; A second step of sensing the voltage change of the bit line by applying a second read voltage to the selected word line, and an intermediate step of making the intermediate level between the low level and the low level, a second precharge step of precharging the bit line to a high level. Steps.

Description

Flash memory device and its operation method {FLASH MEMORY DEVICE AND OPERATING METHOD THEREOF}

The present invention relates to a flash memory device and an operating method, and more particularly, to a method of reading data in a multi-level cell (MLC) based flash memory device.

Semiconductor memory devices are classified into volatile memory and non-volatile memory according to whether data is preserved when power supply is interrupted. Flash memory is one of non-volatile memory. It has the advantages of RAM, which is free to write and delete data, and ROM, which can preserve stored data without supplying power. It is widely used as a storage medium for numerous digital devices such as PDAs, smart phones, and digital cameras.

Recently, in order to further improve the density of flash memory, a multi-bit cell capable of storing a plurality of bits of data in one memory cell is used. Such a memory cell is called a multi-level cell (MLC).

1A is a diagram illustrating a threshold voltage distribution of a multi-level cell.

As shown in FIG. 1A, a multi-level cell can generally store two bits of data in one cell and have four data storage states (A, B, C, D). The cells of each state store data of "11" (A), "10" (B), "00" (C), and "01" (D) in the order of "MSB, LSB".

VR1 to VR3 denote read voltages applied to selected word lines during a read operation for reading data stored in multi-level cells, and VP denotes pass voltages applied to unselected word lines.

1B and 1C are diagrams for describing a read operation of a multi-level cell.

The data read operation of the multi-level cell is divided into an LSB read operation and an MSB read operation.

In the case of the LSB, as illustrated in FIG. 1B, data may be read through two sensing operations by applying VR1 and VR3 as read voltages to the selected word line.

In the case of the MSB, as shown in FIG. 1C, VR2 is applied as the read voltage to the selected word line to read data through one sensing operation.

As such, in order to read two bits of data stored in the multi-level cell, a total of three sensing operations must be performed, and two sensing operations for LSB reading are continuously performed.

2 is a diagram illustrating a memory cell array of a flash memory device, and FIG. 3 is a timing diagram illustrating a read operation process according to the prior art in the memory cell array of FIG. 2.

A case where the LSB of the selected memory cell 203 is read will be described. Assume that the memory cell 203 is programmed to the B state of FIG. 1A. That is, the LSB value is "0".

First, the bit line BLe is precharged to the high level 1V, a bias voltage of 4.5V is applied to the DSL, and the transistor 201 is turned on. The read voltage VR1 is selected for the selected word line Sel_WL. The pass voltage VP is applied to the unlined word line Unsel_WL.

Subsequently, when a bias voltage of 4.5V is applied to the SSL and the transistor 205 is turned on, an operation of sensing a voltage change of the bit line BLe is performed. Since the threshold voltage of the memory cell 203 is higher than the read voltage VR1, the voltage of the bit line BLe is maintained at a high level.

After the sensing operation, the DSL, SSL and word lines are initialized, and the bit line BLe is discharged to the low level (0V).

Subsequently, the bit line BLe is again precharged to a high level (1 V), a bias voltage of 4.5 V is applied to the DSL, a read voltage VR3 is selected to the selected word line Sel_WL, and an unselected word line Unsel_WL to the unselected word line. The pass voltage VP is applied.

When a bias voltage of 4.5 V is applied to the SSL and the transistor 205 is turned on, the voltage of the bit line BLe is similarly sensed. This time, the read voltage VR2 applied to the memory cell 203 is greater than the threshold voltage. Since the charge of the bit line BLe falls to the source line SL, the voltage of the bit line BLe falls to the low level (0V).

Through this two sensing operations, the LSB value stored in the memory cell 203 may be found to be “0”.

As described above, when the read operation is performed on the multi-level cell, since the selected bit line is sensed several times, the operation of precharging the same bit line to the high level and discharging it back to the low level is repeated. However, in the conventional method, even after the first sensing operation is performed by precharging the selected bit line, even if the voltage of the bit line is maintained at the high level, the battery device discharges the battery to a low level for the next sensing operation and then precharges it again to a high level. Since the process, there is a problem that a lot of current and time is consumed during the read operation.

The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a method of operating a flash memory device which can reduce current and time consumed during a read operation.

A read operation method of a flash memory device according to an embodiment of the present invention includes a first precharge step of precharging a bit line to a high level, and applying a first read voltage to a selected word line to change a voltage of the bit line. A first sensing step of sensing a voltage, an intermediate step of making the bit line an intermediate level between a high level and a low level, a second precharge step of precharging the bit line to a high level, and applying a second read voltage to the selected word line. And applying a second sensing step of sensing a voltage change of the bit line, and generating a first latch voltage in response to the first sensing result, in response to the first latch voltage and the second sensing result. The method may further include generating a second latch voltage and reading data corresponding to the second latch voltage.

In the intermediate step, the bit line may be brought to an intermediate level by applying the first latch voltage to the bit line.

According to an exemplary embodiment of the present invention, a flash memory device includes a memory cell array including a plurality of memory cells and a first sensing operation by precharging a bit line to a high level to read data written to a selected memory cell among the plurality of memory cells. The control circuit may include a control circuit configured to perform a second sensing operation by precharging the bit line to a high level after the bit line is made an intermediate level between a high level and a low level.

The control circuit may apply a first latch voltage generated as a result of the first sensing to the bit line to bring the bit line to an intermediate level after the first sensing operation.

According to the present invention, after performing the first sensing operation, instead of discharging the bit line to the low level, the bit line is made into an intermediate level between the high level and the low level, and then precharged to the high level again to perform the second sensing operation. The current consumed during the read operation can be reduced.

Also, in the precharge period for the second sensing, the bit line is precharged from the intermediate level to the high level instead of the low level, thereby reducing the time required for the read operation.

1A is a diagram illustrating threshold voltage distribution of a multi-level cell.
1B and 1C are diagrams for explaining a read operation of a multi-level cell.
2 illustrates a memory cell array of a flash memory device.
3 is a timing diagram illustrating a read operation process according to the prior art in the memory cell array of FIG.
4 is a flowchart illustrating a read operation method of a flash memory device according to the present invention;
FIG. 5 is a circuit diagram of a flash memory device in which the read operation method of FIG. 4 is performed. FIG.
6 is a timing diagram for explaining an intermediate step S405 and a second precharge step S407 of FIG.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

4 is a flowchart illustrating a read operation method of a flash memory device according to an exemplary embodiment of the present invention, and FIG. 5 is a circuit diagram of a flash memory device in which the read operation method of FIG. 4 is performed.

Since the read operation method according to the present invention can be applied to a multi-level cell (MLC) based flash memory device, it is assumed that all of the memory cells shown in FIG. 5 are multi-level cells. Each cell may have four data storage states A, B, C, and D as shown in FIG. 1A.

4 and 5, in the read operation method, a first precharge step S401 for precharging the selected bit line BLe to a high level 1V and a first read voltage VR1 using a first read voltage VR1 is performed. Performing a sensing operation (S403), an intermediate step (S405) of making the bit line (BLe) an intermediate level, a second precharge step (S407) of precharging the bit line (BLe) to a high level (1V), and A second sensing operation is performed using the second read voltage VR3 (S409) and a data read operation (S411). Here, the performing of the first sensing operation S403 may include generating a first latch voltage in response to the first sensing result, and the performing of the second sensing operation S409 may include a first latch voltage and a second latching voltage. And generating a second latch voltage in response to the sensing result.

5, the process of reading the LSB of the selected memory cell 503 will be described sequentially. The MSB can be read by one sensing operation using the read voltage VR2, which is the same as a well-known conventional method, and thus a detailed description thereof will be omitted.

In the first precharge step S401, the PRECHb signal is activated low to increase the voltage of the SO node, and the PBSENSE signal and the BSLe signal are activated high to enable the bit line BLe to be at a high level (1V). Precharged to At the same time, a bias voltage of 4.5V is applied to the DSL to turn on the transistor 501, the first read voltage VR1 is applied to the selected word line Sel_WL, and the pass voltage VP is applied to the unselected word line Unsel_WL. Is applied.

In the first sensing operation S403, a bias voltage of 4.5V is applied to SSL to turn on the transistor 505. At this time, if the threshold voltage of the memory cell 503 is higher than the first read voltage VR1 applied to the selected word line Sel_WL (B, C, and D states), the bit line BLe is at a high level (1V). If the threshold voltage of the memory cell 503 is lower than the first read voltage VR2 (state A), the voltage of the bit line BLe drops to the low level (0V). Subsequently, the PBSENSE signal is activated to transfer the voltage of the bit line BLe to the SO node. The SO node voltage is applied to the gate voltage of the TS transistor connected to the ground terminal, and at the same time, the MSET signal is activated 'high'. When the memory cell 503 is in one of the B, C, or D states, the TS transistor is turned on to generate a first latch voltage having a 'low' level at the QM node. When the memory cell 503 is in the A state, the TS transistor is turned on. The first latch voltage of the 'high' level is generated at the QM node because it is not turned on.

In the intermediate step S405, the first latch voltage is applied to the bit line BLe to make the bit line BLe a middle level between the high level 1V and the low level 0V. As a result of the first sensing operation S403, the voltage of the bit line BLe and the first latch voltage of the QM node always have opposite logic levels. Therefore, the BSLe, PBSENSE, and TRANM signals are activated 'high' to form a current path between the bitline (BLe) and the QM node. The voltage on the bitline (BLe) is raised to the middle level between 'high' and 'low'. I can make it. That is, in the related art, the bit line BLe is completely discharged to the low level (0 V) by activating the DISCHe signal 'high' after the first sensing, but in the present invention, the first latch voltage of the QM node is changed to the bit line BLe. ) To reduce the current and time consumed in precharging the bit line BLe back to a high level in the second precharge step S407. do.

In the second precharge step S407, the PRECHb signal is 'low' again, the voltage of the SO node is increased, and the PBSENSE signal and the BSLe signal are 'high', and the bit line BLe is precharged to a high level. At the same time, a bias voltage of 4.5V is applied to the DSL to turn on the transistor 501, the second read voltage VR3 is applied to the selected word line Sel_WL, and the pass voltage VP is applied to the unselected word line Unsel_WL. Is applied.

In the second sensing operation S409, a bias voltage of 4.5V is applied to SSL so that the transistor 205 is turned on. If the threshold voltage of the memory cell 503 is higher than the second read voltage VR3 applied to the selected word line Sel_WL (D state), the bit line BLe is maintained at the high level 1V and the memory cell 503 Is lower than the second read voltage VR3 (states A, B, and C), the voltage of the bit line BLe drops to the low level (0V). Subsequently, the PBSENSE signal is activated to transfer the voltage of the bit line BLe to the SO node, and the SO node voltage is applied to the gate voltage of the TS transistor connected to the ground terminal, and at the same time, the MRST signal is activated 'high'. At this time, the second latch voltage is generated. When the memory cell 503 is in one of the A, B, and C states, the TS transistor is not turned on, so the QM node maintains the first latch voltage even when the MRST signal is activated. That is, in the A state, the second latch voltage is maintained at the 'high' level, and in the B and C states, the second latch voltage is maintained at the 'low' level. On the other hand, when the memory cell 503 is in the D state, the TS transistor is turned on and the MRST signal is activated so that the QMb node voltage drops to the 'low' level, thereby generating a second latch voltage of the 'high' level at the QM node. .

In the data reading step S411, the data LSB value is read using the second latch voltage. At this time, the second latch voltage latched to the QM node is transferred to the QC node, and output to the external system through the QC node to read data. The LSB value is read as "1" when the second latch voltage is "high" (A, D state) and the LSB value is read as "0" when the second latch voltage is "low" (B, C state). do.

If the LSB read operation and the MSB read operation are continuously performed, the bit line BLe may be brought back to an intermediate level after the second sensing operation S409, and precharge, sensing, and data reading may be performed once more. .

FIG. 6 is a timing diagram for describing an intermediate step S405 and a second precharge step S407 of FIG. 4. Assume that memory cell 503 is programmed to the B state of FIG. 1A. The dotted line portion shows a timing diagram in the prior art.

As shown in FIG. 6, since the BSLe, PBSENSE, and TRANM signals remain 'high' and the DISCHe signal remains 'low' in an intermediate step S405, the voltage of the bit line BLe is low at a high level (1V). The level (0V) is not completely discharged, but falls only to the intermediate level. Since the voltage of the bit line BLe and the first latch voltage generated at the QM node after the first sensing operation always have opposite logic levels, a current path is formed between the bit line BLe and the QM node. BLe) can be made medium.

Subsequently, in the second precharge step S407, the voltage of the SO node is increased by the PRECHb signal, the PBSENSE signal and the BSLe signal are 'high', and the bit line BLe is precharged to a high level. As shown in the drawing, the bit line BLe does not drop to a low level and then rises to a high level, but instead goes directly to a high level from an intermediate level, thereby reducing the current and time required for precharging.

As described above, in the present invention, when performing continuous sensing operations with different read voltages to read data written in one multi-level cell, the bit lines are not discharged to the low level after the first sensing operation. The present invention proposes a read operation method of a flash memory device that reduces current and time consumed during a read operation by making the intermediate level between a high level and a low level, and then precharging it again to a high level to perform a second sensing operation. It was.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited by.

Claims (7)

A first precharge step of precharging the bit line to a high level;
A first sensing step of sensing a voltage change of the bit line by applying a first read voltage to a selected word line;
An intermediate step of making the bit line an intermediate level between a high level and a low level;
A second precharge step of precharging the bit line to a high level; And
A second sensing step of sensing a voltage change of the bit line by applying a second read voltage to the selected word line
Read operation method of a flash memory device comprising a.
The method of claim 1,
Generating a first latch voltage in response to the first sensing result;
Generating a second latch voltage in response to the first latch voltage and the second sensing result; And
Reading data corresponding to the second latch voltage
Read operation method of the flash memory device further comprising.

The method of claim 2,
The first latch voltage is
Has a logic level opposite to the voltage of the bit line corresponding to the first sensing result.
Read operation method of flash memory device.
The method of claim 2,
In the intermediate stage
Applying the first latch voltage to the bit line to bring the bit line to an intermediate level.
Read operation method of flash memory device.
A memory cell array including a plurality of memory cells; And
After the bit line is precharged to a high level to read data written to a selected memory cell among the plurality of memory cells, the first sensing operation is performed, and the bit line is made into an intermediate level between a high level and a low level. The control circuit precharges the bit line to a high level again to perform a second sensing operation.
Flash memory device comprising a.
6. The method of claim 5,
The plurality of memory cells
Is a multi-bit cell that requires two or more sensing operations to read stored data
Flash memory device.
6. The method of claim 5,
The control circuit
Applying a first latch voltage generated as a result of the first sensing to the bit line to bring the bit line to an intermediate level after the first sensing operation.
Flash memory device.
KR1020100103891A 2010-10-25 2010-10-25 Flash memory device and operating method thereof KR20120042274A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10566067B2 (en) 2018-03-29 2020-02-18 SK Hynix Inc. Semiconductor memory device, storage device having the same, and method of operating memory controller
US10573386B2 (en) 2017-07-28 2020-02-25 Samsung Electronics Co., Ltd. Memory device including NAND strings and method of operating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10573386B2 (en) 2017-07-28 2020-02-25 Samsung Electronics Co., Ltd. Memory device including NAND strings and method of operating the same
US10566067B2 (en) 2018-03-29 2020-02-18 SK Hynix Inc. Semiconductor memory device, storage device having the same, and method of operating memory controller

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