KR20230173347A - Thin film transistor substrate and flexible display apparatus comprising the same - Google Patents

Abstract

One embodiment of the present invention includes a first light blocking layer, a first flexible substrate on the first light blocking layer, a first thin film transistor and a second thin film transistor on the first flexible substrate, and the first light blocking layer. The layer overlaps the first active layer of the first thin film transistor, and the first flexible substrate provides a thin film transistor substrate disposed between the first light blocking layer and the first thin film transistor, and a flexible display device including the same. do.

Description

Thin film transistor substrate and flexible display device including the same {THIN FILM TRANSISTOR SUBSTRATE AND FLEXIBLE DISPLAY APPARATUS COMPRISING THE SAME}

One embodiment of the present invention relates to a thin film transistor substrate and a flexible display device including the same. More specifically, an embodiment of the present invention relates to a thin film transistor substrate including a flexible substrate and a flexible display device including the same.

The importance of display devices is increasing with the development of multimedia, and recently, flat panel displays such as liquid crystal displays, plasma displays, and organic light emitting displays have been commercialized.

Recently, flexible display devices that can exhibit display performance even when bent like paper have been developed by using flexible substrates such as plastic instead of existing inflexible glass substrates.

To drive a display device, a thin film transistor is currently used. Since thin film transistors can be manufactured on glass or plastic substrates, they are widely used as switching elements in display devices.

Based on the material that makes up the active layer, the thin film transistor is an amorphous silicon thin film transistor in which amorphous silicon is used as the active layer, a polycrystalline silicon thin film transistor in which polycrystalline silicon is used as the active layer, and an oxide semiconductor in which an oxide semiconductor is used as the active layer. It can be classified into an oxide semiconductor thin film transistor. Among these, oxide semiconductor TFTs, which have high mobility and a large change in resistance depending on the oxygen content, have the advantage of being able to easily obtain desired physical properties. In addition, the manufacturing cost is low because the oxide constituting the active layer can be formed at a relatively low temperature during the manufacturing process of the oxide semiconductor thin film transistor. Due to the nature of oxide, oxide semiconductors are transparent, so they are advantageous for implementing transparent displays.

Research is being conducted to apply oxide semiconductor thin film transistors (Oxide semiconductor TFTs) with these characteristics to flexible display devices.

One embodiment of the present invention can prevent degradation that may occur during the manufacturing process and prevent or reduce unnecessary parasitic capacitance or fringe capacitance. , to provide thin film transistor substrates and flexible display devices.

Another embodiment of the present invention is to prevent the active layer from being degraded by light or heat during a lift-off process using a laser by disposing a light blocking layer on the lower part of the flexible substrate. , to provide thin film transistor substrates and flexible display devices.

Another embodiment of the present invention is a thin film transistor substrate and flexible device that can prevent, suppress, or reduce parasitic capacitance or fringe capacitance by adjusting the distance between the light blocking layer and the active layer. We would like to provide a display device.

Another embodiment of the present invention applies a flexible substrate with a double structure, arranges a light blocking layer between the flexible substrates, prevents cracks or bubbles from occurring, and performs lift-off using a laser. The object of the present invention is to provide a thin film transistor substrate and a flexible display device that can prevent the active layer from being degraded by light or heat during the -Off) process.

One embodiment of the present invention for achieving the above-described technical problem includes a first light blocking layer, a first flexible substrate on the first light blocking layer, a first thin film transistor and a second thin film transistor on the first flexible substrate. A thin film transistor substrate including a thin film transistor is provided. The first thin film transistor includes a first active layer on the first flexible substrate and a first gate electrode spaced apart from the first active layer, and the second thin film transistor includes a second active layer on the first flexible substrate and a first gate electrode spaced apart from the first active layer. It includes a second gate electrode spaced apart from the second active layer. The first light blocking layer overlaps the first active layer, and the first flexible substrate is disposed between the first light blocking layer and the first thin film transistor.

The thin film transistor substrate may further include a second light blocking layer disposed between the first flexible substrate and the second active layer and overlapping the second active layer.

The first light blocking layer may not overlap the second light blocking layer.

The first light blocking layer may overlap the second light blocking layer.

The thin film transistor substrate further includes a lower protective layer, and the first flexible substrate may be disposed between the first thin film transistor and the lower protective layer.

The first light blocking layer may be disposed within the lower protective layer.

The lower protective layer includes a first protective layer and a second protective layer on the first protective layer, wherein the first protective layer and the second protective layer each have electrical insulation, and the first light blocking layer It may be disposed between the first protective layer and the second protective layer.

The thin film transistor substrate further includes a second flexible substrate, and the lower protective layer may be disposed between the first flexible substrate and the second flexible substrate.

The first light blocking layer may be disposed between the first flexible substrate and the second flexible substrate, and may not contact the first flexible substrate or the second flexible substrate.

The first light blocking layer may contact the second flexible substrate and the lower protective layer.

The first light blocking layer may contact the lower protective layer and the first flexible substrate.

The first light blocking layer may be in contact with the second flexible substrate and may not be in contact with the lower protective layer.

At least one of the first active layer and the second active layer may include a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer.

The distance between the first active layer and the first light blocking layer along the thickness direction may be in the range of 2.5 to 10.5 ㎛.

The second thin film transistor includes a second source electrode and a second drain electrode that are spaced apart from each other and are respectively connected to the second active layer, and one of the second source electrode and the second drain electrode is used to block the second light. It can be connected to a layer.

Another embodiment of the present invention provides a display device including the thin film transistor substrate and a display element.

The display device may include a first electrode, an organic light-emitting layer on the first electrode, and a second electrode on the organic light-emitting layer.

The second electrode may be connected to the first light blocking layer.

The display device may include a gate driver on the first flexible substrate, and the gate driver may include the first thin film transistor.

The first light blocking layer may overlap the gate driver.

The first light blocking layer may surround an edge of the first flexible substrate in a plan view.

The display device may include a pixel driving circuit on the first flexible substrate, and the pixel driving circuit may include the first thin film transistor and the second thin film transistor.

The second thin film transistor may be connected to the display element.

According to one embodiment of the present invention, by disposing a light blocking layer on the lower part of a thin film transistor substrate or a flexible substrate constituting a flexible display device, the active layer is activated by light or heat during a lift-off process using a laser. Degradation can be prevented.

According to another embodiment of the present invention, by adjusting the distance between the light blocking layer and the active layer, unnecessary parasitic capacitance or fringe capacitance can be prevented from occurring in a thin film transistor substrate or a flexible display device. You can.

According to another embodiment of the present invention, by applying a flexible substrate with a double structure and disposing a light blocking layer between the flexible substrates, cracks or bubbles are prevented, and lift-off (lift-off) using a laser is prevented. Degradation of the active layer due to light or heat during the lift-off process can be prevented.

1 is a cross-sectional view of a thin film transistor substrate according to an embodiment of the present invention.
Figure 2 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
Figure 3 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
Figure 4 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
Figure 5 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
Figure 6 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
Figure 7 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention.
Figure 8 is a partial cross-sectional view of a display device according to another embodiment of the present invention.
9A and 9B are manufacturing process diagrams for the display device of FIG. 8.
Figure 10 is a schematic diagram of a display device according to another embodiment of the present invention.
Figure 11 is a schematic diagram of a shift resist.
FIG. 12 is a circuit diagram of an embodiment of the stage provided in the shift resist of FIG. 11.
FIG. 13 is a circuit diagram of one pixel (P) of FIG. 10.
Figure 14 is a top view of the pixel of Figure 13.
Figure 15 is a cross-sectional view taken along line II' of Figure 14.
Figure 16 is a circuit diagram of one pixel of a display device according to another embodiment of the present invention.
Figure 17 is a circuit diagram of one pixel of a display device according to another embodiment of the present invention.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms, but the present embodiments only serve to ensure that the disclosure of the present invention is complete and are within the scope of common knowledge in the technical field to which the present invention pertains. It is provided to inform those who have the scope of the invention. The invention is defined only by the scope of the claims.

The shape, size, ratio, angle, number, etc. shown in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown in the drawings. Like components may be referred to by the same reference numerals throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technology may unnecessarily obscure the gist of the present invention, the detailed description is omitted.

When “comprises,” “has,” “consists of,” etc. mentioned in this specification are used, other parts may be added unless the expression “only” is used. If a component is expressed in the singular, the plural is included unless specifically stated.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

For example, when the positional relationship between two parts is described as "on top", "at the top", "at the bottom", "next to", etc., the expressions "immediately" or "directly" are used. Unless otherwise specified, one or more other parts may be located between the two parts.

Spatially relative terms such as “below, beneath,” “lower,” “above,” and “upper” refer to one element or component as shown in the drawing. It can be used to easily describe the correlation with other elements or components. Spatially relative terms should be understood as terms that include different directions of the element during use or operation in addition to the direction shown in the drawings. For example, if an element shown in the drawings is turned over, an element described as “below” or “beneath” another element may be placed “above” the other element. Accordingly, the illustrative term “down” may include both downward and upward directions. Likewise, the illustrative terms “up” or “on” can include both up and down directions.

In the case of a description of a temporal relationship, for example, if a temporal relationship is described as “after”, “followed by”, “after”, “before”, etc., “immediately” or “directly”. Unless the expression is used, non-continuous cases may also be included.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, “at least one of the first, second, and third items” means each of the first, second, or third items, as well as two of the first, second, and third items. It can mean a combination of all items that can be presented from more than one.

Each feature of the various embodiments of the present invention can be combined or combined with each other, partially or entirely, and various technical interconnections and operations are possible, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship. It may be possible.

In adding reference numerals to components in each drawing for explaining embodiments of the present invention, the same components may have the same reference numerals as much as possible even if they are shown in different drawings.

In embodiments of the present invention, the source electrode and the drain electrode are distinguished only for convenience of explanation, and the source electrode and the drain electrode can be interchanged. The source electrode may become a drain electrode, and the drain electrode may become a source electrode. Additionally, the source electrode in one embodiment may become a drain electrode in another embodiment, and the drain electrode in one embodiment may become a source electrode in another embodiment.

In some embodiments of the present invention, the source connection part and the source electrode are distinguished from the drain connection part and the drain electrode for convenience of explanation, but the embodiments of the present invention are not limited thereto. The source connection may be a source electrode, and the drain connection may be a drain electrode. Additionally, the source connection part may be a drain electrode, and the drain area may be a source electrode.

Figure 1 is a cross-sectional view of a thin film transistor substrate 100 according to an embodiment of the present invention.

The thin film transistor substrate 100 according to an embodiment of the present invention includes a first light blocking layer 180, a first flexible substrate 121 on the first light blocking layer 180, and a first flexible substrate 121 on the first light blocking layer 180. It includes a first thin film transistor (TR1) and a second thin film transistor (TR2).

The first light blocking layer 180 overlaps the first active layer 130 of the first thin film transistor TR1 and may have light blocking characteristics. The first light blocking layer 180 may block light incident toward the first flexible substrate 121 and protect the first active layer 130 of the first thin film transistor TR1.

Additionally, the first light blocking layer 180 may have electrical conductivity.

According to one embodiment of the present invention, the first light blocking layer 180 may include a metal having light blocking properties and electrical conductivity. For example, the first light blocking layer 180 is made of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, copper (Cu) or a copper alloy, and Contains at least one of copper-based metals, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), and iron (Fe) can do. The first light blocking layer 180 may have a multilayer structure including at least two conductive films with different physical properties.

The first light blocking layer 180 serves to protect the active layers 130 and 230 of the thin film transistors TR1 and TR2 in the manufacturing method of a flexible display device or thin film transistor substrate using the carrier substrate 190. can do. Specifically, in the process of manufacturing a flexible display device or thin film transistor using the carrier substrate 190, light, for example, a laser, may be used to remove the substrate carrier substrate 190 (FIG. 9A , see 9b). The laser may damage the active layers 130 and 230 of the thin film transistors TR1 and TR2. Accordingly, the first light blocking layer 180 may be used to protect the active layers 130 and 230 of the thin film transistors TR1 and TR2 from laser.

The first flexible substrate 121 is disposed on the first light blocking layer 180. The first flexible substrate 121 may be in contact with the first light blocking layer 180.

According to one embodiment of the present invention, plastic with flexible characteristics may be used as the first flexible substrate 121. The first flexible substrate 121 is, for example, polyethylene terephthalate (PET), polycarbonate (PC), polyethylene naphthalate (PEN), COC (Cyclic olefin copolymer), acrylic ( It may include at least one of Acryl), polyimide (PI), and polyamide-imide.

More specifically, heat-resistant polyimide (PI) that can withstand high temperatures may be used as the first flexible substrate 121.

The first thin film transistor TR1 and the second thin film transistor TR2 may be disposed on the first flexible substrate 121 .

The first thin film transistor TR1 includes a first active layer 130 on the first flexible substrate 121 and a first gate electrode 150 spaced apart from the first active layer 130. The second thin film transistor TR2 includes a second active layer 230 on the first flexible substrate 121 and a second gate electrode 250 spaced apart from the second active layer 230.

According to one embodiment of the present invention, the first flexible substrate 121 is disposed between the first light blocking layer 180 and the first thin film transistor TR1. Additionally, the first light blocking layer 180 overlaps at least the first active layer 130.

In the thin film transistor substrate 100 shown in FIG. 1, the first light blocking layer 180 does not overlap the second active layer 230. However, the embodiment of the present invention is not limited to this, and the first light blocking layer 180 may extend below the second thin film transistor TR2 and overlap the second active layer 230 (Figure 6).

Referring to FIG. 1, a first buffer layer 115 may be disposed on the first flexible substrate 121. The first buffer layer 115 may be made of an insulating material. For example, the first buffer layer 115 may include at least one of insulating materials such as silicon oxide, silicon nitride, and metal oxide. Aluminum oxide may be used as the metal oxide.

The first buffer layer 115 may have a single-layer structure or a multi-layer structure. The first buffer layer 115 can protect the active layers 130 and 230 by blocking air and moisture. Additionally, the surface of the upper part of the first flexible substrate 121 can be made uniform by the first buffer layer 115. The first buffer layer 115 may be omitted.

Referring to FIG. 1, a second light blocking layer 220 may be disposed on the first buffer layer 115. The second light blocking layer 220 is disposed between the first flexible substrate 121 and the second active layer 230, and may overlap the second active layer 230.

The second light blocking layer 220 may have light blocking properties. The second light blocking layer 220 may block light incident from the first flexible substrate 121 and protect the second active layer 230 of the second thin film transistor TR2. Additionally, the second light blocking layer 220 may have electrical conductivity.

According to one embodiment of the present invention, the second light blocking layer 220 may include a metal having light blocking properties and electrical conductivity. The second light blocking layer 220 may be made of the same material as the first light blocking layer 180, or may be made of a different material.

In the thin film transistor substrate 100 shown in FIG. 1, the first light blocking layer 180 does not overlap the second light blocking layer 220.

However, the embodiment of the present invention is not limited to this, and the first light blocking layer 180 may overlap the second light blocking layer 220 (see FIG. 6). For example, when the first light blocking layer 180 extends below the second thin film transistor TR2, the first light blocking layer 180 may overlap the second light blocking layer 220, It may also overlap with the second active layer 230 (see FIG. 6).

Referring to FIG. 1, a second buffer layer 141 is disposed on the second light blocking layer 220.

The second buffer layer 141 may protect the active layers 130 and 230 by blocking air and moisture. Additionally, the surface of the upper part of the second light blocking layer 220 can be made uniform by the second buffer layer 141.

The second buffer layer 141, like the first buffer layer 115, may be made of an insulating material. For example, the first buffer layer 115 may include at least one of metal oxides such as silicon oxide, silicon nitride, and aluminum oxide. The second buffer layer 141 may have a single-layer structure or a multi-layer structure.

Referring to FIG. 1, a first thin film transistor TR1 and a second thin film transistor TR2 may be disposed on the second buffer layer 141.

The first thin film transistor TR1 may include a first active layer 130, a first gate electrode 150, a first source electrode 161, and a first drain electrode 162. The first source electrode 161 and the first drain electrode 162 may be spaced apart from each other and connected to the first active layer 130.

The second thin film transistor TR2 may include a second active layer 230, a second gate electrode 250, a second source electrode 261, and a second drain electrode 262. The second source electrode 261 and the second drain electrode 262 may be spaced apart from each other and connected to the second active layer 230.

The first active layer 130 and the second active layer 230 may be disposed on the second buffer layer 141.

According to one embodiment of the present invention, at least one of the first active layer 130 and the second active layer 230 may include a semiconductor material. The first active layer 130 and the second active layer 230 may have the same composition or may have different compositions. Both the first active layer 130 and the second active layer 230 may include an oxide semiconductor material.

Oxide semiconductor materials include, for example, IZO (InZnO)-based oxide semiconductor materials, IGO (InGaO)-based oxide semiconductor materials, ITO (InSnO)-based oxide semiconductor materials, IGZO (InGaZnO)-based oxide semiconductor materials, and IGZTO (InGaZnSnO)-based oxide semiconductor materials. It may include at least one of an oxide semiconductor material, a GaZnO (GZTO)-based oxide semiconductor material, a GaZnO (GZO)-based oxide semiconductor material, an InSnZnO (ITZO)-based oxide semiconductor material, and a FeInZnO (FIZO)-based oxide semiconductor material. However, the embodiment of the present invention is not limited to this, and the first active layer 130 and the second active layer 230 may be made of other oxide semiconductor materials known in the art.

Although the first active layer 130 and the second active layer 230 are shown as one layer in FIG. 1, the embodiment of the present invention is not limited thereto. According to one embodiment of the present invention, at least one of the first active layer 130 and the second active layer 230 may have a multilayer structure.

According to one embodiment of the present invention, at least one of the first active layer 130 and the second active layer 230 may include a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer. there is.

The first active layer 130 may include a channel portion 130n, a first conductive portion 131, and a second conductive portion 132. The channel portion 130n overlaps the first gate electrode 150. The first conductive portion 131 and the second conductive portion 132 of the first active layer 130 do not overlap the first gate electrode 150. The first conductive portion 131 and the second conductive portion 132 may be formed by selectively converting a semiconductor material into a conductor.

According to one embodiment of the present invention, the first conductive portion 131 of the first active layer 130 may be a source region, and the second conductive portion 132 may be a drain region. According to an embodiment of the present invention, the first conductive portion 131 may be referred to as a source electrode, and the second conductive portion 132 may be referred to as a drain electrode.

The second active layer 230 may include a channel portion 230n, a first conductive portion 231, and a second conductive portion 232. The channel portion 230n overlaps the second gate electrode 250. The first conductive portion 231 and the second conductive portion 232 of the second active layer 230 do not overlap the second gate electrode 250. The first conductive portion 231 and the second conductive portion 232 may be formed by selectively converting a semiconductor material into a conductor.

According to one embodiment of the present invention, the first conductive portion 231 of the second active layer 230 may be a source region, and the second conductive portion 232 may be a drain region. According to an embodiment of the present invention, the first conductive portion 231 may be referred to as a source electrode, and the second conductive portion 232 may be referred to as a drain electrode.

A gate insulating layer 142 is disposed on the first active layer 130 and the second active layer 230. The gate insulating layer 142 may include at least one of silicon oxide, silicon nitride, and metal-based oxide. The gate insulating layer 142 may each have a single-layer structure or a multi-layer structure.

Referring to FIG. 1 , the first gate electrode 150 and the second gate electrode 250 may be disposed on the gate insulating film 142 . The first gate electrode 150 may at least partially overlap the first active layer 130, and the second gate electrode 250 may at least partially overlap the second active layer 230.

The first gate electrode 150 and the second gate electrode 250 are made of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper (Cu) or copper. It may include at least one of copper-based metals such as alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). . The first gate electrode 150 and the second gate electrode 250 may each have a multilayer structure including at least two conductive films with different physical properties.

An interlayer insulating film 143 may be disposed on the first gate electrode 150 and the second gate electrode 250. The interlayer insulating film 143 is an insulating layer made of an insulating material. The interlayer insulating film 143 may be made of an organic material, an inorganic material, or a laminate of an organic material layer and an inorganic material layer. The interlayer insulating film 143 may include silicon oxide, silicon nitride, metal oxide, etc.

Source electrodes 161 and 261 and drain electrodes 162 and 262 may be disposed on the interlayer insulating film 143. The source electrodes 161 and 261 and the drain electrodes 162 and 262 are respectively made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium ( It may include at least one of Nd), copper (Cu), and alloys thereof. The source electrodes 161 and 261 and the drain electrodes 162 and 262 may each be made of a single layer of metal or a metal alloy, or may be made of a multilayer of two or more layers.

The source electrodes 161 and 261 and the drain electrodes 162 and 262 may be connected to the first active layer 130 and the second active layer 230, respectively, through contact holes.

Specifically, the first source electrode 161 and the first drain electrode 162 of the first thin film transistor TR1 may be spaced apart from each other and connected to the first active layer 130, respectively.

The second source electrode 261 and the second drain electrode 262 of the second thin film transistor TR2 may be spaced apart from each other and connected to the second active layer 230, respectively. Additionally, the second source electrode 261 of the second thin film transistor TR2 may be connected to the second light blocking layer 220 through a contact hole. However, the embodiment of the present invention is not limited to this, and the second drain electrode 262 of the second thin film transistor TR2 may be connected to the second light blocking layer 220.

In one embodiment of the present invention and the drawings, the source electrodes 161 and 261 and the drain electrodes 162 and 262 are distinguished for convenience of explanation, and the source electrodes 161 and 261 and the drain electrodes 162 and 262 ) is not limited by the drawings and the above descriptions. The source electrodes 161 and 261 and the drain electrodes 162 and 262 may be interchanged.

In the flexible display device using the carrier substrate 190 as shown in FIG. 9A, the first light blocking layer 180 is used to protect the active layers 130 and 230 from the laser used when removing the carrier substrate 190. When placed on the first flexible substrate 121, a large parasitic capacitance or fringe capacitance may be generated between the active layers 130 and 230 and the first light blocking layer 180. You can. Specifically, when disposed between the first flexible substrate 121 and the active layers 130 and 230, when the first light blocking layer 180 is disposed, the first light blocking layer 180 and the first flexible substrate Since the distance between (121) is close, a relatively large parasitic cap or fringe cap can be generated.

For example, when the first light blocking layer 180 is disposed on top of the first flexible substrate 121, the distance between the first active layer 130 and the first light blocking layer 180 is 300 nm to 500 nm. It is about 300 nm to 600 nm. In this case, a parasitic capacitance of about several to tens of fF (1 fF = 10 ^-15 F) may be generated between the first active layer 130 and the first light blocking layer 180. For reference, considering that the capacity of the storage capacitor (Cst) of the organic light emitting display device is about 100 to 200 fF, several to tens of fF can be said to be a very large parasitic capacitance.

On the other hand, according to one embodiment of the present invention, the first light blocking layer 180 is disposed below the first flexible substrate 121. As the first light blocking layer 180 is disposed below the first flexible substrate 121, the distance between the first active layer 130 of the first thin film transistor TR1 and the first light blocking layer 180 is It goes away. As a result, parasitic capacitance or fringe capacitance generated between the first active layer 130 and the first light blocking layer 180 can be reduced or suppressed.

For example, according to an embodiment of the present invention, when the first light blocking layer 180 is disposed below the first flexible substrate 121, the first active layer 130 and the first light blocking layer ( 180), the parasitic capacitance that occurs can be reduced to tens to hundreds of aF (1 aF = 10 ^-18 F).

According to one embodiment of the present invention, the thickness of the first flexible substrate 121 may range from 2 to 10 ㎛. More specifically, the thickness of the first flexible substrate 121 may be in the range of 4 to 8 ㎛, 5 to 7 ㎛, or about 6 ㎛. Accordingly, according to an embodiment of the present invention, in the thickness direction, the distance between the first active layer 130 and the first light blocking layer 180 may be 2.5 ㎛ or more, 4.5 ㎛ or more, or 5 ㎛ or more. You can.

According to one embodiment of the present invention, in order to suppress parasitic capacitance between the first active layer 130 and the first light blocking layer 180, the first active layer 130 and the first light blocking layer 180 are formed along the thickness direction. The distance between the first light blocking layers 180 may range from 2.5 to 10.5 ㎛. More specifically, the distance between the first active layer 130 and the first light blocking layer 180 may range from 4.5 to 8.5 ㎛, and may range from 5 to 7 ㎛.

Figure 2 is a cross-sectional view of a thin film transistor substrate 200 according to another embodiment of the present invention. Hereinafter, to avoid duplication, descriptions of already described components are omitted.

Compared to the thin film transistor substrate 100 shown in FIG. 1, the thin film transistor substrate 200 shown in FIG. 2 further includes a lower protective layer 110. Referring to FIG. 2, the lower protective layer 110 is disposed below the first flexible substrate 121. According to one embodiment of the present invention, the first flexible substrate 121 may be disposed between the first thin film transistor TR1 and the lower protective layer 110.

The lower protective layer 110 may be made of an insulating material. For example, the lower protective layer 110 may include at least one insulating material selected from metal oxides such as silicon oxide, silicon nitride, and aluminum oxide.

According to another embodiment of the present invention, the first light blocking layer 180 may be disposed within the lower protective layer 110.

More specifically, the lower protective layer 110 may include a first protective layer 111 and a second protective layer 112 on the first protective layer 111. The first protective layer 111 and the second protective layer 112 may each have electrical insulation properties. Referring to FIG. 2, the first light blocking layer 180 may be disposed between the first protective layer 111 and the second protective layer 112.

However, another embodiment of the present invention is not limited to this. According to another embodiment of the present invention, the first light blocking layer 180 may be disposed between the second protective layer 112 and the first flexible substrate 121. The structure in which the first light blocking layer 180 is disposed between the second protective layer 112 and the first flexible substrate 121 is such that the first light blocking layer 180 is disposed between the lower protective layer 110 and the first flexible substrate 121. It can also be said to be a structure placed between (121). Refer to FIG. 5 for the structure in which the first light blocking layer 180 is disposed between the lower protective layer 110 and the first flexible substrate 121.

Additionally, according to another embodiment of the present invention, the first light blocking layer 180 may be disposed below the first protective layer 111. More specifically, the first protective layer 111 is disposed on the first light blocking layer 180, the second protective layer 112 is disposed on the first protective layer 111, and the second protective layer ( The first flexible substrate 121 may be disposed on 112). The structure in which the first light blocking layer 180 is disposed below the first protective layer 111 may be said to be a structure in which the first light blocking layer 180 is disposed below the lower protective layer 110. Refer to FIG. 4 for the structure in which the first light blocking layer 180 is disposed below the lower protective layer 110.

Referring to FIG. 2, a sufficient distance can be secured between the first active layer 130 and the first light blocking layer 180 of the first thin film transistor TR1. As a result, parasitic capacitance or fringe capacitance generated between the first active layer 130 and the first light blocking layer 180 can be efficiently reduced or suppressed.

Figure 3 is a cross-sectional view of a thin film transistor substrate 300 according to another embodiment of the present invention.

Compared to the thin film transistor substrate 200 shown in FIG. 2, the thin film transistor substrate 300 shown in FIG. 3 further includes a second flexible substrate 122. The second flexible substrate 122 may be disposed below the lower protective layer 110 . Plastic with flexible characteristics may be used as the second flexible substrate 122. The second flexible substrate 122 may be made of the same material as the first flexible substrate 121 or may be made of a different material.

According to another embodiment of the present invention, the thickness of the second flexible substrate 1221 may be in the range of 6 to 15 ㎛. More specifically, the thickness of the second flexible substrate 122 may be in the range of 8 to 12 ㎛ or approximately 10 ㎛. Accordingly, according to another embodiment of the present invention, the first thin film transistor TR1 and the second thin film transistor TR2 can be stably supported by the second flexible substrate 1221 having the above thickness.

Referring to FIG. 3 , the lower protective layer 110 may be disposed between the first flexible substrate 121 and the second flexible substrate 122. Additionally, the first light blocking layer 180 may be disposed within the lower protective layer 110. As a result, the first light blocking layer 180 may be disposed between the first flexible substrate 121 and the second flexible substrate 122.

Referring to FIG. 3, the first light blocking layer 180 is disposed between the first flexible substrate 121 and the second flexible substrate 122, and does not contact the first flexible substrate 121, and It may not even contact the substrate 122.

As shown in FIG. 3, the thin film transistor substrate 300 according to another embodiment of the present invention is a multi-layer flexible substrate including a first flexible substrate 121 and a second flexible substrate 122 ( 121, 122). Figure 3 shows flexible substrates 121 and 122 having a double layer structure.

As shown in FIG. 3, when the flexible substrates 121 and 122 have a multi-layer structure, the first thin film transistor TR1 and the second thin film transistor TR2 can be efficiently protected.

For example, if a crack occurs in the second flexible substrate 122 during the manufacturing process, the crack is filled by the lower protective layer 110, and the upper part of the crack is again covered by the first flexible substrate 121. can be reinforced. In addition, even if moisture (H ₂ O) or oxygen (O 2 ) penetrates through the second flexible substrate 122 in contact with the atmosphere (air), moisture (H 2 O) or oxygen (O ₂ ) penetrates through the second flexible substrate ₁₂₂ in contact with the atmosphere (air). (O ₂ ) is blocked, and moisture (H ₂ O) or oxygen (O ₂ ) is again blocked by the first flexible substrate 121.

In particular, when the lower protective layer 110 made of an inorganic material is disposed between the first flexible substrate 121 and the second flexible substrate 122 made of an organic material, it can effectively block moisture and oxygen like a thin film encapsulation layer. , cracks can be prevented and even if cracks occur, they can be easily filled.

According to another embodiment of the present invention, a laminate consisting of the first flexible substrate 121, the lower protective layer 110, and the second flexible substrate 122 serves as a substrate and has excellent flexible characteristics at the same time. , the first thin film transistor (TR1) and the second thin film transistor (TR2) can be efficiently protected.

Figure 4 is a cross-sectional view of a thin film transistor substrate 400 according to another embodiment of the present invention.

Referring to FIG. 4 , the first light blocking layer 180 may be disposed at the interface between the lower protective layer 110 and the second flexible substrate 122. Specifically, the first light blocking layer 180 is disposed between the second flexible substrate 122 and the lower protective layer 110, and can contact both the second flexible substrate 122 and the lower protective layer 110. there is.

Figure 5 is a cross-sectional view of a thin film transistor substrate 500 according to another embodiment of the present invention.

Referring to FIG. 5 , the first light blocking layer 180 may be disposed at the interface between the lower protective layer 110 and the first flexible substrate 121. Specifically, the first light blocking layer 180 is disposed between the first flexible substrate 121 and the lower protective layer 110, and can contact both the first flexible substrate 121 and the lower protective layer 110. there is.

Figure 6 is a cross-sectional view of a thin film transistor substrate 600 according to another embodiment of the present invention.

Referring to FIG. 6 , the first light blocking layer 180 may be disposed to extend below the second thin film transistor TR2. As a result, the first light blocking layer 180 may overlap the second thin film transistor TR2 and the second active layer 230.

Additionally, the first light blocking layer 180 may overlap the second light blocking layer 220. In this case, the second light blocking layer 220 may be omitted.

Figure 7 is a cross-sectional view of a thin film transistor substrate 700 according to another embodiment of the present invention.

Referring to FIG. 7 , the first light blocking layer 180 may be disposed below the second flexible substrate 122 . More specifically, the first light blocking layer 180 may contact the second flexible substrate 122 and not contact the lower protective layer 110.

Hereinafter, a display device to which the above-described thin film transistor substrates 100, 200, 300, 400, 500, 600, and 700 are applied will be described in detail.

Figure 8 is a partial cross-sectional view of a display device 800 according to another embodiment of the present invention.

The display device 800 according to another embodiment of the present invention may include the thin film transistor substrates 100, 200, 300, 400, 500, 600, and 700 and the display element 710 described above. Although FIG. 8 exemplarily shows a case in which the thin film transistor substrate 300 according to FIG. 3 is used, another embodiment of the present invention is not limited thereto. Any one of the thin film transistor substrates 100, 200, 400, 500, 600, and 700 shown in FIGS. 1, 2, 4, 5, 6, and 7 is a display device 800 according to another embodiment of the present invention. It can also be used as a thin film transistor substrate.

Referring to FIG. 8 , the display device 710 may include a first electrode 711, an organic emission layer 712 on the first electrode 711, and a second electrode 713 on the organic emission layer 713. The display device 800 of FIG. 8 is an organic light emitting display device that includes an organic light emitting diode (OLED) as a display element 710.

Referring to FIG. 8, the first thin film transistor (TR1) and the second thin film transistor (TR2) planarization layer 175 are disposed, and the first electrode 711 of the display element 710 is on the planarization layer 175. can be placed. Here, the planarization layer 175 planarizes the upper portions of the first thin film transistor TR1 and the second thin film transistor TR2 and protects the first thin film transistor TR1 and the second thin film transistor TR2.

A bank layer 750 is disposed at the edge of the first electrode 711. The bank layer 750 defines the light-emitting area of the display element 710. The organic light-emitting layer 712 is disposed on the first electrode 711, and the second electrode 713 is disposed on the organic light-emitting layer 712, so that the display element 710 is formed as an organic light-emitting diode (OLED).

The display device 800 of FIG. 8 may have flexible characteristics by having a first flexible substrate 121 and a second flexible substrate 122. This display device 800 may be referred to as a flexible display device.

In the display device 800 of FIG. 8, the first thin film transistor TR1 may be a transistor included in a driver for driving the display device 800. For example, the first thin film transistor TR1 may be a gate driver or data driver transistor. Additionally, the first thin film transistor TR1 of FIG. 8 may function as a switching transistor of the display panel.

The second thin film transistor TR2 shown in FIG. 8 is connected to the display element 710 and serves as a driving transistor that drives the display element 710.

Referring to FIG. 8, the second electrode 713 may be connected to the first light blocking layer 180. Specifically, the pad electrode 165 connected to the first light blocking layer 180 through the first contact hole CN1 is formed on the interlayer insulating film 143, and the second electrode 713 is formed through the second contact hole ( It can be connected to the pad electrode 165 through CN2). As a result, the second electrode 713 may be electrically connected to the first light blocking layer 180.

The first light blocking layer 180 connected to the second electrode 713 may serve to supply a common voltage to the second electrode 713. In this way, the first light blocking layer 180 may be patterned on the first flexible substrate 121 to serve as an ELVDD wiring that supplies a common voltage to the second electrode 713.

FIGS. 9A and 9B are manufacturing process diagrams for the display device 800 of FIG. 8.

Referring to FIG. 9A, a sacrificial layer 195 may be formed on the carrier substrate 190. Next, the thin film transistor substrate 300 shown in FIG. 3 may be formed on the sacrificial layer 195. Next, the display element 710 may be formed on the thin film transistor substrate 300.

As a result, as shown in FIG. 9A, the display device 800 shown in FIG. 8 may be formed on the sacrificial layer 195.

Next, as shown in FIG. 9A, light L may be irradiated in the direction of the arrow toward the carrier substrate 190. A laser may be applied as light (L).

Referring to FIG. 9B, the sacrificial layer 195 is removed by irradiation with light (L), and the carrier substrate 190 can be separated from the second flexible substrate 122. As a result, a display device 800 with flexible characteristics can be produced.

Figure 10 is a schematic diagram of a display device 900 according to another embodiment of the present invention.

As shown in FIG. 10, the display device 900 according to another embodiment of the present invention may include a display panel 310, a gate driver 320, a data driver 330, and a control unit 340. You can.

The display panel 310 includes gate lines GL and data lines DL, and pixels P are disposed in intersection areas of the gate lines GL and data lines DL. An image is displayed by driving the pixel (P). Gate lines GL, data lines DL, and pixels P may be disposed on the first flexible substrate 121 .

The control unit 340 controls the gate driver 320 and data driver 330.

The control unit 340 uses a signal supplied from an external system (not shown) to generate a gate control signal (GCS) for controlling the gate driver 320 and a data control signal (DCS) for controlling the data driver 330. outputs. Additionally, the control unit 340 samples input image data input from an external system, rearranges it, and supplies the rearranged digital image data (RGB) to the data driver 330.

The gate control signal (GCS) includes a gate start pulse (GSP), gate shift clock (GSC), gate output enable signal (GOE), start signal (Vst), and gate clock (GCLK). Additionally, the gate control signal (GCS) may include control signals for controlling the shift register.

The data control signal (DCS) includes a source start pulse (SSP), source shift clock signal (SSC), source output enable signal (SOE), and polarity control signal (POL).

The data driver 330 supplies data voltage to the data lines DL of the display panel 310. Specifically, the data driver 330 converts the image data (RGB) input from the control unit 340 into an analog data voltage and supplies the data voltage to the data lines DL.

According to one embodiment of the present invention, the gate driver 320 may be mounted on the display panel 310. In this way, the structure in which the gate driver 320 is directly mounted on the display panel 310 is called a gate in panel (GIP) structure. Specifically, in a gate in panel (GIP) structure, the gate driver 320 may be disposed on the first flexible substrate 121.

The display device 900 according to an embodiment of the present invention may include the thin film transistor substrates 100, 200, 300, 400, 500, 600, and 700 described above. According to one embodiment of the present invention, the gate driver 320 may include the first thin film transistor TR1 of the thin film transistor substrates 100, 200, 300, 400, 500, 600, and 700 described above. Additionally, the first light blocking layer 180 may overlap the gate driver 320.

Referring to FIG. 10 , the first light blocking layer 180 may have a shape that surrounds the edge of the first flexible substrate 121 in plan view. Specifically, the first light blocking layer 180 overlaps the gate driver 320 and may be patterned to surround the edge of the display panel 310 at the same time.

The gate driver 320 may include a shift register 350.

The shift register 350 sequentially supplies gate pulses to the gate lines GL for one frame using a start signal and gate clock transmitted from the control unit 340. Here, one frame refers to a period during which one image is output through the display panel 310. The gate pulse has a turn-on voltage that can turn on the switching element (thin film transistor) disposed in the pixel P.

Additionally, the shift register 350 supplies a gate-off signal capable of turning off the switching element to the gate line GL during the remaining period in one frame in which the gate pulse is not supplied. Hereinafter, the gate pulse and gate-off signal are collectively referred to as a scan signal (SS or Scan).

The shift register 350 may include the first thin film transistor TR1 of the thin film transistor substrates 100, 200, 300, 400, 500, 600, and 700 described above.

Figure 11 is a schematic diagram of the shift register 350. FIG. 12 is a circuit diagram of the stage 351 provided in the shift resist 350 of FIG. 11.

Referring to FIG. 11, the shift register 350 may include g stages 351 (ST1 to STg).

The shift register 350 transmits one scan signal SS to the pixels P connected to one gate line GL through one gate line GL. Each of the stages 351 may be connected to one gate line GL. When g gate lines GL are formed in the display panel 110, the shift register 350 may include g stages 351 (ST1 to STg), and g scan signals SS1 to SSg) can be produced.

In general, each stage 351 outputs the gate pulse GP once per frame, and the gate pulses GP are sequentially output from each stage 351.

FIG. 12 is a circuit diagram showing one stage 351 of the shift register 350 of the gate driver 320.

One stage 351 of the shift register shown in FIG. 12 includes output units OBc and OBs that supply an output voltage Vout in response to the logic state of the first node Q, and It includes a first node control unit (NC1) that controls charging and discharging.

The output units OBc and OBs include a pull-up transistor Tup that supplies the output voltage of the clock signal CLKa in response to control of the first node. The output voltage is supplied as a scan pulse to the corresponding gate line and simultaneously as a carry signal that controls charging and discharging of other stages.

The first node control unit (NC1) is configured to charge the first node (Q) with a high potential voltage (VDD) or a front-end output (PRE) in response to the front-end output (PRE) from the previous stage. and a second transistor (T2) of the reset unit that discharges the first node (Q) to a low potential voltage (VSS), which is a reset voltage, in response to the rear output (NXT) from the next stage. When the stage 351 in FIG. 12 is the first stage (ST), the start pulse (Vst) is supplied instead of the front end output (PRE).

When the stage 351 in FIG. 12 is the last stage, a reset pulse (Vrst) is supplied instead of the rear output (NXT).

In the first period, the first node Q is precharged by the first transistor T1 turned on in response to the front end output PRE or the start pulse Vst, and then turned off in the second period. It is floated in the charged state by the first and second transistors (T1, T2). At this time, the gate-on voltage (gate high voltage) of the clock signal CLKa is supplied to the drain electrode of the pull-up transistor Tup, and the capacitor between the gate electrode and the source electrode of the pull-up transistor Tup is supplied. 1 As the voltage at the node (Q) is amplified, the pull-up transistor (Tup) is stably turned on and outputs the gate-on voltage of the clock signal (CLKa) as the output voltage.

Subsequently, the pull-up transistor Tup, which maintains the turn-on state due to the floating of the first node Q in the third period, outputs the gate-off voltage (gate low voltage) of the clock signal CLKa as an output voltage. .

Then, in the fourth period, the first node (Q) is discharged by the second transistor (T2), which is turned on in response to the rear end output (NXT) or the reset pulse (Vrst), and the pull-up transistor (Tup) is turned on. By being turned off, the output voltage maintains the gate-off voltage.

Referring to FIG. 12, by providing a carry output unit (OBc) controlled by the first node (Q1), the output units (OBc, OBs) are divided into a scan output unit (OBs) and a carry output unit (OBc).

The scan output unit OBc includes a scan pull-up transistor Tup-S that outputs the clock pulse CLKa as a scan pulse SP in response to control of the first node Q. The carry output unit OBc includes a carry pull-up transistor Tup-C that outputs the clock pulse CLKa as a carry signal CR in response to control of the first node Q. The carry signal CR output from the carry output unit OBc is supplied to the previous stage output (PRE) and the subsequent stage output (NXT) to the previous stage. Accordingly, the output node of the carry signal (CR) and the output node of the scan signal (SP) are separated and the load of the carry signal (CR) is reduced, thereby controlling the charging and discharging of the front and rear stages. Delay is reduced.

Referring to FIG. 12, the carry output unit (OBc) is additionally provided with a carry pull-down transistor (Tdn-C) controlled by the second node (QB), and the scan output unit (OBs) is controlled by the second node. A second node is further provided with a scan pull-down transistor (Tdn-S) controlled by (QB) and includes an inverter (INV) connected between the first node (Q) and the second node (QB). A control unit (NC2) is additionally provided.

The scan pull-down transistor (Tdn-S) of the scan output unit (OBs) converts the first low potential voltage (VSS0) to the first gate-off voltage of the scan signal (SP) in response to the control of the second node (QB). supplied by

The carry pull-down transistor (Tdn-C) of the carry output unit (OBc) converts the second low potential voltage (VSS1) to the second gate-off voltage of the carry signal (CR) in response to the control of the second node (QB). supplied by The carry signal CR output from the carry output unit OBc is supplied to the previous stage output (PRE) and the subsequent stage output (NXT) to the previous stage. In the first node control unit NC1, the second transistor T2, which is a reset unit, discharges the first node Q to the third low potential voltage VSS2, which is a reset voltage, in response to the rear carry signal CRn.

The inverter (INV) of the second node control unit (NC2) responds to the control of the first node (Q) and generates a high potential voltage (VH) or a low potential voltage (VL) that is opposite to the voltage of the first node (Q). It is supplied to the second node (QB).

The high potential voltages (VDD, VH) may be the same or different from each other. The low potential voltages (VSS0, VSS1, VSS2, VL) may be the same or different from each other.

In addition, the first node control unit NC1 further includes a third transistor T3 of the noise cleaner controlled by the second node QB, and the second node control unit NC2 includes fourth to seventh transistors T4. ~T7) and further includes an eighth transistor (T8) controlled by the front-end output (PRE). A third low-potential voltage (VSS2), which is a second reset voltage, is applied to the third transistor (T3) of the noise cleaner, and a fourth low-potential voltage (VSS3), which is a first reset voltage, is applied to the second transistor (T2) of the reset unit. ) is approved.

The third transistor T3 of the noise cleaner added to the first node control unit NC1 discharges the first node Q to the third low potential voltage VSS2 in response to the control of the second node QB. Accordingly, when the first node (Q) is in low logic, the third transistor (T3) is connected to the first node (Q) by coupling the clock (CLKa) supplied to the pull-up transistors (Tup-C, Tup-S). Remove the noise induced by Q). The inverter (INV) of the second node control unit (NC2) includes fourth to seventh transistors (T4, T5, T6, T7), and operates the second node (QB) to be opposite to the voltage of the first node (Q). Supply high potential voltage (VH) or low potential voltage (VL) to. The eighth transistor T8 added to the second node control unit NC2 discharges the second node QB to the low potential voltage VL in response to the front end output PRE.

A first capacitor C1 is formed between the gate electrode and the source electrode of the scan pull-up transistor Tup-S of the scan output unit OBs to amplify the voltage of the gate electrode Q. A second capacitor C2 is formed between the gate electrode and the source electrode of the carry pull-up transistor Tup-C of the carry output unit OBc to amplify the voltage of the gate electrode Q.

When the first node (Q) is in a charging state by the first node control unit (NC1), the scan and carry pull-up transistors (Tup-S, Tup-C) transmit the clock signal (CLKa) to the scan signal (SP) ) and carry signals (CR), respectively.

When the second node (QB) is in a charging state by the second node control unit (NC2), the scan and carry pull-down transistors (Tdn-S, Tdn-C) are connected to the first and second low potential voltages (VSS0). , VSS1) are output as a scan signal (SP) and a carry signal (CR), respectively.

FIG. 13 is a circuit diagram of one pixel (P) of FIG. 10.

The circuit diagram of FIG. 13 is an equivalent circuit diagram of a pixel (P) of the display device 900 including an organic light emitting diode (OLED) as the display element 710.

Referring to FIG. 13, the pixel P includes a display element 710 and a pixel driving circuit (PDC) that drives the display element 710. Specifically, the display device 900 according to an embodiment of the present invention may include a pixel driving circuit (PDC) on the first flexible substrate 121.

The pixel driving circuit (PDC) of FIG. 13 includes a switching transistor and a driving transistor.

According to another embodiment of the present invention, the first thin film transistor TR1 of the thin film transistor substrates 100, 200, 300, 400, 500, 600, and 700 described above may be used as the switching transistor. However, the embodiment of the present invention is not limited to this, and the thin film transistor substrates 100, 200, 300, 400, 500, 600, and 700 described above are used as the switching transistors of the pixel driving circuit (PDC) shown in FIG. 13. The second thin film transistor TR2 may be used.

According to another embodiment of the present invention, the second transistor of the thin film transistor substrates 100, 200, 300, 400, 500, 600, and 700 described above is used as a driving transistor of the pixel driving circuit (PDC) shown in FIG. 13. A thin film transistor (TR2) may be used.

Hereinafter, for convenience of explanation, the pixel driving circuit (PDC) of FIG. 13 is a switching transistor and is a first thin film transistor (TR1) of the thin film transistor substrates (100, 200, 300, 400, 500, 600, 700) described above. The display device 900 will be described with a focus on an embodiment in which is applied and the second thin film transistor TR2 is applied as the driving transistor. The second thin film transistor TR2 is connected to the display element 710.

The first thin film transistor TR1, which is a switching transistor, is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS supplied through the gate line GL.

The data line DL provides the data voltage Vdata to the pixel driving circuit PDC, and the first thin film transistor TR1 controls the application of the data voltage Vdata.

The driving power line PL provides a driving voltage (Vdd) to the display element 710, and the second thin film transistor TR2, which is a driving transistor, controls the driving voltage (Vdd). The driving voltage (Vdd) is a pixel driving voltage for driving an organic light emitting diode (OLED), which is the display element 710.

When the second thin film transistor TR2 is turned on by the scan signal SS applied from the gate driver 320 through the gate line GL, the data voltage Vdata supplied through the data line DL is displayed. It is supplied to the gate electrode of the second thin film transistor TR2 connected to the device 710. The data voltage Vdata is charged in the storage capacitor Cst formed between the gate electrode and the source electrode of the second thin film transistor TR2.

The amount of current supplied to the organic light emitting diode (OLED), which is the display element 710, through the second thin film transistor TR2 is controlled according to the data voltage (Vdata), and accordingly, the light output from the display element 710 is controlled. Gradation can be controlled.

FIG. 14 is a plan view of the pixel P in FIG. 13, and FIG. 15 is a cross-sectional view taken along line II' of FIG. 14.

Referring to FIGS. 14 and 15 , the protective layer 110 may be disposed on the second flexible substrate 122, and the first light blocking layer 180 may be disposed within the lower protective layer 110.

Specifically, the lower protective layer 110 includes a first protective layer 111 and a second protective layer 112 on the first protective layer 111, and the first light blocking layer 180 includes the first protective layer. It may be disposed between (111) and the second protective layer (112). In the pixel P area, the first light blocking layer 180 may be omitted and the second light blocking layer 220 may be disposed instead.

The first flexible substrate 121 is disposed on the protective layer 110.

Referring to FIG. 15 , a first buffer layer 115 may be disposed on the first flexible substrate 121. The first thin film transistor TR1 and the second thin film transistor TR2 are disposed on the first buffer layer 115 on the first flexible substrate 121.

Referring to FIG. 15, a second light blocking layer 220 may be disposed on the first buffer layer 115. The first light blocking layer 180 may be omitted under the first thin film transistor TR1, and the second light blocking layer 220 may also be disposed under the first thin film transistor TR1. In this case, the lower second light blocking layer 220 of the first thin film transistor TR1 and the lower second light blocking layer 220 of the second thin film transistor TR2 are spaced apart from each other.

Referring to FIG. 15, the first light blocking layer 180 does not overlap the second light blocking layer 220.

The second buffer layer 141 is disposed on the second light blocking layer 220.

The first active layer A1 of the first thin film transistor TR1 and the second active layer A2 of the second thin film transistor TR2 may be disposed on the second buffer layer 141.

The first active layer (A1) and the second active layer (A2) may include, for example, an oxide semiconductor material. The first active layer (A1) and the second active layer (A2) may be formed of an oxide semiconductor layer made of an oxide semiconductor material.

The first active layer (A1) may include a channel portion, a first conductive portion, and a second conductive portion. The channel portion of the first active layer (A1) overlaps the first gate electrode (G1). According to another embodiment of the present invention, the first conductive part of the first active layer (A1) may be referred to as the first source electrode (S1), and the second conductive part may be referred to as the first drain electrode (D1). .

The second active layer A2 may include a channel portion, a first conductive portion, and a second conductive portion. The channel portion of the second active layer (A2) overlaps the second gate electrode (G2). According to another embodiment of the present invention, the first conductive part of the first active layer (A1) may be referred to as the second source electrode (S2), and the second conductive part may be referred to as the second drain electrode (D2). .

Referring to FIGS. 14 and 15 , a portion of the first active layer (A1) may be converted into a conductor to become the first capacitor electrode (C11) of the first capacitor (C1).

A gate insulating layer 142 is disposed on the first active layer (A1) and the second active layer (A2). The gate insulating layer 142 may cover the entire upper surface of the first active layer (A1) and the second active layer (A2), or may cover only a portion of the first active layer (A1) and the second active layer (A2). It may be possible.

The first gate electrode G1 of the first thin film transistor TR1 and the second gate electrode G2 of the second thin film transistor TR2 are disposed on the gate insulating film 142.

The first gate electrode G1 of the first thin film transistor TR1 overlaps at least a portion of the first active layer A1. The second gate electrode G2 of the second thin film transistor TR2 overlaps at least a portion of the second active layer A2.

An interlayer insulating film 143 is disposed on the first gate electrode G1 and the second gate electrode G2.

A data line DL and a driving power line PL are disposed on the interlayer insulating film 143.

The data line DL contacts the first source electrode S1 formed on the first active layer A1 through the first contact hole H1. According to another embodiment of the present invention, a part of the data line DL that overlaps the first active layer A1 may be referred to as the first source electrode S1.

The driving power line PL contacts the second drain electrode D2 formed in the second active layer A2 through the fifth contact hole H5. According to another embodiment of the present invention, a part of the driving power line PL that overlaps the second active layer A2 may be referred to as the second drain electrode D2.

Referring to FIGS. 14 and 15 , the second capacitor electrode C12, the first bridge BR1, and the second bridge BR2 of the first capacitor C1 are disposed on the interlayer insulating film 143.

The second capacitor electrode C12 overlaps the first capacitor electrode C11 to form the first capacitor C1.

The first bridge BR1 may be formed integrally with the second capacitor electrode C12. The first bridge BR1 is connected to the second light blocking layer 220 through the second contact hole H2 and to the second source electrode S2 through the third contact hole H3. As a result, the second light blocking layer 220 may be connected to the second source electrode S2 of the second thin film transistor TR2.

The second bridge BR2 is connected to the second gate electrode G2 of the second thin film transistor TR2 through the fourth contact hole H4, and is connected to the first capacitor C1 through the seventh contact hole H7. It is connected to the first capacitor electrode (C11).

The planarization layer 175 is disposed on the data line DL, the driving power line PL, the second capacitor electrode C12, the first bridge BR1, and the second bridge BR2. The planarization layer 175 planarizes the upper portions of the first thin film transistor TR1 and the second thin film transistor TR2 and protects the first thin film transistor TR1 and the second thin film transistor TR2.

The first electrode 711 of the display element 710 is disposed on the planarization layer 175. The first electrode 711 of the display element 710 contacts the second capacitor electrode C12 formed integrally with the first bridge BR1 through the sixth contact hole H6 formed in the planarization layer 175. . As a result, the first electrode 711 may be connected to the second source electrode S2 of the second thin film transistor TR2.

A bank layer 750 is disposed at the edge of the first electrode 711. The bank layer 750 defines the light-emitting area of the display element 710.

An organic emission layer 712 is disposed on the first electrode 711, and a second electrode 713 is disposed on the organic emission layer 712. Accordingly, the display element 710 is completed. The display element 710 shown in FIG. 15 is an organic light emitting diode (OLED). Accordingly, the display device 900 according to an embodiment of the present invention is an organic light emitting display device.

FIG. 16 is a circuit diagram of one pixel P of the display device 1000 according to another embodiment of the present invention.

Figure 16 is an equivalent circuit diagram for a pixel (P) of an organic light emitting display device.

The pixel P of the display device 1000 shown in FIG. 16 includes an organic light emitting diode (OLED), which is the display element 710, and a pixel driving circuit (PDC) that drives the display element 710. The display element 710 is connected to a pixel driving circuit (PDC).

In the pixel P, signal lines DL, GL, PL, RL, and SCL that supply signals to the pixel driving circuit PDC are disposed.

A data voltage (Vdata) is supplied to the data line (DL), a scan signal (SS) is supplied to the gate line (GL), and a driving voltage (Vdd) for driving the pixel is supplied to the driving power line (PL). The reference voltage (Vref) is supplied to the reference line (RL), and the sensing control signal (SCS) is supplied to the sensing control line (SCL).

The pixel driving circuit (PDC) includes, for example, a first thin film transistor (TR1) (switching transistor) connected to the gate line (GL) and the data line (DL), and a data voltage transmitted through the first thin film transistor (TR1). A second thin film transistor (TR2) (driving transistor) that controls the size of the current output to the display element 710 according to (Vdata), and a third thin film transistor (TR3) for detecting the characteristics of the second thin film transistor (TR2). ) (sensing transistor).

The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL, and the data voltage Vdata supplied to the data line DL is connected to the gate electrode of the second thin film transistor TR2. send to

The third thin film transistor TR3 is connected to the first node (n1) and the reference line (RL) between the second thin film transistor (TR2) and the display element 710, and is turned on or turned on by the sensing control signal (SCS). It is turned off, and the characteristics of the second thin film transistor (TR2), which is a driving transistor, are sensed during the sensing period.

The second node (n2) connected to the gate electrode of the second thin film transistor (TR2) is connected to the first thin film transistor (TR1). A storage capacitor Cst is formed between the second node n2 and the first node n1.

When the first thin film transistor TR1 is turned on, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode of the second thin film transistor TR2. The data voltage Vdata is charged in the storage capacitor Cst formed between the gate electrode and the source electrode of the second thin film transistor TR2.

When the second thin film transistor TR2 is turned on, current is supplied to the display element 710 through the second thin film transistor TR2 by the driving voltage Vdd that drives the pixel, and light is emitted from the display element 710. This is output.

FIG. 17 is a circuit diagram of one pixel P of the display device 1100 according to another embodiment of the present invention.

The pixel P of the display device 1100 shown in FIG. 17 includes an organic light emitting diode (OLED), which is the display element 710, and a pixel driving circuit (PDC) that drives the display element 710. The display element 710 is connected to a pixel driving circuit (PDC).

The pixel driving circuit (PDC) includes thin film transistors (TR1, TR2, TR3, and TR4).

In the pixel P, signal lines (DL, EL, GL, PL, SCL, RL) that supply driving signals to the pixel driving circuit (PDC) are disposed.

Compared to the pixel P in FIG. 16, the pixel P in FIG. 17 further includes an emission control line EL. The emission control signal (EM) is supplied to the emission control line (EL). In addition, compared to the pixel driving circuit (PDC) of FIG. 16, the pixel driving circuit (PDC) of FIG. 17 includes a fourth thin film transistor (TR4), which is a light emission control transistor for controlling the timing of light emission of the second thin film transistor (TR2). It further includes.

The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL, and the data voltage Vdata supplied to the data line DL is connected to the gate electrode of the second thin film transistor TR2. send to

A storage capacitor (Cst) is located between the gate electrode of the second thin film transistor (TR2) and the display element 710.

The third thin film transistor TR3 is connected to the reference line RL, is turned on or off by the sensing control signal SCS, and detects the characteristics of the third thin film transistor TR1, which is a driving transistor, during the sensing period.

The fourth thin film transistor TR4 transmits the driving voltage (Vdd) to the second thin film transistor (TR2) or blocks the driving voltage (Vdd) according to the emission control signal (EM). When the fourth thin film transistor TR4 is turned on, current is supplied to the second thin film transistor TR2, and light is output from the display element 710.

The pixel driving circuit (PDC) according to another embodiment of the present invention may be formed in various structures other than those described above. The pixel driving circuit (PDC) may include, for example, five or more thin film transistors.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications and changes can be made without departing from the technical details of the present invention in the technical field to which the present invention pertains. It will be obvious to anyone with ordinary knowledge. Therefore, the scope of the present invention is indicated by the claims described below, and all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention.

110: lower protective layer 111: first protective layer
112: second protective layer 115: first buffer layer
121: first flexible substrate 122: first flexible substrate
130: first active layer 130n, 230n: channel portion
131, 231: first conductor section 132, 232: second conductor section
141: second buffer layer 142: gate insulating film
143: interlayer insulating film 150: first gate electrode
161, 261: source electrode 162, 262: drain electrode
180: first light blocking layer 190: carrier substrate
195: sacrificial layer 220: second light blocking layer
230: second active layer 250: second gate electrode
TR1: first thin film transistor TR2: second thin film transistor

Claims (23)

A first light blocking layer;
a first flexible substrate on the first light blocking layer;
Includes a first thin film transistor and a second thin film transistor on the first flexible substrate,
The first thin film transistor,
a first active layer on the first flexible substrate; and
It includes a first gate electrode spaced apart from the first active layer,
The second thin film transistor,
a second active layer on the first flexible substrate; and
It includes a second gate electrode spaced apart from the second active layer,
The first light blocking layer overlaps the first active layer,
The first flexible substrate is a thin film transistor substrate disposed between the first light blocking layer and the first thin film transistor. According to paragraph 1,
A thin film transistor substrate disposed between the first flexible substrate and the second active layer and further comprising a second light blocking layer overlapping the second active layer. According to paragraph 2,
The first light blocking layer does not overlap the second light blocking layer. According to paragraph 2,
The first light blocking layer overlaps the second light blocking layer. According to paragraph 1,
Further comprising a lower protective layer,
The first flexible substrate is a thin film transistor substrate disposed between the first thin film transistor and the lower protective layer. According to clause 5,
The first light blocking layer is disposed in the lower protective layer. According to clause 5,
The lower protective layer is,
first protective layer; and
It includes a second protective layer on the first protective layer,
The first protective layer and the second protective layer each have electrical insulation,
The first light blocking layer is disposed between the first protective layer and the second protective layer. According to clause 5,
Further comprising a second flexible substrate,
The lower protective layer is disposed between the first flexible substrate and the second flexible substrate. According to clause 8,
A thin film transistor substrate, wherein the first light blocking layer is disposed between the first flexible substrate and the second flexible substrate, and does not contact the first flexible substrate and does not contact the second flexible substrate. According to clause 8,
The first light blocking layer is in contact with the second flexible substrate and the lower protective layer. According to clause 5,
The first light blocking layer is in contact with the lower protective layer and the first flexible substrate. According to clause 8,
The first light blocking layer is in contact with the second flexible substrate and does not contact the lower protective layer. According to paragraph 1,
At least one of the first active layer and the second active layer,
A first oxide semiconductor layer; and
Including, a second oxide semiconductor layer on the first oxide semiconductor layer,
Thin film transistor substrate. According to paragraph 1,
A thin film transistor substrate wherein the distance between the first active layer and the first light blocking layer along the thickness direction is in the range of 2.5 to 10.5 ㎛. According to paragraph 2,
The second thin film transistor includes a second source electrode and a second drain electrode that are spaced apart from each other and are respectively connected to the second active layer,
A thin film transistor substrate, wherein one of the second source electrode and the second drain electrode is connected to the second light blocking layer. The thin film transistor substrate of any one of claims 1 to 15; and
Including a display element;
Display device. According to clause 16,
The display element is,
first electrode;
an organic light-emitting layer on the first electrode; and
A display device comprising: a second electrode on the organic emission layer. According to clause 17,
The second electrode is connected to the first light blocking layer. According to clause 16,
Includes a gate driver on the first flexible substrate,
The display device wherein the gate driver includes the first thin film transistor. According to clause 19,
The first light blocking layer overlaps the gate driver. According to clause 16,
The first light blocking layer surrounds an edge of the first flexible substrate in a plan view. According to clause 16,
It includes a pixel driving circuit on the first flexible substrate,
The display device wherein the pixel driving circuit includes the first thin film transistor and the second thin film transistor. According to clause 22,
The second thin film transistor is connected to the display element.

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