KR20230172166A - Semiconductor test system - Google Patents

Abstract

A semiconductor test system according to an embodiment of the present disclosure is connected to a plurality of semiconductor test devices and a user terminal, and is directly connected to a first interface included in the plurality of semiconductor test devices through a parallel bus. and an interface unit, wherein the user terminal transmits a simultaneous control signal for simultaneously controlling the plurality of semiconductor test devices to each of the plurality of semiconductor test devices through the interface unit, wherein the first interface is configured to: It mediates signal transmission and reception between a processor provided in and one or more boards provided in the semiconductor test device.

Description

Semiconductor test system {SEMICONDUCTOR TEST SYSTEM}

This disclosure relates to a semiconductor test system, and more specifically, to a semiconductor test system capable of controlling a plurality of semiconductor test devices through a bus interface.

Semiconductor test equipment, also referred to as Automatic Test Equipment (ATE), is a device that verifies whether a semiconductor device is good by applying an electrical pattern signal to the semiconductor device and analyzing the response.

Semiconductor test equipment has internal hardware components such as power supply, instrumentation, Algorithmic Pattern Generator (ALPG), Timing Generator (TG), Pin Electronics (PE) with built-in drivers and comparators, and a central processing unit (CPU) for controlling them.

In the case of testing multiple semiconductor devices using multiple semiconductor test devices, a PC and each semiconductor test device are connected via LAN, and a P2P (peer to peer) connection is used to transmit test commands from the PC to each semiconductor test device. It is common to use the method of forwarding to a peer).

In this case, when the PC individually transmits a control command to each of a plurality of semiconductor test devices, the CPU of each semiconductor test device autonomously performs the test of the target semiconductor device, and the PC causes all CPUs of each semiconductor test device to perform the test. The test is completed through the process of checking whether it has been completed by polling.

However, this existing method has a problem in that it is difficult to transmit commands to simultaneously control a plurality of semiconductor test devices from a PC.

In particular, when the pattern generated in ALPG must be loaded for each semiconductor test device, when the test must be started or stopped using the loaded pattern, when the power supply to the semiconductor device must be controlled, and when the DC test must be performed. Simultaneous control is necessary in cases where multiple units must be controlled, but with the existing method, only individual control is possible, so delays occur in the process of transmitting commands to each semiconductor test device and completing the test.

Therefore, a technology that can control multiple semiconductor test devices simultaneously rather than the existing individual control method is required.

Republic of Korea Patent Publication No. 10-2005-0120168 (published on December 22, 2005)

The technical problem that the present disclosure aims to solve is a semiconductor test system that provides an interface structure that can simultaneously control the test functions of each of the plurality of semiconductor test devices when testing a semiconductor device using a plurality of semiconductor test devices. is to provide.

Another technical problem that the present disclosure aims to solve is that, in the case of testing a semiconductor device using a plurality of semiconductor test devices, loading of a pattern generated in ALPG and testing using the loaded pattern are performed on a plurality of semiconductors without delay. The goal is to provide a semiconductor test system that enables simultaneous test equipment.

Another technical problem that the present disclosure aims to solve is to provide a semiconductor test system that can simultaneously control the power supply to each of the plurality of semiconductor test devices when testing a semiconductor device using a plurality of semiconductor test devices. It is done.

The technical problems of the present disclosure are not limited to the technical problems mentioned above, and other technical problems not mentioned can be clearly understood by those skilled in the art from the description below.

In order to solve the above technical problem, a semiconductor test system according to an embodiment of the present disclosure is connected to a plurality of semiconductor test devices and a user terminal, and includes a first interface and a parallel bus ( an interface unit directly connected through a parallel bus, wherein the user terminal transmits a simultaneous control signal for simultaneously controlling the plurality of semiconductor test devices to each of the plurality of semiconductor test devices through the interface unit, 1 Interface mediates signal transmission and reception between a processor provided in the semiconductor test device and one or more boards provided in the semiconductor test device.

In one embodiment, the interface unit may be connected to the user terminal using a PCIe (PCI express) bus, and may be connected to the first interface included in the plurality of semiconductor test devices using a 32-bit PCI bus.

In one embodiment, the semiconductor test device includes an algorithm pattern generator (ALPG) that generates pattern data to be applied to a semiconductor device, a timing generator that generates a timing signal using pattern data generated by the algorithm pattern generator, and a plurality of devices. It may include a power supply unit that supplies power having a voltage to the semiconductor device, and a DC unit that supplies power for DC testing to the semiconductor test device.

In one embodiment, the user terminal may transmit a simultaneous control signal to each of the plurality of semiconductor test devices through the interface unit so that pattern data generated by the algorithm pattern generator is loaded simultaneously.

In one embodiment, the user terminal may transmit a simultaneous control signal to each of the plurality of semiconductor test devices through the interface unit to simultaneously start or stop testing using the loaded pattern data.

In one embodiment, the user terminal may transmit a simultaneous control signal to each of the plurality of semiconductor test devices through the interface unit to simultaneously turn on or off power supply by the power supply unit and the DC unit.

In one embodiment, it is connected to the user terminal and further includes a communication interface unit connected to a processor provided in the plurality of semiconductor test devices through a LAN, and the user terminal is connected to one of the plurality of semiconductor test devices. An individual control signal for control may be transmitted to the processor provided in the semiconductor test device through the communication interface unit.

1 is a block diagram showing the configuration of a semiconductor test system according to an embodiment of the present disclosure.
FIG. 2 illustrates a detailed configuration of a semiconductor test system for controlling a plurality of semiconductor test devices according to an embodiment of the present disclosure.
Figure 3 is an example of simultaneous control signal transmission from a user terminal to a plurality of semiconductor test devices according to some embodiments of the present disclosure.

Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the attached drawings. The advantages and features of the present disclosure and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the technical idea of the present disclosure is not limited to the following embodiments and may be implemented in various different forms. The following examples are merely intended to complete the technical idea of the present disclosure and to be used in the technical field to which the present disclosure belongs. It is provided to fully inform those skilled in the art of the scope of the present disclosure, and the technical idea of the present disclosure is only defined by the scope of the claims.

When adding reference numerals to components in each drawing, it should be noted that identical components are given the same reference numerals as much as possible even if they are shown in different drawings. Additionally, in describing the present disclosure, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present disclosure, the detailed description will be omitted.

Unless otherwise defined, all terms (including technical and scientific terms) used in this specification may be used with meanings that can be commonly understood by those skilled in the art to which this disclosure pertains. Additionally, terms defined in commonly used dictionaries are not interpreted ideally or excessively unless clearly specifically defined. The terminology used herein is for the purpose of describing embodiments and is not intended to limit the disclosure. As used herein, singular forms also include plural forms, unless specifically stated otherwise in the context.

Additionally, in describing the components of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, or order of the component is not limited by the term. When a component is described as being “connected,” “coupled,” or “connected” to another component, that component may be directly connected or connected to that other component, but there is another component between each component. It will be understood that elements may be “connected,” “combined,” or “connected.”

As used in the specification, “comprises” and/or “comprising” refers to the presence of one or more other components, steps, operations and/or elements. or does not rule out addition.

Hereinafter, several embodiments of the present disclosure will be described in detail with reference to the attached drawings.

1 is a block diagram showing the configuration of a semiconductor test system according to an embodiment of the present disclosure. Referring to FIG. 1, the semiconductor test system 1 includes a plurality of semiconductor test devices 101, 102, ..., 103, a user terminal 10, an interface unit 11, and a communication interface unit 12. Includes composition.

Each of the plurality of semiconductor test devices 101, 102, ..., 103 applies an electrical test signal to the semiconductor device and analyzes the resulting test results to determine whether the semiconductor device is good.

Each of the plurality of semiconductor test devices 101, 102, ..., 103 includes an algorithm pattern generator (ALPG) (see symbol 1016 in FIG. 2), a timing generator (see symbol 1015 in FIG. 2), and pin electronics (not shown). , a test analysis module (not shown), a power supply unit (see symbol 1014 in FIG. 2), a DC unit (see symbol 1013 in FIG. 2), a CPU (see symbol 1011 in FIG. 2), and a first interface (see symbol 1014 in FIG. 2). 1012), and may further include additional components necessary for testing semiconductor devices.

The algorithm pattern generator (ALPG) 1016 sequentially generates logic data using data stored in memory. Logic data may include addresses, data, control signals, etc. to be applied to the semiconductor device. Logic data is provided to the timing generator 1015 along with a clock signal in the form of pulse data expressed as “0” and “1.”

The timing generator 1015 generates a timing signal based on pulse data input through a plurality of channels. The generated timing signal is transmitted to pin electronics (not shown).

Pin Electronics (not shown) uses a timing signal to generate a test signal for electrical testing of a semiconductor device and applies the generated test signal to the semiconductor device. Pin electronics (not shown) may include DCL (Driver Comparator Logic (not shown)) that receives a timing signal and a pattern signal and generates a test signal by modulating the pattern signal based on the timing signal.

The test analysis module (not shown) receives a change in the electrical state or response of the semiconductor device according to the application of a test signal as a test result, and analyzes it to determine whether the semiconductor device is good or bad. According to the result of determining whether the product is good or not, repair work may be performed on a failed semiconductor device.

The power supply unit 1014 supplies power having a plurality of voltages to the semiconductor device. Additionally, the DC unit 1013 supplies power for DC testing to the semiconductor test device.

Again, looking at the configuration of the semiconductor test system 1, the user terminal 10 transmits a control signal to control each device to a plurality of semiconductor test devices 101, 102, ..., 103, and Receive a corresponding response. The user terminal 10 may transmit a control signal through the interface unit 11 or the communication interface unit 12. Here, the interface unit 11 is an interface based on the PCI bus standard, and the communication interface unit 12 is an interface based on LAN communication.

Specifically, the user terminal 10 transmits a simultaneous control signal to simultaneously control each device to a plurality of semiconductor test devices 101, 102, ..., 103 through the interface unit 11 based on the PCI bus standard. You can. At this time, the interface unit 11 is connected to the user terminal 10 and runs in parallel with the first interface (see symbol 1012 in FIG. 2) included in each of the plurality of semiconductor test devices 101, 102, ..., 103. They are directly connected through a parallel bus.

Additionally, the user terminal 10 may transmit an individual control signal to one of the plurality of semiconductor test devices 101, 102, ..., 103 through the communication interface unit 12 based on LAN communication. At this time, the communication interface unit 12 is connected to the user terminal 10 and connected to the CPU 1011 provided in each of the plurality of semiconductor test devices 101, 102, ... 103 through LAN.

According to the configuration of the semiconductor test system as described above, when testing a semiconductor device using a plurality of semiconductor test devices, an interface that can simultaneously control the test function of each of the plurality of semiconductor test devices and an interface that can control them individually All possible interfaces can be provided.

FIG. 2 illustrates the configuration of a semiconductor test system for controlling a plurality of semiconductor test devices according to an embodiment of the present disclosure. The configuration shown in FIG. 2 includes the detailed configuration of each of the plurality of semiconductor test devices 101, 102, ..., 103 described in FIG. 1, and the plurality of semiconductor test devices 101, 102, and ..., 103) and includes detailed interfaces for simultaneous or individual control.

In the illustrated configuration, each of the plurality of semiconductor test devices 101, ..., 103 has a detailed configuration, including a CPU 1011, a first interface 1012, a DC unit 1013, and a Device Power Supply (DPS) ( 1014), TG (Timing Generator) (1015), and ALPG (Algorithmic Pattern Generator) (1016).

As an embodiment, the user terminal 10 is connected to the interface board 110 using a PCIe bus (PCI express bus), and the interface board 110 is connected to a plurality of semiconductor test devices 101, ..., 103. It can be connected to the first interface 1012 included in each using a parallel bus. The parallel bus may be, for example, a 32-bit peripheral component interconnect (PCI).

Here, the first interface 1012 transmits and receives signals between the CPU 1011 provided in each of the plurality of semiconductor test devices 101, ..., 103 and one or more boards 1013, 1014, 1015, and 1016. It may be an intermediary interface.

As described above, the user terminal 10 connects one or more boards ( Simultaneous control signals to control (1013, 1014, 1015, 1016) can be transmitted.

Accordingly, through simultaneous control of the test performance of each of the plurality of semiconductor test devices 101, ..., 103, semiconductor device testing can be performed without delay.

In addition, the user terminal 10 is connected to the hub 120 through a LAN, and the hub 120 is connected to the CPU 1011 provided in each of the plurality of semiconductor test devices 101, ..., 103 through the LAN. can be connected At this time, each of the plurality of semiconductor test devices 101, ..., 103 may be equipped with a LAN card 1017 for LAN connection.

As described above, the user terminal 10 connects one or more boards 1013 to any one CPU 1011 of the plurality of semiconductor test devices 101, ..., 103 through the hub 120 based on LAN communication. 1014, 1015, and 1016) can be transmitted. Accordingly, it is also possible to perform individual control on any one of the plurality of semiconductor test devices 101, ..., 103.

Figure 3 is an example of simultaneous control signal transmission from a user terminal to a plurality of semiconductor test devices according to some embodiments of the present disclosure. The configuration shown in FIG. 3 shows only the configuration for simultaneously controlling a plurality of semiconductor test devices 101, ..., 103 from the user terminal 10 among the configurations in FIG. 1, and the configuration for individual control is Omitted.

In the illustrated example, the user terminal 10 is connected to the interface unit 11 using the PCIe bus 31, and the interface unit 11 is connected to each of a plurality of semiconductor test devices 101, ..., 103. It can be connected using the PCI bus 32, which is a parallel bus.

As an embodiment, the user terminal 10 uses a plurality of semiconductor test devices 101 through an interface unit 11 based on the PCI bus standard so that pattern data generated by an algorithm pattern generator (see symbol 1016 in FIG. 2) is loaded simultaneously. , 102, ..., 103), a simultaneous control signal 33 for pattern loading can be transmitted respectively.

In addition, the user terminal 10 starts/stops the pattern with each of the plurality of semiconductor test devices 101, 102, ..., 103 through the interface unit 11 to simultaneously start or stop the test using the loaded pattern data. A simultaneous control signal 34 for stopping can be transmitted.

In addition, the user terminal 10 uses a plurality of semiconductor test devices 101 through the interface unit 11 to simultaneously turn on or off the power supply by the power supply unit (1014 in FIG. 2) and the DC unit (1013 in FIG. 2). , 102, ..., 103) can transmit a simultaneous control signal 35 for power on/off, respectively.

According to the above embodiment, loading of patterns generated in ALPG and testing using the loaded patterns can be performed simultaneously in a plurality of semiconductor test devices without delay. Additionally, power supply to each of a plurality of semiconductor test devices can be controlled simultaneously.

Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical idea or essential features. I can understand that there is. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of the present invention shall be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope shall be construed as being included in the scope of rights of the technical ideas defined by the present invention.

Claims (7)

In a semiconductor test system,
A plurality of semiconductor test devices; and
An interface unit connected to a user terminal and directly connected to a first interface included in the plurality of semiconductor test devices through a parallel bus,
The user terminal transmits a simultaneous control signal for simultaneously controlling the plurality of semiconductor test devices to each of the plurality of semiconductor test devices through the interface unit,
The first interface is,
Mediating signal transmission and reception between a processor provided in the semiconductor test device and one or more boards provided in the semiconductor test device,
Semiconductor test system. According to claim 1,
The interface unit,
Connected to the user terminal using a PCIe (PCI express) bus, and connected to the first interface included in the plurality of semiconductor test devices using a 32-bit PCI bus,
Semiconductor test system. According to claim 1,
The semiconductor test device is,
An algorithm pattern generator (ALPG) that generates pattern data to be applied to a semiconductor device;
a timing generator that generates a timing signal using pattern data generated by the algorithm pattern generator;
a power supply unit that supplies power having a plurality of voltages to the semiconductor device; and
Including a DC unit that supplies power for DC testing to the semiconductor test device,
Semiconductor test system. According to clause 3,
The user terminal is,
Transmitting simultaneous control signals to each of the plurality of semiconductor test devices through the interface unit so that the pattern data generated by the algorithm pattern generator is loaded simultaneously,
Semiconductor test system. According to clause 4,
The user terminal is,
Transmitting simultaneous control signals to each of the plurality of semiconductor test devices through the interface unit to simultaneously start or stop testing using the loaded pattern data,
Semiconductor test system. According to clause 3,
The user terminal is,
Transmitting a simultaneous control signal to each of the plurality of semiconductor test devices through the interface unit to simultaneously turn on or off the power supply by the power supply unit and the DC unit,
Semiconductor test system. According to claim 1,
It further includes a communication interface unit connected to the user terminal and connected to a processor provided in the plurality of semiconductor test devices through a LAN,
The user terminal is,
Transmitting an individual control signal for controlling one of the plurality of semiconductor test devices to the processor provided in the semiconductor test device through the communication interface unit,
Semiconductor test system.

Images