KR20230169663A - A semiconductor device of bonding type - Google Patents

Abstract

In a bonded semiconductor device, first circuit patterns are provided on a first substrate. A lower interlayer insulating film is provided covering the first circuit patterns. A first bonding pad pattern having an upper surface protruding from the upper surface of the lower interlayer insulating film is provided on the lower interlayer insulating film. Second circuit patterns are provided on the base layer pattern spaced apart from the first substrate. An interlayer insulating film is provided that covers the second circuit patterns on the lower interlayer insulating film, has a lowermost part facing the lower interlayer insulating film, and has an opening formed in the lowermost part. A second bonding pad pattern is provided inside the lower part of the interlayer insulating film and has one side wall exposed by the opening. The first bonding pad pattern has a shape inserted into the opening, and one sidewall of the second bonding pad pattern is in contact with and bonded to one sidewall of the first bonding pad pattern.

Description

Bonding type semiconductor device {A SEMICONDUCTOR DEVICE OF BONDING TYPE}

The present invention relates to semiconductor devices. More specifically, it relates to a bonded vertical semiconductor device.

A bonded semiconductor device can be formed by bonding a first substrate on which first circuit patterns are formed and a second substrate on which second circuit patterns are formed. In manufacturing the bonded semiconductor device, electrical defects may occur due to bonding defects.

One object of the present invention is to provide a bonded semiconductor device.

In order to achieve the object of the present invention, a bonded semiconductor device according to embodiments of the present invention is provided with first circuit patterns on a first substrate. A lower interlayer insulating film is provided covering the first circuit patterns. A first bonding pad pattern having an upper surface protruding from the upper surface of the lower interlayer insulating film is provided on the lower interlayer insulating film. Second circuit patterns are provided on the base layer pattern spaced apart from the first substrate. An interlayer insulating film is provided that covers the second circuit patterns on the lower interlayer insulating film, has a lowermost part facing the lower interlayer insulating film, and has an opening formed in the lowermost part. A second bonding pad pattern is provided inside the lower part of the interlayer insulating film and has one side wall exposed by the opening. The first bonding pad pattern has a shape inserted into the opening, and one sidewall of the second bonding pad pattern is in contact with and bonded to one sidewall of the first bonding pad pattern.

In order to achieve the object of the present invention, a bonded semiconductor device according to embodiments of the present invention is provided with first circuit patterns on a first substrate. A lower interlayer insulating film is provided covering the first circuit patterns. A first bonding pad pattern is provided on the lower interlayer insulating layer. Second circuit patterns are provided on the base layer pattern spaced apart from the first substrate. An interlayer insulating film is provided to cover the second circuit patterns on the lower interlayer insulating film, and whose lowermost part faces the lower interlayer insulating film. A second bonding pad pattern is provided below the interlayer insulating layer. A bonding film is provided between the upper surface of the lower interlayer insulating film and the lowermost surface of the interlayer insulating film to bond the lower interlayer insulating film and the interlayer insulating film. It has a structure in which one sidewall of the first bonding pad pattern and one sidewall of the second bonding pad pattern are in contact with each other and bonded to each other.

Bonded semiconductor devices according to example embodiments have a structure in which one sidewall of the first bonding pad pattern and one sidewall of the second bonding pad pattern are in contact with each other and are bonded to each other. Therefore, even if a step occurs at the bonding surfaces bonded to each other, at least a portion of the sidewalls of the first and second bonding pad patterns can be bonded. Therefore, defects in which the first and second bonding pad patterns are not electrically connected can be reduced.

1 to 16 are cross-sectional views for explaining a method of manufacturing a bonded semiconductor device according to example embodiments.
17 to 20 are cross-sectional views for explaining a method of manufacturing a bonded semiconductor device according to example embodiments.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

Hereinafter, a direction parallel to the substrate surface will be referred to as a first direction, and a direction parallel to the substrate surface and perpendicular to the first direction will be referred to as a second direction. Additionally, the description will be made while referring to the direction perpendicular to the substrate surface as the vertical direction.

1 to 16 are cross-sectional views for explaining a method of manufacturing a bonded semiconductor device according to example embodiments.

Referring to FIG. 1, lower circuit patterns 110 are formed on the first substrate 100.

In an exemplary embodiment, the lower circuit patterns 110 may include peripheral circuits. The lower circuit patterns 110 may include, for example, transistors and wiring. A lower interlayer insulating film 120 is formed to cover the lower circuit patterns 110 .

The first substrate 100 may include a semiconductor material such as silicon, germanium, or silicon-germanium, or a group III-V compound such as GaP, GaAs, or GaSb. According to some embodiments, the first substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

A first bonding film 122 is formed on the uppermost surface of the lower interlayer insulating film 120. In an exemplary embodiment, the first bonding film 122 may include SiCN.

Referring to FIG. 2, an upper sacrificial layer 124 is formed on the first bonding layer 122. A portion of the upper sacrificial layer 124 and the first bonding layer 122 is etched to form a first opening 126 at a portion for forming a first bonding pad pattern. The wiring of the lower circuit pattern 110 may be exposed on the bottom of the first opening 126.

A first bonding pad pattern 130 is formed to fill the inside of the first opening 126. In an exemplary embodiment, a metal film is formed on the upper sacrificial film 124 to fill the inside of the first opening 126, and the metal film is flattened to expose the upper surface of the upper sacrificial film 124. A first bonding pad pattern 130 may be formed.

The first bonding pad pattern 130 may be electrically connected to wires included in the lower circuit patterns 110. In an exemplary embodiment, the bottom surface of the first bonding pad pattern 130 may be in direct contact with the wires.

The first bonding pad pattern 130 may include a metal material. The first bonding pad pattern 130 may include copper, aluminum, etc., for example.

The first bonding pad pattern 130 may be formed in an area where the bonding pad structure of the final bonded semiconductor device is to be formed. The first bonding pad pattern 130 may be provided as a part of the bonding pad structure. Accordingly, the first bonding pad pattern 130 may be formed to have a width narrower than the target width of the bonding pad structure.

Referring to FIG. 3, the upper sacrificial layer 124 is removed. Accordingly, the first bonding film 122 and the first bonding pad pattern 130 may be exposed on the first substrate 100. Additionally, the first bonding pad pattern 130 may protrude from the top surface of the first bonding film 122. The first bonding film 122 is disposed between the first bonding pad patterns 130, and the sidewall and top surface of the first bonding pad pattern 130 may be exposed to the outside.

A process for forming memory cells on a second substrate will be described with reference to FIGS. 4 to 8 .

In an exemplary embodiment, a memory cell of a vertical semiconductor memory device may be formed on the second substrate. However, the structure of memory cells formed on the second substrate is not limited to this. Additionally, an example of a method of manufacturing vertical memory cells will be briefly described with reference to FIGS. 4 to 8 , but the method of manufacturing vertical memory cells is not limited thereto.

Referring to FIG. 4, a base layer is formed on the second substrate 200. A first sacrificial layer, a second sacrificial layer, and a third sacrificial layer are sequentially formed on the base layer. A first support layer is formed on the third sacrificial layer.

The base layer may include polysilicon. The first and third sacrificial layers may each include an oxide such as silicon oxide, and the second sacrificial layer may include a nitride such as silicon nitride. The first support film may include polysilicon.

A first insulating layer and a fourth sacrificial layer may be alternately and repeatedly stacked on the first support layer along the vertical direction. The first insulating layer may include silicon oxide, and the fourth sacrificial layer may include silicon nitride.

Afterwards, the first insulating films and the fourth sacrificial films are sequentially etched to form a mold structure 230 whose sidewalls have a step shape. The mold structure 230 may have a structure in which first insulating patterns 220 and fourth sacrificial patterns 222 are alternately stacked. Subsequently, the first support layer, first to third sacrificial layers, and base layer under the mold structure 230 are etched to form a first support layer pattern 216, first to third sacrificial layer patterns 210, 212, 214) and a base film pattern 201a are formed.

A first interlayer insulating film 240 covering the mold structure 230 is formed on the second substrate 200. After this, a process of planarizing the upper surface of the first interlayer insulating film 240 may be further performed.

Afterwards, the first interlayer insulating layer 240, the mold structure 230, the first support layer pattern 216, the first to third sacrificial layer patterns 210, 212, and 214, and the base layer pattern 201a. By etching the upper part of the first interlayer insulating layer 240, the mold structure 230, the first support layer pattern 216, and the first to third sacrificial layer patterns 210, 212, and 214, the base layer is etched. Channel holes 250 extending to the inside of the pattern 201a are formed. The channel holes 250 may be regularly arranged in cell blocks.

Referring to FIG. 5, a first blocking dielectric layer, a charge storage layer, and a tunnel insulating layer are sequentially formed conformally on the sidewalls and bottom of the channel hole 250 and the first interlayer insulating layer 240.

The first blocking dielectric layer may include silicon oxide, the charge storage layer may include silicon nitride, and the tunnel insulating layer may include silicon oxide. A channel film is conformally formed on the tunnel insulating film. A buried insulating film is formed on the channel film to completely fill the inside of the channel hole 250. The buried insulating film may include an oxide, for example, silicon oxide.

The buried insulating layer, the channel layer, the first blocking dielectric layer, the charge storage layer, and the tunnel insulating layer may be planarized until the top surface of the first interlayer insulating layer 240 is exposed. Afterwards, the upper portions of the buried insulating film and the channel film are removed to form a first recess, and a capping pattern 288 is formed inside the first recess. For example, the capping pattern 288 may include polysilicon doped with impurities or undoped.

Accordingly, the channel hole 250 includes a preliminary first blocking dielectric layer pattern, a charge storage layer pattern, a preliminary tunnel insulating layer pattern, a channel 284, a first buried insulating pattern 286, and a capping pattern 288. A preliminary channel structure 290 may be formed.

To avoid complication in the drawing, in FIG. 5, the preliminary first blocking dielectric layer pattern, the preliminary charge storage layer pattern, and the preliminary tunnel insulating layer pattern are shown as a single layer, which is referred to as the preliminary data storage pattern 280.

Referring to FIG. 6, the first interlayer insulating film 240 in the area where the mold structure 230 is not formed is etched to penetrate the first interlayer insulating film 240 and reach the top of the second substrate 200. Extending first contact holes 300 are formed.

A barrier metal film is formed on the surfaces of the first contact holes 300, and a metal film is formed on the barrier metal film. Afterwards, the metal film and the barrier metal film are planarized so that the upper surface of the first interlayer insulating film 240 is exposed. Accordingly, the first contact plug 302 is formed in the first contact hole 300. The first contact plug 302 may include a first barrier metal pattern 302a and a metal pattern 302b.

Thereafter, after forming the second interlayer insulating film 310 on the first interlayer insulating film 240, the preliminary channel structure 290, and the first contact plug 302, the second interlayer insulating film 310 and the first interlayer insulating film 310 are formed on the first interlayer insulating film 310 and the first contact plug 302. A trench (not shown) penetrating the interlayer insulating film 240 and the mold structure 230 is formed through, for example, a dry etching process. The surface of the first support film pattern 216 may be exposed on the bottom of the trench.

The trench may extend in the first direction, and a plurality of trenches may be formed in the second direction. As the trench is formed, the mold structures 230 may be separated from each other. Accordingly, the mold structure 230 may extend in the first direction.

Referring to FIG. 7, spacers (not shown) are formed on the sidewalls of the trench, and the first to third sacrificial layer patterns 210, 212, and 214 below the first support layer pattern 216 are removed, A first gap (not shown) is formed between the first support film pattern 216 and the base film pattern 201a. The upper surface of the base layer pattern 201a may be exposed at the bottom of the first gap.

Additionally, the lower sidewall of the preliminary data storage pattern 280 may be exposed by the first gap, and the exposed preliminary data storage pattern 280 is removed to expose the outer sidewall of the channel 284. Accordingly, the lower portion of the preliminary data storage pattern 280 may be cut to form a data storage pattern 281 having an upper and lower portion. The data storage pattern 281 may have a structure in which a first blocking dielectric layer pattern, a charge storage layer pattern, and a tunnel insulating layer pattern are stacked. In addition, in the channel hole 250, a channel structure including a first blocking dielectric layer pattern, a charge storage layer pattern, a tunnel insulating layer pattern, a channel 284, a first buried insulating pattern 286, and a capping pattern 288 ( 290a) may be formed.

After this, the spacer can be removed. A channel connection pattern 312 is formed to fill the first gap region. The channel connection pattern 312 contacts the lower sidewalls of the channels 284 and electrically connects the lower portions of the channels to each other. Additionally, the channel connection pattern 312 contacts the upper surface of the base layer pattern and electrically connects the channels 284 and the base layer pattern 201a to each other. The channel connection pattern 312 may include polysilicon doped with impurities.

Next, the fourth sacrificial patterns 222 may be removed to form a second gap (not shown) between the first insulating patterns 220 formed in each layer. A portion of the outer wall of the first blocking dielectric layer pattern of the data storage pattern 281 may be exposed by the second gap.

A second blocking film (not shown) may be formed on the surface of the trench and the second gap and on the top surface of the second interlayer insulating film 310, and a gate electrode film may be formed on the second blocking film. Afterwards, by partially removing the gate electrode film, the gate electrode 304 can be formed inside each of the first gaps.

In example embodiments, the gate electrode 304 may extend in the first direction, and a plurality of gate electrodes 304 may be stacked while being spaced apart from each other in the vertical direction.

Accordingly, a pattern structure 230a in which the gate electrode 304 and the first insulating pattern 220 are repeatedly stacked can be formed on the base layer pattern 201a. At this time, a plurality of the pattern structures 230a may be formed in the second direction by being spaced apart from each other by the trench. Afterwards, a second buried insulating pattern (not shown) is formed to fill the inside of the trench.

Referring to FIG. 8, a second contact plug 320 is formed that penetrates the second interlayer insulating film 310 and contacts the capping pattern 288 and the first contact plug 302 of each channel structure 290a. do.

Although not shown, cell contact plugs are formed that penetrate the first and second interlayer insulating films 240 and 310 and the first insulating pattern 220 and contact the gate electrodes 304 of each layer. The cell contact plugs may each be formed at a step-shaped portion at the edge of the pattern structure 230a.

A third interlayer insulating film 330 is formed on the second interlayer insulating film 310, the second contact plug 320, and the cell contact plug. A first wiring 332 is formed through the third interlayer insulating film 330 and electrically connected to the second contact plug 320. In an exemplary embodiment, the first wiring 332 may include a contact plug and a conductive line.

A first diffusion barrier layer 338 is formed on the third interlayer insulating layer 330 and the first wiring 332. The first diffusion barrier layer 338 may include, for example, a silicon nitride layer, a silicon oxynitride layer, or a SiOCN layer.

A fourth interlayer insulating layer 340 is formed on the first diffusion barrier layer 338. A second interconnection 342 is formed through the fourth interlayer insulating layer 340 and the first diffusion barrier layer 338 and is electrically connected to the first interconnection 332 . In an exemplary embodiment, the second wiring 342 may include a contact plug and a conductive line. The second wiring 342 may include a metal material.

In an exemplary embodiment, the second wires 342 may be formed through a dual damascene process or a single damascene process.

Subsequently, a second diffusion barrier layer 348 and a fifth interlayer insulating layer 350 are formed on the fourth interlayer insulating layer 340 and the second wiring 342. A third interconnection 352 electrically connected to the second interconnection 342 is formed through the fifth interlayer insulating layer 350 and the second diffusion barrier layer 348. In this way, multi-layered wirings can be formed.

Memory structures and metal wires may be formed on the second substrate 200 through the processes described with reference to FIGS. 2 to 8 .

Referring to FIG. 9, a sixth interlayer insulating film 360 is formed on the fifth interlayer insulating film 350 and the third wiring 352. The sixth interlayer insulating film 360 may be the uppermost interlayer insulating film.

A second bonding layer 362 is formed on the sixth interlayer insulating layer 360. In an exemplary embodiment, the second bonding layer 362 may include the same material as the first bonding layer 122 formed on the first substrate 100 . The second bonding film 362 may include SiCN.

A portion of the second bonding layer 362 and the sixth interlayer insulating layer 360 is etched to form a second opening at a portion for forming a second bonding pad pattern. A second bonding pad pattern 364 is formed to fill the inside of the second opening.

In an exemplary embodiment, a metal film is formed on the second bonding film 362 to fill the inside of the second opening, and the metal film is flattened so that the upper surface of the second bonding film 362 is exposed. 2 Bonding pad patterns 364 can be formed. The second bonding pad pattern 364 may be electrically connected to the third wires 352. In an exemplary embodiment, a contact in contact with the third wires 352 may be formed under the second bonding pad pattern 364 .

The second bonding pad pattern 364 may include a metal material. The second bonding pad pattern 364 may include copper, aluminum, etc., for example. The second bonding pad pattern 364 may include the same material as the first bonding pad pattern 130 formed on the first substrate.

The top surface of the second bonding pad pattern 364 may be located on the same plane as the top surface of the second bonding film 362 and may be exposed to the outside. In example embodiments, the second bonding pad pattern 364 may be formed through a dual damascene process or a single damascene process.

The second bonding pad pattern 364 may be formed in an area where the final bonding pad structure is to be formed. The second bonding pad pattern 364 may be provided as part of the bonding pad structure. The second bonding pad pattern 364 may be formed to have a width narrower than the target width of the bonding pad structure. The first bonding pad pattern 130 on the first substrate 100 and the second bonding pad pattern 364 on the second substrate 200 may be formed into one bonding pad structure through a subsequent process.

One sidewall of the second bonding pad pattern 364 may be formed at a position corresponding to one sidewall of the first bonding pad pattern 130 formed on the first substrate 100. That is, in a subsequent bonding process, one sidewall of the second bonding pad pattern 364 may be vertically aligned with one sidewall of the first bonding pad pattern 130 formed on the first substrate 100.

Through a subsequent process, one sidewall of the second bonding pad pattern 364 and one sidewall of the first bonding pad pattern 130 may be bonded to each other to form a single bonding pad structure. Accordingly, the sum of the widths of the first bonding pad pattern 130 and the width of the second bonding pad pattern 364 may be equal to the target width of the bonding pad structure.

Referring to FIG. 10, a third opening 366 is formed by etching a portion of the second bonding film 362 and the sixth interlayer insulating film 360 so that one sidewall of the second bonding pad pattern 364 is exposed. do.

The third opening 366 may be formed at a position corresponding to the first bonding pad pattern 130 so that the first bonding pad pattern 130 formed on the first substrate 100 can be accommodated. That is, in the subsequent bonding process, as the first bonding pad pattern 130 is inserted into the third opening 366, one side wall of the first bonding pad pattern 130 and the second bonding pad pattern 364 ) may be in contact with each other laterally. Additionally, one sidewall of the first bonding pad pattern 130 and one sidewall of the second bonding pad pattern 364 may be bonded to each other.

To allow the first bonding pad pattern 130 to be sufficiently inserted into the third opening 366, the internal width of the third opening 366 is approximately the same as the width of the first bonding pad pattern 130. It may be formed or may be formed slightly wider than the width of the first bonding pad pattern 130. Additionally, when the first bonding pad pattern 130 is inserted into the third opening 366, the first bonding film 122 and the second bonding film 362 must be in contact with each other. That is, in order to prevent the first bonding film 122 and the second bonding film 362 from being separated from each other, the first bonding pad pattern 130 can be completely inserted into the third opening 366. It can have depth. Accordingly, the depth of the third opening 366 may be the same as or deeper than the height from the surface of the first bonding film 122 formed on the first substrate to the top surface of the first bonding pad pattern 130.

Meanwhile, a step may occur at the top of the first substrate 100 and/or at the bottom of the second substrate 200 due to process deviation. In this case, the height of the first bonding pad pattern 130 protruding from the top of the first substrate 100 may vary depending on the area of the first substrate 100. Additionally, the height of the second bonding pad pattern 364 formed at the bottom of the second substrate 200 may vary depending on the area of the second substrate 200. Therefore, in order to secure a storage margin for the first bonding pad pattern 130 inside the third opening 366, the depth of the third opening 366 is greater than the height of the second bonding pad pattern 364. It can be formed larger.

Referring to FIGS. 11 and 12 , the second substrate 200 is rotated 180 degrees. Afterwards, the first and second substrates 100 and 200 are aligned and brought into contact so that the first bonding pad pattern 130 is inserted into the third opening 366, respectively. At this time, the second bonding film 362 formed on the second substrate 200 is adhered to the first bonding film 122 formed on the first substrate 100.

Through the above process, the first substrate 100 and the second substrate 200 can be bonded to each other to form one body. At this time, the top and bottom of the structures formed on the second substrate 200 may be reversed, and the top and bottom relationship will be explained based on the changed state.

Since the first bonding film 122 and the second bonding film 362 are formed of substantially the same material, they can form one bonding film 370. The bonding film 370 may be positioned between the lower interlayer insulating film 120 and the sixth interlayer insulating film 360.

At this time, one sidewall of the first bonding pad pattern 130 inserted into the third opening 366 may be adhered to one sidewall of the second bonding pad pattern 364. Accordingly, one bonding pad structure 368 including the first and second bonding pad patterns 130 and 364 may be formed. The bonding pad structure 368 may include an adhesive interface between the first and second bonding pad patterns 130 and 364. In the bonding pad structure 368, an air gap 372 may be included between the surface of the third opening 366 and the first bonding pad pattern 130. In an exemplary embodiment, in the bonding pad structure 368, an air gap 372 may be included between the surface of the third opening 366 and the upper surface of the first bonding pad pattern 130.

13 to 15 show the top of the first substrate 100 and the second substrate 200 according to the step generated at the top of the first substrate 100 and/or the bottom of the second substrate 200. Indicates the contact form at the bottom.

In the adhesion process, the sidewall of the first bonding pad pattern 130 and the second bonding pad pattern 364 are formed according to the step of the uppermost part of the first substrate 100 and/or the lowermost part of the second substrate 200. The contact area of the side wall may be different.

As an example, when there is almost no step at the top of the first substrate 100 and almost no step at the bottom of the second substrate 200, the first and second bonding pad patterns 130 and 364 each have a target shape. It can be formed to have any height. Therefore, as shown in FIG. 13, the entire sidewall of the first bonding pad pattern 130 and the entire sidewall of the second bonding pad pattern 364 may be adhered to each other. In this case, the upper surface of the bonding pad structure 368 may not have a step (i.e., a difference in height of the upper surface) at the boundary of the first and second bonding pad patterns 130 and 364. An air gap 372 may be formed between the upper surface of the first bonding pad pattern 130 and the surface of the third opening 366.

For example, the height of the first bonding pad pattern 130 may be reduced as the step at the top of the first substrate 100 is lowered. In this case, as shown in FIG. 14, one sidewall of the first bonding pad pattern 130 and a portion of one sidewall of the second bonding pad pattern 364 may be adhered to each other. The upper surface of the bonding pad structure 368 may have a step at the boundary of the first and second bonding pad patterns 130 and 364. On the top surface of the bonding pad structure 368, the top surface of the second bonding pad pattern 364 may be higher than the top surface of the first bonding pad pattern 130. Additionally, an air gap 372 may be formed between the upper surface of the first bonding pad pattern 130 and the surface of the third opening 366.

For example, the height of the second bonding pad pattern 364 may be reduced by lowering the step at the bottom of the second substrate 200. In this case, as shown in FIG. 15, a portion of one sidewall of the first bonding pad pattern 130 and one sidewall of the second bonding pad pattern may be adhered to each other. The upper surface of the bonding pad structure 368 may have a step at the boundary of the first and second bonding pad patterns 130 and 364. On the top surface of the bonding pad structure 368, the top surface of the second bonding pad pattern 364 may be lower than the top surface of the first bonding pad pattern 130. In this case, the first bonding pad An air gap 372 may be formed between the upper surface of the pattern 130 and the surface of the third opening 366.

13 to 15, the top of the first substrate 100 and the second substrate ( The contact form at the bottom of 200) may vary. However, even if a step occurs at the top of the first substrate 100 and/or the bottom of the second substrate 200, at least a portion of one side wall of the first bonding pad pattern 130 and the second bonding pad pattern At least a portion of one side wall of 364 may be in direct contact. Therefore, the first and second bonding pad patterns 130 and 364 may be electrically connected. Accordingly, defects in which the first and second bonding pad patterns 130 and 364 are not in contact and are not electrically connected can be reduced.

Referring to FIG. 16, the second substrate 200 is removed.

In an exemplary embodiment, the process of removing the second substrate 200 may include a grinding process and a chemical mechanical polishing process.

When the second substrate 200 is removed, the base layer pattern 201a, the first interlayer insulating layer 240, and the first contact plug 302 may be exposed at the top of the first substrate 100.

Afterwards, an upper interlayer insulating film 410 is formed to cover the first interlayer insulating film 240, the base film pattern 201a, and the first contact plug 302. An upper contact plug 412 is formed through the upper interlayer insulating film 410 and connected to the first contact plug 302.

After this, although not shown, upper wirings may be further formed on the upper contact plug 412.

By performing the above processes, a bonded vertical semiconductor device can be manufactured.

As described above, the bonded vertical semiconductor device can be electrically connected by having the sidewalls of the first and second bonding pad patterns 130 and 364 contact each other, so that the first and second bonding pad patterns 130 , 364) are not in contact, so electrical defects that occur can be reduced.

Meanwhile, the bonded vertical semiconductor device manufactured through the above-described processes may have the following structural characteristics.

Structural features of the bonded vertical semiconductor device will be described with reference to FIG. 16.

Referring to FIG. 16, the bonded vertical semiconductor device has a lower circuit pattern 110 on a first substrate 100, and a lower interlayer insulating film 120 covering the lower circuit pattern 110.

A first bonding pad pattern 130 may be provided on the lower interlayer insulating film 120. The first bonding pad pattern 130 may have an upper surface that protrudes from the upper surface of the lower interlayer insulating film 120 . The first bonding pad pattern 130 may include metal. The first bonding pad pattern 130 may include copper or aluminum, for example.

A pattern structure 230a may be provided on the base film pattern 201a disposed to be spaced apart from the first substrate 100. The pattern structure may be formed on the lower interlayer insulating film. The pattern structure includes a pattern structure 230a in which first insulating patterns 220 and gate electrodes 304 are alternately and repeatedly stacked. The edge of the pattern structure 230a may have an upside-down step shape.

Interlayer insulating films 240, 310, 330, 340, 350, and 360 may be provided on the lower interlayer insulating film 120 to cover the pattern structure 230a. In an exemplary embodiment, as shown, first to sixth interlayer insulating films 240, 310, 330, 340, 350, and 360 may be provided in the order of distance from the first substrate. The sixth interlayer insulating film 360 may be disposed closest to the first substrate 100 .

A second bonding pad pattern 364 may be provided under the sixth interlayer insulating film 360. The second bonding pad pattern 364 may include metal. The second bonding pad pattern 364 may include copper or aluminum, for example. In an exemplary embodiment, the first bonding pad pattern and the second bonding pad pattern may include the same metal material.

One sidewall of the first bonding pad pattern 130 may be vertically aligned with one sidewall of the second bonding pad pattern 364.

An opening may be provided on the lowermost surface of the sixth interlayer insulating film 360. The second bonding pad pattern 364 may be exposed on one side wall of the opening. The opening may be formed to allow the first bonding pad pattern 130 to be inserted.

The lower interlayer insulating film 120 and the interlayer insulating film (eg, a sixth interlayer insulating film) may be bonded to each other. In addition, the first bonding pad pattern 130 is inserted into the opening, and one side wall of the second bonding pad pattern 364 is in contact with one side wall of the first bonding pad pattern 130 to be bonded. You can have An air gap 372 may be included between the first bonding pad pattern 130 and the surface of the opening.

A structure where the first and second bonding pad patterns 130 and 364 are joined may be provided as a bonding pad structure. In the bonding pad structure, the upper surface of the boundary between the first and second bonding pad patterns 130 and 364 may have a step.

A bonding film 370 may be further provided between the lower interlayer insulating film 120 and the sixth interlayer insulating film 360 located at the bottom. The bonding film 370 is interposed between the lower interlayer insulating film 120 and the sixth interlayer insulating film 360 to bond the lower interlayer insulating film 120 and the sixth interlayer insulating film 360 to each other. The bonding film 370 may include SiCN, for example.

The bonding film 370 may include a first bonding film 122 and a second bonding film 362. The first bonding film 122 may cover the bottom of the second bonding pad pattern 364 close to the first substrate 100 .

Channel holes may be provided that penetrate the pattern structure 230a in a vertical direction. A channel structure 290a including a data storage pattern 281, a channel 284, a first buried insulating pattern 286, and a capping pattern 288 may be provided in the channel holes. The data storage pattern 281 may have a structure in which a first blocking dielectric layer pattern, a charge storage layer pattern, and a tunnel insulating layer pattern are stacked. The channel 284 may have a cylindrical shape formed along the surface of the channel holes. The buried insulating pattern may be formed on the channel 284 to fill most of the channel hole. The capping pattern 288 may be disposed on the bottom of the channel structure 290a and electrically connected to the channel 284.

A first support film pattern 216, a channel connection pattern 312, and a base film pattern 201a may be formed on the top of the pattern structure 230a. The channel connection pattern 312 may electrically connect lower portions of the channels 284 to each other and electrically connect the channels 284 and the base layer pattern 201a to each other.

Wires 332, 342, and 352 electrically connected to the channel structure 290a may be included in the interlayer insulating films 240, 310, 330, 340, 350, and 360. In an exemplary embodiment, as shown, first to third wirings 332, 342, and 352 may be provided. In an exemplary embodiment, the wires are connected to the capping pattern 288 disposed on the bottom of the channel structure 290a, and thus may be electrically connected to the channel 284.

A first contact plug 302 penetrating the interlayer insulating films 240, 310, 330, 340, 350, and 360 may be further included. The first contact plug 302 may be arranged to be spaced apart from the pattern structure 230a. Accordingly, the first contact plug 302 may not penetrate the pattern structure 230a. The first contact plug 302 may be electrically connected to the wires 332, 342, and 352.

An upper interlayer insulating film 410 may be further provided to cover the first interlayer insulating film 240, the base film pattern 201a, and the first contact plug 302. An upper contact plug 412 passing through the upper interlayer insulating film 410 and connected to the first contact plug 302 may be further provided. Upper wires may be further provided on the upper contact plug 412.

17 to 20 are cross-sectional views for explaining a method of manufacturing a bonded semiconductor device according to example embodiments.

The manufacturing method described below except that an opening is formed in one side wall of the first bonding pad pattern formed on the first substrate, and the second bonding pad pattern formed on the second substrate has a protruding shape. This is the same as the manufacturing method of the bonded semiconductor device described with reference to FIGS. 1 to 16.

Referring to FIG. 17, the process described with reference to FIG. 1 is performed in the same manner. Afterwards, a portion of the first bonding film 122 and the lower interlayer insulating film 120 is etched to form a first opening 126 at a portion for forming a first bonding pad pattern. The wiring of the lower circuit pattern 110 may be exposed on the bottom of the first opening 126. A first bonding pad pattern 130 is formed to fill the inside of the first opening 126.

Referring to FIG. 18, a second opening 400 is formed by etching a portion of the first bonding film 322 and the lower interlayer insulating film 120 so that one sidewall of the first bonding pad pattern 130 is exposed. .

The second opening 400 may be formed at a position corresponding to the second bonding pad pattern so that the second bonding pad pattern formed on the second substrate 200 can be accommodated in a subsequent process.

Continuing, memory structures and metal wires are formed on the second substrate 200 through the processes described with reference to FIGS. 2 to 8 .

Referring to FIG. 19, a sixth interlayer insulating film 360, which is an uppermost interlayer insulating film, is formed on the fifth interlayer insulating film 350 and the third wiring 352. A contact 361 in contact with the third wirings 352 is formed on the sixth interlayer insulating film 360.

A second bonding layer 362 is formed on the sixth interlayer insulating layer 360. An upper sacrificial layer 402 is formed on the bonding layer.

A portion of the second bonding layer 362 and the upper sacrificial layer 402 is etched to form a third opening 404 at a portion for forming a second bonding pad pattern.

A second bonding pad pattern 364 is formed to fill the inside of the third opening 404. A lower portion of the second bonding pad pattern 364 may be in contact with a contact 361 that is in contact with the third wires 352 .

The second bonding pad pattern 364 may be formed at a position corresponding to the second opening 400 formed in the first substrate 100. The first bonding pad pattern 130 on the first substrate 100 and the second bonding pad pattern 364 on the second substrate 200 may be formed into one bonding pad structure through a subsequent process.

Referring to FIG. 20, the upper sacrificial layer 402 is removed. Accordingly, the second bonding pad pattern 364 may protrude from the second bonding film 362.

The second substrate 200 is rotated 180 degrees. Afterwards, the first and second substrates 100 and 200 are aligned and brought into contact so that the second bonding pad pattern 164 is inserted into the second opening 400, respectively. At this time, the second bonding film 362 formed on the second substrate 200 is adhered to the first bonding film 122 formed on the first substrate 100.

Accordingly, one sidewall of the first bonding pad pattern 130 inserted into the second opening 400 may be adhered to one sidewall of the second bonding pad pattern 364. Accordingly, one bonding pad structure 368 including the first and second bonding pad patterns 130 and 364 may be formed.

In the bonding pad structure 368, an air gap 372 may be included between the surface of the second opening 400 and the second bonding pad pattern 364. In an exemplary embodiment, in the bonding pad structure 368, an air gap 372 may be included between the surface of the second opening 400 and the bottom of the second bonding pad pattern 364.

Continuing, the process described with reference to FIG. 16 is performed. Accordingly, the bonded vertical semiconductor device shown in FIG. 20 can be manufactured.

As described above, the bonded vertical semiconductor device can be electrically connected by having the sidewalls of the first and second bonding pad patterns 130 and 364 contact each other, so that the first and second bonding pad patterns 130 , 364) are not in contact, so electrical defects that occur can be reduced.

As described above, the present invention has been described with reference to preferred embodiments, but those skilled in the art can make various modifications and modifications to the present invention without departing from the spirit and scope of the present invention as set forth in the patent claims. You will understand that you can change it.

100: substrate 110: lower circuit pattern
120: lower interlayer insulating film 122: first bonding film
124: upper sacrificial layer 130: first bonding pad pattern
200: second substrate 230: mold structure
230a: pattern structure 290a: channel structure
302: first contact plug 304: gate electrode
320: second contact plug 362: second bonding film
332, 342, 352: 1st wiring, 2nd wiring, 3rd wiring
364: second bonding pad pattern 368: bonding pad structure
372: air gap 270: bonding film

Claims (10)

First circuit patterns formed on a first substrate;
a lower interlayer insulating film covering the first circuit patterns;
a first bonding pad pattern provided on the lower interlayer insulating film and having an upper surface protruding from the upper surface of the lower interlayer insulating film;
second circuit patterns formed on the base film pattern spaced apart from the first substrate;
an interlayer insulating film covering the second circuit patterns on the lower interlayer insulating film, a lowermost part of which is disposed to face the lower interlayer insulating film, and an opening formed in the lowermost part; and
A second bonding pad pattern is provided inside the lower part of the interlayer insulating film and has one side wall exposed by the opening,
The first bonding pad pattern has a shape inserted into the opening, and a sidewall of the second bonding pad pattern is in contact with a sidewall of the first bonding pad pattern. The bonded semiconductor device of claim 1, wherein the first bonding pad pattern and the second bonding pad pattern include the same metal material. The bonded semiconductor device of claim 1, wherein an air gap is included between the first bonding pad pattern and the surface of the opening. The method of claim 1, wherein the structure where the first and second bonding pad patterns are bonded is provided as a bonding pad structure, and an upper surface of a boundary portion of the first and second bonding pad patterns in the bonding pad structure has a step. Bonding type semiconductor device. The bonded semiconductor device of claim 1, wherein a bonding film is provided between the upper surface of the lower interlayer insulating film and the lowermost surface of the interlayer insulating film. The bonded semiconductor device of claim 5, wherein a portion of the bonding film covers a bottom surface of the second bonding pad pattern close to the first substrate. The bonded semiconductor device of claim 5, wherein the bonding film includes SiCN material. First circuit patterns formed on a first substrate;
a lower interlayer insulating film covering the first circuit patterns;
a first bonding pad pattern provided on the lower interlayer insulating layer;
second circuit patterns formed on the base film pattern spaced apart from the first substrate;
an interlayer insulating film that covers the second circuit patterns on the lower interlayer insulating film, and whose lowermost part is disposed to face the lower interlayer insulating film;
a second bonding pad pattern provided below the interlayer insulating film; and
A bonding film provided between the upper surface of the lower interlayer insulating film and the lowermost surface of the interlayer insulating film to bond the lower interlayer insulating film and the interlayer insulating film,
A bonded semiconductor device having a structure in which one sidewall of the first bonding pad pattern and one sidewall of the second bonding pad pattern are in contact with each other and bonded to each other. The bonded semiconductor device of claim 8, wherein the first bonding pad pattern is inserted into an opening of the interlayer insulating film, and an air gap is included between the first bonding pad pattern and a surface of the opening. The bonded semiconductor device of claim 8, wherein the second bonding pad pattern is inserted into the opening of the lower interlayer insulating film, and an air gap is included between the second bonding pad pattern and a surface of the opening.