KR20230143067A - Nonvolatile memory device and Method for Manufacturing the same - Google Patents

Abstract

A non-volatile memory device is provided. A non-volatile memory device according to embodiments of the present disclosure includes a first semiconductor structure; a second semiconductor structure vertically stacked on the first semiconductor structure; and a junction interface between the first semiconductor structure and the second semiconductor structure, wherein the first semiconductor structure includes a first junction insulator, a plurality of first junction lines vertically penetrating the first junction insulator, and the first junction insulator. a first bonding layer vertically penetrating the first bonding insulator and including at least one first dummy bonding line horizontally parallel to the plurality of first bonding lines; a first wiring layer including a first pad insulator on which a plurality of first wiring pads are disposed and vertically stacked on the first bonding layer; and a first liner film between the first bonding layer and the first wiring layer, wherein the plurality of first bonding lines vertically penetrate the first wiring layer and the first liner film, and the plurality of first bonding lines vertically penetrate the first wiring layer and the first liner film. A lower surface of the bonding line is in contact with the plurality of first wiring pads, the at least one first dummy bonding line vertically penetrates the first liner film, and the second semiconductor structure includes a second bonding insulator, the first 2. It includes a plurality of second bonding lines vertically penetrating the second bonding insulator and at least one second dummy bonding line vertically penetrating the second bonding insulator and horizontally parallel to the plurality of second bonding lines, a second bonding layer opposite the first bonding layer; a second wiring layer including a second pad insulator on which a plurality of second wiring pads are disposed and vertically stacked on the second bonding layer; and a second liner film between the second bonding layer and the second wiring layer, wherein the plurality of second bonding lines vertically penetrate the second wiring layer and the second liner film, and the plurality of second bonding lines vertically penetrate the second wiring layer and the second liner film. The upper surface of the plurality of bonding lines contacts the plurality of second wiring pads, the at least one second dummy bonding line vertically penetrates the second liner film, and the upper surface of the plurality of first bonding lines is at the bonding interface. It contacts the lower surface of the plurality of second bonding lines, and the upper surface of the at least one first dummy bonding line contacts the lower surface of the at least one second dummy bonding line at the bonding interface.

Description

Nonvolatile memory device and method for manufacturing the same}

The present disclosure relates to non-volatile memory devices and memory systems including the same. More specifically, the present disclosure relates to a three-dimensional non-volatile memory device including two structures bonded to each other and a memory system including the same.

Consumers demand non-volatile memory devices with high performance, small size, and low price. Therefore, in order to achieve a non-volatile memory device with high integration, a three-dimensional non-volatile memory device in which a plurality of memory cells are arranged vertically has been proposed. In addition, a first structure is formed by forming a part of the non-volatile memory element on a first substrate, a second structure is formed by forming the remaining part of the non-volatile memory element on a second substrate, and the first structure is formed by forming a first structure. A non-volatile memory device with a reduced surface area formed by bonding to a two-structure structure has been proposed.

The problem that the present disclosure aims to solve is to provide a non-volatile memory device with reduced resistance and improved unbonding defects, and a method for manufacturing the same.

A non-volatile memory device according to embodiments of the present disclosure includes a first semiconductor structure; a second semiconductor structure vertically stacked on the first semiconductor structure; and a junction interface between the first semiconductor structure and the second semiconductor structure, wherein the first semiconductor structure includes a first junction insulator, a plurality of first junction lines vertically penetrating the first junction insulator, and the first junction insulator. a first bonding layer vertically penetrating the first bonding insulator and including at least one first dummy bonding line horizontally parallel to the plurality of first bonding lines; a first wiring layer including a first pad insulator on which a plurality of first wiring pads are disposed and vertically stacked on the first bonding layer; and a first liner film between the first bonding layer and the first wiring layer, wherein the plurality of first bonding lines vertically penetrate the first wiring layer and the first liner film, and the plurality of first bonding lines vertically penetrate the first wiring layer and the first liner film. A lower surface of the bonding line is in contact with the plurality of first wiring pads, the at least one first dummy bonding line vertically penetrates the first liner film, and the second semiconductor structure includes a second bonding insulator, the first 2. It includes a plurality of second bonding lines vertically penetrating the second bonding insulator and at least one second dummy bonding line vertically penetrating the second bonding insulator and horizontally parallel to the plurality of second bonding lines, a second bonding layer opposite the first bonding layer; a second wiring layer including a second pad insulator on which a plurality of second wiring pads are disposed and vertically stacked on the second bonding layer; and a second liner film between the second bonding layer and the second wiring layer, wherein the plurality of second bonding lines vertically penetrate the second wiring layer and the second liner film, and the plurality of second bonding lines vertically penetrate the second wiring layer and the second liner film. The upper surface of the plurality of bonding lines contacts the plurality of second wiring pads, the at least one second dummy bonding line vertically penetrates the second liner film, and the upper surface of the plurality of first bonding lines is at the bonding interface. It contacts the lower surface of the plurality of second bonding lines, and the upper surface of the at least one first dummy bonding line contacts the lower surface of the at least one second dummy bonding line at the bonding interface.

Through the single damascene process, the first and second bonding lines are directly bonded instead of indirectly through other lines or vias, thereby increasing the area of the electrical contact. This has the effect of reducing resistance by increasing the wiring area. Additionally, the volume of conductors such as Cu that make up the electrical contact increases, which can improve the possibility of unbonding defects in the process of bonding the first and second semiconductor structures.

1 is a block diagram of a non-volatile memory device according to exemplary embodiments of the present invention.
2 is a schematic perspective view of a non-volatile memory device according to exemplary embodiments of the present invention.
3 is an equivalent circuit diagram of a memory cell array of a non-volatile memory device according to example embodiments of the present invention.
4 is a cross-sectional view of a non-volatile memory device according to exemplary embodiments of the present invention.
5 to 12 are cross-sectional views of portions of non-volatile memory devices according to exemplary embodiments of the present invention.
FIGS. 13A to 13D are cross-sectional views for explaining a method of manufacturing a portion of a non-volatile memory device according to an exemplary embodiment of the present invention shown in FIG. 5 .
14A to 14D are cross-sectional views illustrating a method of manufacturing a portion of a non-volatile memory device according to exemplary embodiments of the present invention.
Figure 15 is a diagram schematically showing a memory system including non-volatile memory elements according to example embodiments of the present invention.
Figure 16 is a perspective view schematically showing a memory system including non-volatile memory elements according to example embodiments of the present invention.
17 is a cross-sectional view schematically showing a semiconductor package according to example embodiments of the present invention.

1 is a block diagram of a non-volatile memory device according to exemplary embodiments of the present invention.

Referring to FIG. 1 , the non-volatile memory device 10 may include a memory cell array 20 and a peripheral circuit 30. The memory cell array 20 includes a plurality of memory cell blocks BLK1, BLK2, ..., BLKn. Each of the plurality of memory cell blocks (BLK1, BLK2, ..., BLKn) may include a plurality of memory cells. The memory cell blocks (BLK1, BLK2, ..., BLKn) are connected to the peripheral circuit 30 through a bit line (BL), word line (WL), string select line (SSL), and ground select line (GSL). You can.

The peripheral circuit 30 may include a row decoder 32, a page buffer 34, a data input/output circuit 36, and control logic 38. Although not shown in FIG. 1, the peripheral circuit 30 may further include an input/output interface, column logic, a voltage generator, a pre-decoder, a temperature sensor, a command decoder, an address decoder, an amplifier circuit, etc.

The memory cell array 20 may be connected to the page buffer 34 through a bit line (BL), and to the row decoder 32 through a word line (WL), a string select line (SSL), and a ground select line (GSL). ) can be connected to. In the memory cell array 20, the plurality of memory cells included in the plurality of memory cell blocks BLK1, BLK2, ..., BLKn may each be a flash memory cell. The memory cell array 20 may include a three-dimensional memory cell array. The three-dimensional memory cell array may include a plurality of NAND strings, and each NAND string may include a plurality of memory cells connected to a plurality of word lines (WL) vertically stacked on a substrate.

The peripheral circuit 30 may receive an address (ADDR), a command (CMD), and a control signal (CTRL) from outside the non-volatile memory element 10, and may be connected to a device external to the non-volatile memory element 10. You can send and receive data (DATA).

The row decoder 32 can select at least one of a plurality of memory cell blocks (BLK1, BLK2, ..., BLKn) in response to an external address (ADDR), and the word line (WL) of the selected memory cell block , string select line (SSL), and ground select line (GSL) can be selected. The row decoder 32 may transmit a voltage for performing a memory operation to the word line (WL) of the selected memory cell block.

The page buffer 34 may be connected to the memory cell array 20 through a bit line BL. The page buffer 34 operates as a write driver during a program operation to apply a voltage to the bit line (BL) according to the data (DATA) to be stored in the memory cell array 20, and operates as a sense amplifier during a read operation. It is possible to detect data (DATA) stored in the memory cell array 20 by operating as . The page buffer 34 may operate according to a control signal (PCTL) provided from the control logic 38.

The data input/output circuit 36 may be connected to the page buffer 34 through data lines DLs. The data input/output circuit 36 receives data (DATA) from a memory controller (not shown) during a program operation, and stores the program data (DATA) in a page buffer ( 34) can be provided. The data input/output circuit 36 may provide read data DATA stored in the page buffer 34 to the memory controller based on the column address C_ADDR provided from the control logic 38 during a read operation.

The data input/output circuit 36 may transmit an input address or command to the control logic 38 or the row decoder 32. The peripheral circuit 30 may further include an Electro Static Discharge (ESD) circuit and a pull-up/pull-down driver.

The control logic 38 may receive a command (CMD) and a control signal (CTRL) from the memory controller. The control logic 38 may provide a row address (R_ADDR) to the row decoder 32 and a column address (C_ADDR) to the data input/output circuit 36. The control logic 38 may generate various internal control signals used within the non-volatile memory device 10 in response to the control signal CTRL. For example, the control logic 38 may adjust the voltage level provided to the word line (WL) and the bit line (BL) when performing a memory operation such as a program operation or an erase operation.

2 is a schematic perspective view of a non-volatile memory device according to exemplary embodiments of the present invention.

Referring to FIG. 2 , the non-volatile memory device 10 includes a cell array structure (CS) and a peripheral circuit structure (PS) that overlap each other in the vertical direction (Z direction). The cell array structure CS may include the memory cell array 20 described with reference to FIG. 1 . The peripheral circuit structure PS may include the peripheral circuit 30 described with reference to FIG. 1 .

The cell array structure CS may include a plurality of memory cell blocks BLK1, BLK2, ..., BLKn. Each of the plurality of memory cell blocks (BLK1, BLK2, ..., BLKn) may include memory cells arranged three-dimensionally.

3 is an equivalent circuit diagram of a memory cell array of a non-volatile memory device according to example embodiments of the present invention.

Referring to FIG. 3, the memory cell array (MCA) may include a plurality of memory cell strings (MS). The memory cell array (MCA) includes a plurality of bit lines (BL: BL1, BL2, ..., BLm), a plurality of word lines (WL: WL1, WL2, ..., WLn-1, WLn), and at least one string selection line ( SSL), at least one ground select line (GSL), and a common source line (CSL). A plurality of memory cell strings (MS) may be formed between the plurality of bit lines (BL: BL1, BL2, ..., BLm) and the common source line (CSL). Although FIG. 3 illustrates a case in which each of the plurality of memory cell strings MS includes two string select lines SSL, the technical idea of the present invention is not limited thereto. For example, each of the plurality of memory cell strings MS may include one string select line SSL.

Each of the plurality of memory cell strings (MS) may include a string select transistor (SST), a ground select transistor (GST), and a plurality of memory cell transistors (MC1, MC2, ..., MCn-1, MCn). The drain area of the string select transistor (SST) may be connected to the bit lines (BL: BL1, BL2, ..., BLm), and the source area of the ground select transistor (GST) may be connected to the common source line (CSL). The common source line (CSL) may be an area where the source regions of a plurality of ground selection transistors (GST) are commonly connected.

The string select transistor (SST) may be connected to the string select line (SSL), and the ground select transistor (GST) may be connected to the ground select line (GSL). A plurality of memory cell transistors (MC1, MC2, ..., MCn-1, MCn) may be connected to a plurality of word lines (WL: WL1, WL2, ..., WLn-1, WLn), respectively.

Figure 4 is a cross-sectional view of a non-volatile memory device 100 according to exemplary embodiments of the present invention.

Referring to FIG. 4 , the non-volatile memory device 100 includes a first structure (S1) and a second structure (S2) bonded to the first structure (S1). The first structure (S1) is connected to the second structure (S2) so that the plurality of first bonding pads (BP1) of the first structure (S1) and the plurality of second bonding pads (BP2) of the second structure (S2) are in contact with each other. can be contacted. In some embodiments, when the first bonding pad BP1 includes copper (Cu) and the second bonding pad BP2 includes copper (Cu), the first structure S1 is formed by Cu-Cu bonding. may be bonded to the second structure (S2).

The first structure S1 includes a first substrate 110, a peripheral circuit (PC) on the first substrate 110, a first insulating structure (IL1) on the first substrate 110 and the peripheral circuit (PC), and a first insulating structure (IL1) on the first substrate 110 and the peripheral circuit (PC). It may include a plurality of first bonding pads BP1 on the insulating structure IL1, and a first interconnect structure IC1 in the first insulating structure IL1.

The first substrate 110 may include a semiconductor material such as a group IV semiconductor material, a group III-V semiconductor material, or a group II-VI semiconductor material. The Group IV semiconductor material may include, for example, silicon (Si), germanium (Ge), or silicon (Si)-germanium (Ge). The III-V semiconductor materials include, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimony (InSb), or indium gallium arsenide (InGaAs). can do. The group II-VI semiconductor material may include, for example, zinc telluride (ZnTe) or cadmium sulfide (CdS). The first substrate 110 may be a bulk wafer or an epitaxial layer.

The peripheral circuit (PC) may be disposed on the first substrate 110 . The peripheral circuit (PC) may include a plurality of transistors 120. For example, the transistor 120 includes a gate electrode 122 on the first substrate 110, a gate insulating layer 121 between the gate electrode 122 and the first substrate 110, and a gate electrode 121 on the side of the gate electrode 122. It may include a gate spacer 123 and source/drains 124 and 125 on both sides of the gate electrode 122.

The first insulating structure IL1 may cover the first substrate 110 and the peripheral circuit (PC). Although not shown in FIG. 4 , the first insulating structure IL1 may include a plurality of insulating layers stacked on top of each other. The first insulating structure IL1 may include an insulating material that may include, for example, silicon oxide, silicon nitride, a low-k material, or a combination thereof. The low-dielectric material is a material having a lower dielectric constant than silicon oxide, such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), organosilicate glass (OSG), spin-on-glass (SOG), It may include spin-on-polymer, or a combination thereof.

The first bonding pad BP1 may be disposed on the first insulating structure IL1. In some embodiments, the top surface of the first bonding pad BP1 may be coplanar with the top surface of the first insulating structure IL1. That is, the first bonding pad BP1 may not protrude from the top surface of the first insulating structure IL1. The first bonding pad BP1 may include copper (Cu), gold (Au), silver (Ag), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or a combination thereof. It may contain conductive materials.

The first interconnect structure IC1 may be disposed within the first insulating structure IL1. The first interconnect structure IC1 may be connected to the peripheral circuit PC and a plurality of first bonding pads BP1. The first interconnect structure IC1 may connect the peripheral circuit PC to a plurality of first bonding pads BP1. The first interconnect structure IC1 may further connect the plurality of transistors 120 in the peripheral circuit PC. The first interconnect structure IC1 may include a plurality of lines, vias connecting the plurality of lines, and plugs connecting the plurality of lines and the plurality of transistors 120. The first interconnect structure IC1 may include a conductive material such as copper (Cu), aluminum (Al), tungsten (W), silver (Ag), gold (Au), or a combination thereof.

The second structure (S2) includes a low-resistance conductive layer 170, a common source line layer 130 on the low-resistance conductive layer 170, a stacked structure (SS) on the common source line layer 130, and a stacked structure (SS). A plurality of channel structures 140 penetrating the cell region CELL, a plurality of dummy channel structures 180 penetrating the step region EXT of the stacked structure SS, and a second insulating structure on the stacked structure SS. (IL2), a plurality of second bonding pads (BP2) on the second insulating structure (IL2), and a second interconnect structure (IC2) in the second insulating structure (IL2).

In some embodiments, the second structure S2 may further include a lower conductive layer 150 between the common source line layer 130 and the stacked structure SS. In some embodiments, the second structure S2 may further include a lower support layer 160 between the lower conductive layer 150 and the laminated structure SS. In some embodiments, the second structure S2 includes a second insulating structure IL2 and a third insulating structure IL3 on the low-resistance conductive layer 170, and an input/output pad penetrating the third insulating structure IL3 ( 190) may further be included.

The common source line layer 130 may include a semiconductor material, such as a Group IV semiconductor material, a Group III-V semiconductor material, or a Group II-VI semiconductor material. Common source line layer 130 may include polysilicon, for example. Low-resistance conductive layer 170 may contact common source line layer 130 and function as part of the common source line. The material constituting the low-resistance conductive layer 170 may have a lower resistivity than the material constituting the common source line layer 130. For example, common source line layer 130 may include polysilicon, while low-resistance conductive layer 170 may include metal. The metal may include, for example, copper (Cu), aluminum (Al), tungsten (W), silver (Ag), gold (Au), or a combination thereof. The low-resistance conductive layer 170 may reduce common source line noise by reducing the net resistance of the common source line.

The stacked structure SS may be disposed on the common source line layer 130 . The stacked structure SS may include a plurality of gate layers 132a and 132b and a plurality of interlayer insulating layers 131a and 131b alternately stacked on the common source line layer 130. The stacked structure SS may include a first part SSa on the common source line layer 130 and a second part SSb on the first part SSa. The first portion (SSa) of the stacked structure (SS) may include a plurality of first gate layers (132a) and a plurality of first interlayer insulating layers (131a) alternately stacked on the common source line layer (130). there is. The second part (SSb) of the stacked structure (SS) includes a plurality of second gate layers (132b) and a plurality of second interlayer insulating layers (131b) alternately stacked on the first part (SSa) of the stacked structure (SS). ) may include.

The stacked structure SS may include a cell region (CELL) and a step region (EXT). The step area EXT of the stacked structure SS is located on one side of the cell area CELL of the stacked structure SS and may have a step shape. For example, the cell region CELL of the stacked structure SS may have a step shape going down in the +Z direction.

The plurality of gate layers 132a and 132b may include, but are not limited to, tungsten (W), copper (Cu), silver (Ag), gold (Au), aluminum (Al), or a combination thereof. may include. The plurality of interlayer insulating layers 131a and 131b may include an insulating material that may include silicon oxide, silicon nitride, a low dielectric material, or a combination thereof.

Each channel structure 140 may contact the common source line layer 130 through the cell region CELL of the stacked structure SS. In some embodiments, channel structure 140 may further penetrate lower conductive layer 150 and lower support layer 160.

The plurality of dummy channel structures 180 may contact the common source line layer 130 through the step area EXT of the stacked structure SS. The dummy channel structure 180 may further penetrate the lower conductive layer 150 and the lower support layer 160. The dummy channel structure 180 may further penetrate the second portion IL2b and the third portion IL2c of the second insulating structure IL2. The dummy channel structure 180 includes a first dummy channel hole 180Ha and a second insulating structure ( It may be located in the second dummy channel hole 180Hb penetrating the second portion IL2b of IL2).

The dummy channel structure 180 may include an insulating layer 182 on the first dummy channel hole 180Ha and the second dummy channel hole 180Hb, and a conductive layer 181 on the insulating layer 182. The conductive layer 181 may extend within the first dummy channel hole 180Ha and the second dummy channel hole 180Hb and contact the common source line layer 130. The insulating layer 182 may extend between the conductive layer 181 and the step region (EXT) of the stacked structure (SS). The insulating layer 182 may further extend between the conductive layer 181 and the second portion IL2b of the second insulating structure IL2. The insulating layer 182 may further extend between the conductive layer 181 and the third portion IL2c of the second insulating structure IL2. In some embodiments, insulating layer 182 may extend further between conductive layer 181 and lower support layer 160. In some embodiments, insulating layer 182 may extend further between conductive layer 181 and lower conductive layer 150.

Conductive layer 181 may include a conductive material such as a semiconductor material or a metal material. The conductive layer 181 may include, for example, polysilicon, copper (Cu), tungsten (W), aluminum (Al), gold (Au), silver (Au), or a combination thereof. The insulating layer 182 may include, for example, silicon oxide, silicon nitride, a low dielectric material, or a combination thereof.

The dummy channel structure 180 penetrating the step region EXT of the stacked structure SS may serve as a common source line contact for contacting the common source line layer 130. Since the planar area occupied by the common source line contact contacting the common source line layer 130 outside the stacked structure SS is not required, the planar area of the non-volatile memory device 100 can be reduced.

The second insulating structure IL2 may cover the stacked structure SS, the plurality of channel structures 140, and the plurality of dummy channel structures 180. The second insulating structure IL2 may include a plurality of insulating layers. For example, the second insulating structure IL2 may include a first part IL2a, a second part IL2b on the first part IL2a, and a third part IL2c on the second part IL2b. You can. The second insulating structure IL2 may include an insulating material that may include, for example, silicon oxide, silicon nitride, a low dielectric material, or a combination thereof.

A plurality of second bonding pads BP2 may be disposed on the second insulating structure IL2. In some embodiments, the top surface of the second bonding pad BP2 may be coplanar with the bottom surface of the second insulating structure IL2. That is, the second bonding pad BP2 may not protrude from the lower surface of the second insulating structure IL2. The second bonding pad BP2 may include copper (Cu), gold (Au), silver (Ag), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or a combination thereof. It may contain conductive materials.

The second interconnect structure IC2 is disposed in the second insulating structure IL2 and includes a plurality of gate layers 132a and 132b, a plurality of channel structures 140, a dummy channel structure 180, and a plurality of second bonding structures. It can be connected to the pad (BP2). For example, the second interconnect structure IC2 may connect a plurality of gate layers 132a and 132b, a plurality of channel structures 140, and a dummy channel structure 180 to a plurality of second bonding pads BP2. there is. In some embodiments, the second interconnect structure IC2 may be further connected to the input/output pad 190. For example, the second interconnect structure IC2 may connect the input/output pad 190 to the second bonding pad BP2.

The plurality of gate layers 132a and 132b are connected to peripheral circuits through the second interconnect structure IC2, the plurality of second bonding pads BP2, the plurality of first bonding pads BP1, and the first interconnect structure IC1. Can be connected to (PC). In addition, the plurality of channel structures 140 are connected to peripheral circuits through the second interconnect structure IC2, the plurality of second bonding pads BP2, the plurality of first bonding pads BP1, and the first interconnect structure IC1. Can be connected to (PC). In addition, the dummy channel structure 180 is connected to the peripheral circuit (PC) through the second interconnect structure (IC2), the second bonding pad (BP2), the first bonding pad (BP1), and the first interconnect structure (IC1). You can. Additionally, the input/output pad 190 may be connected to the peripheral circuit (PC) through the second interconnect structure (IC2), the second bonding pad (BP2), the first bonding pad (BP1), and the first interconnect structure (IC1). there is.

The second interconnect structure IC2 includes a plurality of lines, vias connecting the plurality of lines, a plurality of gate layers 132a and 132b, a plurality of channel structures 140, a dummy channel structure 28, and a plurality of plugs in contact with the input/output pad 190. The second interconnect structure IC2 may include a conductive material such as copper (Cu), aluminum (Al), tungsten (W), silver (Ag), gold (Au), or a combination thereof.

Lower conductive layer 150 may extend between lower support layer 160 and common source line layer 130. Lower conductive layer 150 may include a conductive material, such as a semiconductor material or a metallic material. The lower conductive layer 150 may include polysilicon, aluminum (Al), tungsten (W), silver (Ag), gold (Au), or a combination thereof. In some embodiments, lower conductive layer 150 may penetrate gate insulating layer 241 and contact channel layer 242, as shown in FIG. 1B.

The lower support layer 160 may extend between the stacked structure SS and the lower conductive layer 150. The lower support layer 160 may include a conductive material, such as a semiconductor material or a metallic material. The lower support layer 160 may include polysilicon, aluminum (Al), tungsten (W), silver (Ag), gold (Au), or a combination thereof. In some embodiments, common source line layer 130, lower conductive layer 150, and lower support layer 160 include polysilicon to form a boundary between common source line layer 130 and lower conductive layer 150. and the boundary between the lower conductive layer 150 and the lower support layer 160 may be unclear or indistinguishable.

The third insulating structure IL3 may be disposed on the second insulating structure IL2 and the low-resistance conductive layer 170. Although not shown in FIG. 4 , the third insulating structure IL3 may include a plurality of insulating layers stacked on top of each other. The third insulating structure IL3 may include an insulating material such as silicon oxide, silicon nitride, a low dielectric material, or a combination thereof.

The input/output pad 190 may penetrate the third insulating structure IL3. The input/output pad 190 may be exposed to the outside of the non-volatile memory device 100. The input/output pad 190 may be connected to a memory controller (not shown) external to the non-volatile memory device 100, as will be described with reference to FIGS. 15 and 16 . The input/output pad 190 may include a conductive material such as copper (Cu), aluminum (Al), tungsten (W), silver (Ag), or gold (Au).

5 to 12 are cross-sectional views of portions of non-volatile memory devices according to exemplary embodiments of the present invention.

Referring to FIG. 5 , the non-volatile memory device 200 is formed by stacking a first semiconductor structure 210 and a second semiconductor structure 230 in the first direction D1. The first direction D1 may be a vertical direction. In some embodiments, the first semiconductor structure 210 may be disposed below the second semiconductor structure 230 and include a substrate. In another embodiment, the second semiconductor structure 230 may be disposed below the first semiconductor structure 210. In some embodiments, the first semiconductor structure 210 may be a peripheral device chip or a memory array device chip, and the first device layer 219 may include a peripheral device or a NAND memory string, respectively, as described in FIG. 1 above. You can. Peripheral elements may include the peripheral circuit (PC) of FIG. 4 . Similarly, the second semiconductor structure 230 may include a second device layer 239. In some embodiments, the second semiconductor structure 230 may be a memory array device chip or a peripheral device chip, and the second device layer 239 may include a NAND memory string or a peripheral device, respectively, as described in FIG. 4 above. You can.

The first semiconductor structure 210 may also include a first wiring layer 216 over the first device layer 219. In some embodiments, the first wiring layer 216 may include a first pad insulator 217 and a plurality of first wiring pads 218. The first wiring pad 218 may include the first interconnect structure IC1 or the second interconnect structure IC2 of FIG. 4 . In some embodiments, the plurality of first interconnection pads 218 are configured to transmit electrical signals across the junction interface 220 and between the first semiconductor structure 210 and the second semiconductor structure 230. A functional MEOL or BEOL wiring pad (e.g., a wiring pad line or via contact) electrically connected to both the first device layer 219 of the semiconductor structure 210 and the second device layer 239 of the second semiconductor structure 230. )am. In some embodiments, only some of the plurality of first wiring pads 218 may be functional MEOL or BEOL wiring pads that are electrically connected to both the first device layer 219 and the second device layer 239. In some embodiments, some of the plurality of first wiring pads 218 are electrically connected to the first device layer 219 of the first semiconductor structure 210 to transmit electrical signals within the first semiconductor structure 210. It may be a functional MEOL or BEOL wiring pad that is connected to but not electrically connected to the second device layer 239 of the second semiconductor structure 230. In some embodiments, some of the plurality of first wiring pads 218 may be dummy wiring pads that are not electrically connected to the first device layer 219 of the first semiconductor structure 210. The plurality of first wiring pads 218 in the first wiring layer 216 may include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof.

The first pad insulator 217 in the first interconnection layer 216 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. there is.

The first semiconductor structure 210 may further include a first bonding layer 211 on the first wiring layer 216. The first bonding layer 211 may include a first bonding insulator 212, a plurality of first bonding lines 213, and a first dummy bonding line 214. The first bonding line 213 may include the first bonding pad BP1 or the second bonding pad BP2 of FIG. 4 . The plurality of first bonding lines 213 may be formed by penetrating the first bonding insulator 212 in the first direction D1. In some embodiments, the first bonding layer 211 may be configured to include at least one first dummy bonding line 214. The first dummy bonding line 214 may be formed parallel to the plurality of first bonding lines 213 in the second direction D2 perpendicular to the first direction D1. The second direction D2 may be a horizontal direction.

The first bonding layer 211 may be formed by a single patterning process (eg, including only one photolithography and development process). As a result, in some embodiments, each first bond line 213 has substantially the same horizontal width (e.g., the diameter of the via contact). In some embodiments, the horizontal width of the plurality of first bonding lines 213 and the horizontal width of the first dummy bonding line 214 may be substantially the same. In some embodiments, the plurality of first bonding lines 213 and the first dummy bonding lines 214 are lines formed through a single damascene process rather than lines formed through a dual damascene process. This can result in process simplification.

Through the single damascene process, the first and second bonding lines 213 and 214 are directly bonded instead of indirectly through other lines or vias, thereby increasing the area of the electrical contact. This has the effect of reducing resistance by increasing the wiring area. It also results in an increase in the volume of conductors such as Cu that make up the electrical contact. This maximizes the expansion of the etching, barrier/adhesion layer or conductor in the dishing profile through deposition, planarization, etc. of the barrier/adhesion layer or conductor (e.g. metal). Because you can. If the volume of the conductor constituting the electrical contact increases, the possibility of unbonding failure during the bonding process of the first semiconductor structure 210 and the second semiconductor structure 230 can be improved.

The plurality of first bond lines 213 are functional bond contacts that are part of the electrical connection between the first semiconductor structure 210 and the second semiconductor structure 230 across the bond interface 220 . The first dummy bond line 214 is a dummy bond contact that crosses the bond interface 220 and is not part of the electrical connection between the first semiconductor structure 210 and the second semiconductor structure 230. The plurality of first bonding lines 213 and first dummy bonding lines 214 within the first bonding layer 211 are made of a conductive material including, but not limited to, W, Co, Cu, Al, or any combination thereof. It can be included. In some embodiments, the plurality of first bond lines 213 and first dummy bond lines 214 are made of Cu for hybrid bonding.

The first dummy bond line 214 increases the local density of functional bond contacts that are part of the electrical connection between the first semiconductor structure 210 and the second semiconductor structure 230 at the bond interface 220, thereby increasing bond yield and strength. Can be used to increase The density of the bonding contacts can affect hybrid bonding. In addition to the first bonding line 213, which is a functional bonding contact required for electrical interconnection, a first dummy bonding line 214 is added to the first bonding layer 211 to improve hybrid bonding yield and strength. density can be increased.

The first bond insulator 212 in the first bond layer 211 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. . In some embodiments, first junction insulator 212 is made of silicon oxide for hybrid junctions.

A first liner film 215 may exist between the first bonding layer 211 and the first wiring layer 216. An interface may exist between the first liner film 215 and the first bonding layer 211. That is, the first liner film 215 may be a separate layer from the first bonding layer 211. That is, the first liner film 215 may not be formed at the same time as the first bonding layer 211. In some embodiments, first liner film 215 may be SiN.

The plurality of first bonding lines 213 may extend in the first direction D1 and penetrate the first bonding layer 211 and the first liner film 215. The plurality of first bonding lines 213 extend in the first direction D1 and completely penetrate the first liner film 215 between the first bonding layer 211 and the first wiring layer 216, It may contact the plurality of first wiring pads 218 of the wiring layer 216 . In some embodiments, a cross section of the plurality of first bonding lines 213 that contact the plurality of first wiring pads 218 may be the first surface 213a. The first surface 213a may be the lower surface of the first bonding line 213. The plurality of first bonding lines 213 may be electrically connected by contacting the plurality of first wiring pads 218 and form an electrical bonding contact. In some embodiments, the plurality of first bonding lines 213 and the plurality of first wiring pads 218 that contact each other in the first semiconductor structure 210 may not have a one-to-one correspondence. That is, there may be two or more first bonding lines 213 contacting one first wiring pad 218. The number of first bonding lines 213 contacting one first wiring pad 218 may be different. In another embodiment, the plurality of first bonding lines 213 and the plurality of first wiring pads 218 that contact each other may have a one-to-one correspondence. That is, one first bonding line 213 may contact one first wiring pad 218.

At least one first dummy bonding line 214 extends in the first direction D1 parallel to the plurality of first bonding lines 213 and penetrates the first bonding layer 211 and the first liner film 215. can do. Unlike the plurality of first bonding lines 213 , the first dummy bonding line 214 may not contact the plurality of first wiring pads 218 of the first wiring layer 216 . In some embodiments, the first dummy bond line 214 may completely penetrate the first liner film 215 and contact the first pad insulator 217 of the first interconnection layer 216 . In some embodiments, the cross section of at least one first dummy bond line 214 that contacts the first pad insulator 217 may be the first surface 214a. In other embodiments, unlike what is shown in the figure, the first dummy bond line 214 may not completely penetrate the first liner film 215. That is, the first dummy bonding line 214 may not contact the first pad insulator 217 of the first wiring layer 216. In this case, the first surface 214a of the first dummy bonding line 214 exists within the first liner film 215. In other embodiments, the first dummy bond line 214 completely penetrates the first liner film 215 and extends further in the first direction D1 to connect the first pad insulator of the first interconnection layer 216 ( 217) It can be extended to the inside. That is, the first surface 214a of the first dummy bond line 214 may exist within the first pad insulator 217.

Since the etch ratio is different for each material, the etch depth may vary when different materials are etched during the process. After forming the first liner film 215 on the first wiring layer 216 and depositing the first bonding insulator 212 on the first liner film 215, the first bonding insulator 212 ) and the first liner film 215 are etched to form a trench, and then the inside of the trench is filled with material to form a plurality of first bond lines 213 and first dummy bond lines 214. At this time, the first bonding line 213 constituting the electrical contact may contact the first wiring pad 218 of the first wiring layer 216 and be electrically connected. When etching the first bond insulator 212 and the first liner film 215 to form a trench, the etch depth may vary because the etch stop layer is different. That is, when forming a trench for forming the first bonding line 213, etching is stopped by contacting the material layer forming the first wiring pad 218, but forming the first dummy bonding line 214 When a trench is formed, etching is stopped upon contact with the material layer constituting the first junction insulator 212. Since the material constituting the first wiring pad 218 and the material constituting the first junction insulator 212 are different, the etch depth may vary. In some embodiments, the first dummy bonding line 214 may be formed to have a greater depth in the first direction D1 with respect to the bonding interface 220 than the plurality of first bonding lines 213 . In another embodiment, the first dummy bonding line 214 may be formed to have a shallower depth in the first direction D1 with respect to the bonding interface 220 than the plurality of first bonding lines 213 .

On the opposite side of the junction interface 220, the second semiconductor structure 230 may also include a second interconnection layer 236 beneath the second device layer 239. In some embodiments, the second wiring layer 236 may include a second pad insulator 237 and a plurality of second wiring pads 238. The second wiring pad 238 may include the first interconnect structure IC1 or the second interconnect structure IC2 of FIG. 4 . In some embodiments, the plurality of second wiring pads 238 are configured to transmit electrical signals across the junction interface 220 and between the first semiconductor structure 210 and the second semiconductor structure 230. It is a functional MEOL or BEOL wiring pad that is electrically connected to both the first device layer 219 of the semiconductor structure 210 and the second device layer 239 of the second semiconductor structure 230. In some embodiments, only some of the plurality of second wiring pads 238 may be functional MEOL or BEOL wiring pads that are electrically connected to both the first device layer 219 and the second device layer 239. In some embodiments, some of the plurality of second wiring pads 238 are electrically connected to the second device layer 239 of the second semiconductor structure 230 in order to transmit electrical signals within the second semiconductor structure 230. It may be a functional MEOL or BEOL wiring pad that is connected to but not electrically connected to the first device layer 219 of the first semiconductor structure 210. In some embodiments, some of the plurality of second wiring pads 238 may be dummy wiring pads that are not electrically connected to the second device layer 239 of the second semiconductor structure 230. The plurality of second wiring pads 238 in the second wiring layer 236 include, but are not limited to, W, Co, Cu, Al, silicide, or any combination thereof.

The second pad insulator 237 in the second wiring layer 236 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

The second semiconductor structure 230 may further include a second bonding layer 231 on the second wiring layer 236. The second bonding layer 231 may include a second bonding insulator 232, a plurality of second bonding lines 233, and a second dummy bonding line 234. The second bonding line 233 may include the first bonding pad BP1 or the second bonding pad BP2 of FIG. 4 . The plurality of second bonding lines 233 may be formed by penetrating the second bonding insulator 232 in the first direction D1. In some embodiments, the second bonding layer 231 may be configured to include at least one second dummy bonding line 234. The second dummy bonding line 234 may be formed side by side in the second direction D2 perpendicular to the first direction D1.

Like the first bonding layer, the second bonding layer 231 may be formed by a single patterning process (eg, including only one photolithography and development process). As a result, in some embodiments, each second bond line 233 has substantially the same horizontal width (e.g., the diameter of the via contact). In some embodiments, the horizontal width of the plurality of second bonding lines 233 and the horizontal width of the second dummy bonding line 234 may be substantially the same. In some embodiments, the plurality of second bond lines 233 and second dummy bond lines 234 are single damascene lines rather than dual damascene lines.

The plurality of second bond lines 233 are functional bond contacts that are part of the electrical connection between the first semiconductor structure 210 and the second semiconductor structure 230 across the bond interface 220 . The second dummy bond line 234 is a dummy bond contact that crosses the bond interface 220 and is not part of the electrical connection between the first semiconductor structure 210 and the second semiconductor structure 230. The plurality of second bonding lines 233 and second dummy bonding lines 234 in the second bonding layer 231 are made of a conductive material including, but not limited to, W, Co, Cu, Al, or any combination thereof. It can be included. In some embodiments, the plurality of second bond lines 233 and second dummy bond lines 234 are made of Cu for hybrid bonding.

As described above, the second dummy bond line 234 increases the local density of functional bond contacts that are part of the electrical connection between the first semiconductor structure 210 and the second semiconductor structure 230 at the bond interface 220. Can be used to increase bonding yield and strength. This may form a Cu-Cu fusion joint with a corresponding first dummy bond line 214 at the bond interface 220 . The density of the bonding contacts can affect hybrid bonding. In addition to the second bond line 233, which is a functional bond contact required for electrical interconnection, a second dummy bond line 234 is added to the second bond layer 231 to improve hybrid bond yield and strength. density can be increased.

The second bond insulator 232 in the second bond layer 231 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. . In some embodiments, second junction insulator 232 is made of silicon oxide for hybrid junctions.

A second liner film 235 may exist between the second bonding layer 231 and the second wiring layer 236. An interface may exist between the second liner film 235 and the second bonding layer 231. That is, the second liner film 235 may be a separate layer from the second bonding layer 231. That is, the second liner film 235 may not be formed at the same time as the second bonding layer 231. In some embodiments, second liner film 235 may be SiN.

The plurality of second bonding lines 233 may extend in the first direction D1 and penetrate the second bonding layer 231 and the second liner film 235. The plurality of second bonding lines 233 extend in the first direction D1 and completely penetrate the second liner film 235 between the second bonding layer 231 and the second wiring layer 236, It may contact the plurality of second wiring pads 238 of the wiring layer 236. In some embodiments, the cross-section of the plurality of second bonding lines 233 that contact the plurality of second wiring pads 238 may be the first surface 233a. The first surface 233a of the second bonding line 233 may be the upper surface of the second bonding line 233. The plurality of second bonding lines 233 may be electrically connected by contacting the plurality of second wiring pads 238 and form an electrical bonding contact. In some embodiments, the plurality of second bond lines 233 and the plurality of second wiring pads 238 that contact each other in the second semiconductor structure 230 may not have a one-to-one correspondence. That is, there may be two or more second bonding lines 233 in contact with one second wiring pad 238. The number of second bonding lines 233 contacting one second wiring pad 238 may be different. In another embodiment, the plurality of second bonding lines 233 and the plurality of second wiring pads 238 that contact each other may have a one-to-one correspondence. That is, one second bonding line 233 may contact one second wiring pad 238.

At least one second dummy bonding line 234 extends in the first direction D1 parallel to the plurality of second bonding lines 233 and penetrates the second bonding layer 231 and the second liner film 235. can do. Unlike the plurality of second bonding lines 233, the second dummy bonding line 234 may not contact the plurality of second wiring pads 238 of the second wiring layer 236. In some embodiments, the second dummy bond line 234 may completely penetrate the second liner film 235 and contact the second pad insulator 237 of the second wiring layer 236. In some embodiments, the cross section of at least one second dummy bond line 234 in contact with the second pad insulator 237 may be the first surface 234a. In other embodiments, unlike what is shown in the figure, the second dummy bonding line 234 may not completely penetrate the second liner film 235. That is, the second dummy bonding line 234 may not contact the second pad insulator 237 of the second wiring layer 236. In this case, the first surface 234a of the second dummy bonding line 234 exists within the second liner film 235. In other embodiments, the second dummy bond line 234 completely penetrates the second liner film 235 and extends further in the first direction D1 to connect the second pad insulator of the second wiring layer 236 ( 237) It can be extended to the inside. That is, the first surface 234a of the second dummy bond line 234 may exist within the second pad insulator 237. That is, in some embodiments, the second dummy bonding line 234 may be formed to have a greater depth in the first direction D1 with respect to the bonding interface 220 than the plurality of second bonding lines 233 . In another embodiment, the second dummy bonding line 234 may be formed to have a shallower depth in the first direction D1 with respect to the bonding interface 220 than the plurality of second bonding lines 233 .

The first semiconductor structure 210 and the second semiconductor structure 230 may be bonded by contacting each other at the bonding interface 220 . At the bonding interface 220, a plurality of first bonding lines 213 and a plurality of second bonding lines 233 may be in contact. In some embodiments, the cross section of the plurality of first bonding lines 213 that contacts the plurality of second bonding lines 233 may be the second surface 213b. The second surface 213b of the first bonding line 213 may be the upper surface of the first bonding line 213. In some embodiments, the cross section of the plurality of second bonding lines 233 that contacts the plurality of first bonding lines 213 may be the second surface 233b. The second surface 233b of the second bonding line 233 may be the lower surface of the second bonding line 233. That is, at the bonding interface 220, the second surface 213b of the plurality of first bonding lines 213 and the second surface 233b of the plurality of second bonding lines 233 may be in contact. The plurality of first bonding lines 213 and the plurality of second bonding lines 233 may form a one-to-one correspondence relationship. That is, the number of first bonding lines 213 and the number of second bonding lines 233 may be the same. In some embodiments, the first plurality of bonding lines 213 and the plurality of second bonding lines 233 may be symmetrical to each other with the bonding interface 220 interposed therebetween. That is, from a plan view, the plurality of first bonding lines 213 and the plurality of second bonding lines 233 may overlap each other.

At the bonding interface 220, the first dummy bonding line 214 may contact the second dummy bonding line 234. In some embodiments, the cross section of the first dummy bonding line 214 that contacts the second dummy bonding line 234 may be the second surface 214b. In some embodiments, the cross section of the second dummy bonding line 234 that contacts the duplicate first dummy bonding line 214 may be the second surface 234b. That is, at the bonding interface 220, the second surface 214b of the first dummy bonding line 214 and the second surface 234b of the second dummy bonding line 234 may contact. The first dummy bonding line 214 and the second dummy bonding line 234 may form a one-to-one correspondence relationship. That is, the number of first dummy bonding lines 214 and second dummy bonding lines 234 may be the same. That is, from a plan view, the first dummy bonding line 214 and the second dummy bonding line 234 may overlap each other.

A plurality of first and second bonding lines 213 and 214 in contact at the bonding interface 220 are symmetrical to each other with respect to the bonding interface 220, and the first and second dummy bonding lines 214 and 234 are bonded. Unlike being symmetrical to each other with respect to the interface 220, the first wiring pad 218 of the first wiring layer 216 and the second wiring pad 238 of the second wiring layer 236 may not be symmetrical to each other. there is. That is, from a plan view, the first wiring pad 218 and the second wiring pad 238 may not overlap each other. In some embodiments, the number of first wiring pads 218 may be different from the number of second wiring pads 238. Or, in some embodiments, the number of first bonding lines 213 in contact with each of the first wiring pads 218 may be different from the number of second bonding lines 233 in contact with each of the second wiring pads 238. You can. When the numbers of the first and second bonding lines 213 and 233 in contact with the first and second wiring pads 218 and 238 are different from each other, the first and second bonding lines 213 and 233 Since they are symmetrical to each other across the bonding interface 220, the first and second wiring pads 218 and 238 may not be symmetrical to each other across the bonding interface 220.

A junction interface 220 may be formed between the first semiconductor structure 210 and the second semiconductor structure 230. At the bonding interface 220, the first semiconductor structure 210 and the second semiconductor structure 230 may be vertically bonded. The bonding interface 220 may be a surface with no thickness or a layer with a thickness. If the bonding interface is a thick layer, it may include SiCN.

Hereinafter, in FIGS. 6 to 12, the differences from FIG. 5 will be explained with emphasis. Components not described are similar to those described with reference to FIG. 5 .

Referring to FIG. 6 , unlike what is shown in FIG. 5 , the first wiring pad 318 of the first wiring layer 316 and the second wiring pad 338 of the second wiring layer 336 have a bonding interface 320. may be symmetrical to each other. That is, from a plan view, the first wiring pad 318 and the second wiring pad 338 may overlap each other. In some embodiments, the number of first wiring pads 318 may be equal to the number of second wiring pads 338. In some embodiments, the number of first bonding lines 313 in contact with each of the first wiring pads 318 may be equal to the number of second bonding lines 314 in contact with each of the second wiring pads 338. .

Referring to FIG. 7 , unlike FIG. 5 , the first dummy bond line 414 may contact the first wiring pad 418 . In some embodiments, the first dummy bonding line 414 may extend in the first direction D1 and penetrate the first bonding layer 411 and the first liner film 415. The first dummy bonding line 414 extends in the first direction D1 and completely penetrates the first liner film 415 between the first bonding layer 411 and the first wiring layer 416, thereby forming the first wiring layer. It may contact the first wiring pad 418 of layer 416 . In some embodiments, the cross section of the first dummy bond line 414 that contacts the first wiring pad 418 may be the second surface 414a. The first dummy bond line 414 may be physically connected to the first wiring pad 418, but may not be electrically connected to the first wiring pad 418. That is, even if the first dummy bond line 414 is connected to the first wiring pad 418, it does not serve as an electrical contact.

The second dummy bonding line 434 may extend in the first direction D1 in parallel with the plurality of second bonding lines 433 and penetrate the second wiring layer 431 and the second liner film 435. . Unlike the first dummy bonding line 414 contacting the first wiring pad 418 of the first wiring layer 416, the second dummy bonding line 434 is in contact with the second wiring pad 418 of the second wiring layer 436. There may be no contact with the pad 438. In some embodiments, the second dummy bond line 434 may completely penetrate the second liner film 435 and contact the second pad insulator 437 of the second wiring layer 436. In some embodiments, the cross section of the second dummy bond line 434 in contact with the second pad insulator 437 may be the first surface 434a. In other embodiments, unlike what is shown in the figure, the second dummy bond line 434 may not completely penetrate the second liner film 435. That is, the second dummy bond line 434 may not contact the second pad insulator 437 of the second wiring layer 436. In this case, the first surface 434a of the second dummy bonding line 434 exists within the second liner film 435. In other embodiments, the second dummy bond line 434 completely penetrates the second liner film 435 and extends further in the first direction D1 to connect the second pad insulator of the second wiring layer 436 ( 437) It can be extended to the inside. That is, the first surface 434a of the second dummy bond line 434 may exist within the second pad insulator 437. That is, in some embodiments, the second dummy bonding line 434 may be formed to have a greater depth in the first direction D1 with respect to the bonding interface 420 than the plurality of second bonding lines 433 . In another embodiment, the second dummy bonding line 434 may be formed to have a shallower depth in the first direction D1 with respect to the bonding interface 420 than the plurality of second bonding lines 433 .

The first dummy bond line 414 may contact the first wiring pad 418 , while the second dummy bond line 434 may not contact the second wiring pad 438 . Accordingly, the first wiring pad 418 of the first wiring layer 416 and the second wiring pad 438 of the second wiring layer 436 may be formed in shapes that are not symmetrical to each other. In some embodiments, the number of first wire pads 418 and second wire pads 438 may be the same, but this means that the first and second wire pads 418 and 438 are connected to the first wire pad 418 and the second wire pad 438. The number of bonding lines 413 and 433 and the type of bonding line, that is, first and second bonding lines or first and second dummy bonding lines, do not mean the same thing. In some embodiments, the first wiring pad 418 and the second wiring pad 438 may not overlap each other from a plan view.

Referring to FIG. 8, there may be one or more first and second dummy bonding lines 514 and 534. Some of the one or more first and second dummy bonding lines 514 and 534 may be dummy bonding lines connected to the first and second wiring pads 518 and 538, and some of the remaining portions may be connected to the first and second wiring pads (514 and 534). It may be a dummy joint line that is not connected to 518, 538). That is, in some embodiments, the first side 514a of one first dummy bonding line 514 may be physically connected to the first wiring pad 518, and the first side 514a of another first dummy bonding line 514 may be physically connected to the first wiring pad 518. (514a) may be physically connected to the first pad insulator 517. Even though the first or second dummy bonding lines 514 and 534 are physically connected to the first or second wiring pads 518 and 538, they may not be electrically connected. In some embodiments, if the first side 514a of a first dummy bond line 514 is physically connected to the first wiring pad 518, the first dummy bond line 514 and the second side ( The first surface 534a of the second dummy bond line 534 contacted through 534b may be physically connected to the second wiring pad 538. Likewise, if the first side 534a of a second dummy bond line 534 is physically connected to the second wiring pad 538, the second dummy bond line 534 and the second side 514b are connected to each other. The first surface 514a of the first dummy bonding line 514 contacting the surface 514 may be physically connected to the first wiring pad 518 . In some embodiments, if the first side 514a of any first dummy bond line 514 is not physically connected to the first wiring pad 518, then the first dummy bond line 514 and the second side The first side 534a of the second dummy bond line 534 contacted through 534b may not be physically connected to the second wiring pad 538. Likewise, if the first side 534a of a second dummy bonding line 534 is physically connected to the second wiring pad 538, through the second dummy bonding line 534 and the second side 514b. The first surface 514a of the first dummy bond line 514 that is in contact may not be physically connected to the first wiring pad. In this case, the first wiring pad 518 and the second wiring pad 538 may be formed symmetrically with respect to the bonding interface 520 . That is, from a plan view, the first wiring pad 518 and the second wiring pad 538 may overlap each other.

Referring to FIG. 9, there may be one or more first and second dummy bonding lines 614 and 634. Some of the one or more first and second dummy bonding lines 614 and 634 may be dummy bonding lines connected to the first and second wiring pads 618 and 638, and some of the remaining portions may be connected to the first and second wiring pads (614 and 634). It may be a dummy joint line that is not connected to 618, 638). That is, in some embodiments, the first side 614a of a first dummy bonding line 614 may be physically connected to the first wiring pad 618, and the first side of the first dummy bonding line 614 ( 614a) may be physically connected to the first pad insulator 617. However, unlike FIG. 8 , in some embodiments, even if the first surface 614a of a first dummy bonding line 614 is physically connected to the first wiring pad 618, the first dummy bonding line 614 The first surface 634a of the second dummy bond line 634 that contacts the second surface 634b may not be physically connected to the second wiring pad 638. Likewise, even if the first side 634a of any second dummy bond line 634 is not physically connected to the second wiring pad 638, the second dummy bond line 634 and the second side 614b The first surface 614a of the first dummy bonding line 614 contacted through may be physically connected to the first wiring pad 618. In some embodiments, if the first side 614a of the other first dummy bond line 614 is not physically connected to the first wiring pad 618, the first dummy bond line 614 and the second side The first side 634a of the second dummy bond line 634 contacted through 634b may not be physically connected to the second wiring pad 638. In this case, the first wiring pad 618 and the second wiring pad 638 may be formed not to be symmetrical to each other with respect to the bonding interface 620. In another embodiment, the first wiring pad 618 and the second wiring pad 638 may not overlap each other from a plan view.

Referring to FIG. 10, if the first surface 714a of a first dummy bond line 714 is physically connected to the first wiring pad 718, similar to that described with reference to FIG. 8, the first dummy bond line 714 is physically connected to the first wiring pad 718. The first side 734a of the second dummy bonding line 734 that contacts the bonding line 714 through the second side 734b may be physically connected to the second wiring pad 738. In some embodiments, if the first side 714a of any first dummy bond line 714 is not physically connected to the first wiring pad 718, then the first dummy bond line 714 and the second side The first side 734a of the second dummy bond line 734 contacted through 734b may not be physically connected to the second wiring pad 738. In this case, the first wiring pad 718 and the second wiring pad 738 may be formed not to be symmetrical to each other with respect to the bonding interface 720. In another embodiment, the first wiring pad 718 and the second wiring pad 738 may not overlap each other from a plan view.

Referring to FIGS. 11 and 12 , the first semiconductor structure 810 and the second semiconductor structure 830 may be misaligned with each other at the junction interface 820. In particular, the first bonding line 813 may be misaligned with the second bonding line 833 at the bonding interface 820. In other words, when the second surface 813b of the first bonding line 813 and the second surface 833b of the second bonding line 833 contact each other at the bonding interface 820, there may be a portion that is misaligned. That is, the entire area of the second surface 813b of the first bonding line 813 does not contact the entire area of the second surface 833b of the second bonding line 833, but the first bonding line 813 A portion of the second surface 813b may not be in contact with a portion of the second surface 833b of the second bonding line 833 . Likewise, a portion of the second surface 833b of the second bonding line 833 may not be in contact with a portion of the second surface 813b of the first bonding line 813 . In some embodiments, the first bonding line 813 and the second bonding line 833 may not overlap in plan view. In some embodiments, the centerline of the first bonding line 813 may not coincide with the centerline of the second bonding line 833.

In some embodiments, the first dummy bond line 814 may be misaligned with the second dummy bond line 834 at the bond interface 820. In other words, when the second surface 814b of the first dummy bonding line 814 and the second surface 834b of the second dummy bonding line 834 contact at the bonding interface 820, there may be a portion that is misaligned with each other. there is. That is, the entire area of the second surface 814b of the first dummy bonding line 814 does not contact the entire area of the second surface 834b of the second dummy bonding line 834, but the first dummy bonding line 834 Some areas of the second side 814b of 814 may not be in contact with some areas of the second side 834b of the second dummy bond line 834 . Likewise, a portion of the second surface 834b of the second dummy bonding line 834 may not be in contact with a portion of the second surface 814b of the first dummy bonding line 814 . In some embodiments, the first dummy bond line 814 and the second dummy bond line 834 may not overlap in plan view. In some embodiments, the centerline of the first dummy bonding line 814 may not coincide with the centerline of the second dummy bonding line 834.

Meanwhile, as shown in FIG. 11, the first wiring pad 818 of the first wiring layer 816 and the second wiring pad 838 of the second wiring layer 836 are aligned with each other around the bonding interface 820. It may be formed not symmetrically. That is, the first wiring pad 818 and the second wiring pad 838 may not overlap each other from a plan view.

In other embodiments, as shown in FIG. 12, the first wire pad 818 of the first wire layer 816 and the second wire pad 838 of the second wire layer 836 have a bond interface 820. ) can be formed symmetrically around each other. That is, the first wiring pad 818 and the second wiring pad 838 may overlap each other from a plan view.

FIGS. 13A to 13D are cross-sectional views for explaining a method of manufacturing a portion of a non-volatile memory device according to an exemplary embodiment of the present invention shown in FIG. 5 . 14A to 14D are cross-sectional views illustrating a method of manufacturing a portion of a non-volatile memory device according to exemplary embodiments of the present invention.

An example of the non-volatile memory device manufactured according to FIGS. 13A to 13D may be the non-volatile memory device 200 shown in FIG. 5 . The manufacturing method will be described below.

Referring to FIG. 13A, the first device layer 219 may be formed on a substrate (not shown). In some embodiments, the first device layer 219 is deposited on the substrate by a plurality of processes, including but not limited to photolithography, dry/wet etching, thin film deposition, thermal growth, ion implantation, CMP, and other suitable processes. It may be a peripheral element layer including a plurality of transistors (not shown) formed in .

In some embodiments, the first device layer 219 may be a memory array device layer including a plurality of NAND memory strings (not shown), each extending vertically through a memory stack (not shown) formed on a substrate. . To form a memory stack, a dielectric stack comprising alternating stacks of sacrificial layers (e.g., silicon nitride) and dielectric layers (e.g., silicon oxide) can be formed using CVD, physical vapor deposition (PVD), or atomic. It may be formed on a substrate by one or more thin film deposition processes, including but not limited to atomic layer deposition (ALD) or combinations thereof. The memory stack can then be formed on the substrate by a gate replacement process, i.e., replacing the sacrificial layer in the dielectric stack with a conductive layer. In some embodiments, the manufacturing process for forming a NAND memory string includes, but is not limited to, forming a semiconductor channel extending vertically through a dielectric stack, and forming a tunneling layer, a storage layer, and a blocking layer between the semiconductor channel and the dielectric stack. It involves forming a composite dielectric layer (memory film) that does not The semiconductor channel and memory films can be made by one or more thin film deposition processes, such as ALD, CVD, PVD, other suitable processes, or any combination thereof.

Next, the first wiring layer 216 is formed on the first device layer 219. The first wiring layer 216 includes a first pad insulator 217 and a plurality of first wiring pads 218, and may be electrically connected to the first device layer 219. In some embodiments, the first wiring layer 216 includes a first pad insulator 217 and a plurality of first wiring pads 218 formed therein through multiple processes. For example, the plurality of first wiring pads 218 may include a conductive material deposited by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electrochemical deposition, or any combination thereof. You can. First pad insulator 217 may include a dielectric material deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

13B and 13C, a first liner film 215 is formed on the first wiring layer 216. A first bonding layer 211 is formed on the first liner film 215.

First, the first bonding insulator 212 is deposited on the first liner film 215. First bond insulator 212 is deposited on the top surface of first liner film 215 by a thin film deposition process including, but not limited to, CVD, PVD, ALD, or any combination thereof. Afterwards, a bonding interface layer 222 is formed to serve as an adhesive. In some embodiments, bonding interface layer 222 may include SiCN.

The first bonding line 213 and the first dummy bonding line 214 are formed in the first bonding insulator 212 to form the first bonding layer 211 on the first wiring layer 216 and the first device layer 219. forms. The first bonding line 213 and the first dummy bonding line 214 may be patterned by a single patterning process including only one photolithography process. In some embodiments, an etch mask (photoresist and/or hard mask) is patterned by a single patterning process to form bond interface layer 222 in areas where first bond line 213 and first dummy bond line 214 are to be formed. ) is exposed. Thereafter, the bonding interface layer 222, the first bonding insulator 212, and the first liner film 215 are etched at once using dry etching and/or wet etching to form the first bonding line trench 213T and the first dummy. A joint line trench 214T is formed. The first wiring pad 218 of the first wiring layer 216 may be exposed by the first bonding line trench 213T. The first pad insulator 217 of the first wiring layer 216 may be exposed by the first dummy bond line trench 214T. As described above, the first direction of the first bonding line trench 213T and the first dummy bonding line trench 214T is formed according to the difference in the etch rate of the material forming the first wiring pad 218 and the first pad insulator 217. The depth into (D1) may vary.

Referring to Figure 13c, the first bonding line 213 and the first dummy bonding line 214 are CVD, PVD, and so on to fill the first bonding line trench 213T and the first dummy bonding line trench 214T, respectively. A barrier/adhesion layer and a conductor (e.g., metal) that are in turn subsequently deposited by one or more thin film deposition processes, including but not limited to ALD, electrochemical deposition, or any combination thereof. can do. Excess conductors can be removed by CMP, and the top surface of the first bonding layer 211 can be planarized for bonding.

Since the first bonding line 213 and the first dummy bonding line 214 are formed through a single damascene process, that is, one patterning process, one etching process, etc., they may have substantially the same horizontal width. Additionally, it may have a constant horizontal width along the first direction D1. However, due to processing problems, the horizontal width may not be completely the same or the horizontal width may change along the first direction. When the horizontal width changes along the first direction, the change may occur continuously. That is, the horizontal width may not change discontinuously. In some embodiments, the cross-sectional side surfaces of the first bond line 213 and the first dummy bond line 214 do not have curved portions.

After the first bonding layer 211 is formed, the same process is repeated to form the second semiconductor structure 230. That is, the second device layer 239 is formed on the substrate, and the second wiring layer 236 is formed on the second device layer 239. The second wiring layer 236 may include a second pad insulator 237 and a second wiring pad 238. A second liner film 235 is formed on the second wiring layer 236. A second bonding insulator 232 is applied on the second liner film 235 to form a second bonding layer 231, and a bonding interface layer that can act as an adhesive is applied on the second bonding insulator 232 ( 222). Thereafter, a second bond line trench and a second dummy bond line trench are formed through a single damascene process, which is formed by one or more processes including, but not limited to, CVD, PVD, ALD, electrochemical deposition, or any combination thereof. The second bonding line 233 and the second dummy bonding line 234 are formed by filling them with materials such as a barrier/adhesion layer and a conductor (e.g., metal) that are sequentially deposited through a thin film deposition process. do.

Referring to FIG. 13D, the second semiconductor structure 230 is turned upside down. The second bonding layer 231 facing downward faces the first bonding layer 211 facing upward. In some embodiments, first bond line 213 and first dummy bond line 214 are aligned with second bond line 233 and second dummy bond line 234 prior to hybrid bonding, such that each first bond line The line 213 and the first dummy bonding line 214 contact each of the second bonding line 233 and the second dummy bonding line 234 at the bonding interface 220 after hybrid bonding. According to some embodiments, a treatment process, such as plasma treatment, wet treatment and/or heat treatment, is applied to the bonding surfaces prior to hybrid bonding. As a result of hybrid bonding, the first bonding line 213 and the first dummy bonding line 214 may be inter-mixed with the second bonding line 233 and the second dummy bonding line 234, , a bonding interface layer 222 may be formed. The bonding interface layer 222 may be formed by covalently bonding a portion of the bonding interface layer of the first semiconductor structure 210 and a portion of the bonding interface layer of the second semiconductor structure 230 made of the same material. Accordingly, a bonding interface may be formed between the first bonding layer 211 and the second bonding layer 231.

Another embodiment of a non-volatile memory device can be manufactured according to FIGS. 14A to 14D.

Referring to FIG. 14A, the first device layer 219 may be formed on a substrate (not shown). In some embodiments, the first device layer 219 may be a peripheral device layer. In another embodiment, the first device layer 219 may be a memory array device layer including NAND memory strings (not shown).

Next, the first wiring layer 216 is formed on the first device layer 219. The first wiring layer 216 includes a first pad insulator 217 and a plurality of first wiring pads 218, and may be electrically connected to the first device layer 219. In some embodiments, the first wiring layer 216 includes a first pad insulator 217 and a plurality of first wiring pads 218 formed therein through multiple processes.

Unlike what is explained with FIGS. 13A to 13D, in the non-volatile memory device manufactured with FIGS. 14A to 14D, a first bonding interface layer is used to form the first bonding layer 211 on the first wiring layer 216. (222a) is formed. The first bonding interface layer 222a may include SiCN, which constitutes the bonding interface layer 222 described above. That is, instead of sequentially applying the first liner film 215 (FIG. 13A), the first bond insulator 212 (FIG. 13A), and the first bond interface layer 222 (FIG. 13A), a single layer of the first bond interface layer 222a is applied. ) to simplify the process.

The process of FIGS. 14B to 14D is similar to that described in FIGS. 13B to 13D. In FIG. 13B, the first liner film 215 (FIG. 13A), the first bond insulator 212 (FIG. 13A), and the first bond interface layer 222 (FIG. 13A) are etched at once to form a first bond line trench 213T. And instead of forming the first dummy bond line trench 214T, in FIG. 14B, the first bond interface layer 222a, which is a single layer, is etched to form the first bond line trench 213T and the first dummy bond line trench 214T. can be formed. A barrier/adhesion layer and a conductor ( The first bonding line 213 and the first dummy bonding line 214 are formed by filling it with a material such as metal).

Forming the second semiconductor structure 230 in the same manner, aligning the first bonding line 213 and the first dummy bonding line 214 with the second bonding line 233 and the second dummy bonding line 234. , are joined to form a bonding interface 220.

Figure 15 is a diagram schematically showing a memory system including non-volatile memory elements according to example embodiments of the present invention. Figure 16 is a perspective view schematically showing a memory system including non-volatile memory elements according to example embodiments of the present invention. 17 is a cross-sectional view schematically showing a semiconductor package according to example embodiments of the present invention.

Referring to FIG. 15 , the memory system 1000 may include one or more memory elements 1100 and a memory controller 1200 electrically connected to the memory elements 1100 . The memory system 1000 may be, for example, a solid state drive device (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device including at least one memory element 1100.

The memory device 1100 may be a non-volatile memory device. For example, the memory device 1100 may be a NAND flash memory device including one of the non-volatile memory devices 100 to 900 described with reference to FIGS. 4 to 12 or a combination thereof. The memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. The first structure 1100F may correspond to the first structure S1 shown in FIG. 4. The peripheral circuit (PC) shown in FIG. 4 may include a row decoder 1110, a page buffer 1120, and a logic circuit 1130.

The second structure 1100S may correspond to the second structure S2 shown in FIG. 4 . The second structure 1100S includes a bit line (BL), a common source line (CSL), a plurality of word lines (WL), first and second string selection lines (UL1, UL2), and first and second ground selection lines. (LL1, LL2), and a plurality of memory cell strings (CSTR) between the bit line (BL) and the common source line (CSL).

In the second structure 1100S, the plurality of memory cell strings CSTR include ground selection transistors LT1 and LT2 adjacent to the common source line CSL, and string selection transistors UT1 and UT1 adjacent to the bit line BL, respectively. UT2), and a plurality of memory cell transistors (MCT) disposed between the ground selection transistors LT1 and LT2 and the string selection transistors UT1 and UT2. The number of ground selection transistors LT1 and LT2 and the number of string selection transistors UT1 and UT2 may vary depending on the embodiments.

In example embodiments, the plurality of ground selection lines LL1 and LL2 may be connected to gate electrodes of the lower transistors LT1 and LT2, respectively. The word line (WL) may be connected to the gate electrode of the memory cell transistor (MCT). The plurality of string selection lines UL1 and UL2 may be connected to the gate electrodes of the string selection transistors UT1 and UT2, respectively.

A common source line (CSL), a plurality of ground selection lines (LL1 and LL2), a plurality of word lines (WL), and a plurality of string selection lines (UL1 and UL2) may be connected to the row decoder 1110. A plurality of bit lines BL may be electrically connected to the page buffer 1120.

The memory element 1100 may communicate with the memory controller 1200 through an external connection pad 1101 that is electrically connected to the logic circuit 1130. The external connection pad 1101 may be electrically connected to the logic circuit 1130.

The memory controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the memory system 1000 may include a plurality of memory elements 1100, and in this case, the memory controller 1200 may control the plurality of memory elements 1100.

The processor 1210 may control the overall operation of the memory system 1000, including the memory controller 1200. The processor 1210 may operate according to predetermined firmware and may control the NAND controller 1220 to access the memory device 1100. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the memory device 1100. Through the NAND interface 1221, a control command for controlling the memory element 1100, data to be written to a plurality of memory cell transistors (MCTs) of the memory element 1100, and a plurality of memory cells of the memory element 1100. Data to be read from the transistor (MCT) may be transmitted. The host interface 1230 may provide a communication function between the memory system 1000 and an external host. Upon receiving a control command from an external host through the host interface 1230, the processor 1210 may control the memory device 1100 in response to the control command.

Referring to FIG. 16, a memory system 2000 according to an exemplary embodiment of the present invention includes a main board 2001, a memory controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and May include DRAM (2004). The semiconductor package 2003 and the DRAM 2004 may be connected to the memory controller 2002 through a plurality of wiring patterns 2005 formed on the main substrate 2001.

The main board 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the memory system 2000 and the external host. In exemplary embodiments, the memory system 2000 may include Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Storage (UFS), etc. It is possible to communicate with an external host according to any one of the interfaces. In example embodiments, the memory system 2000 may operate with power supplied from an external host through the connector 2006. The memory system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the memory controller 2002 and the semiconductor package 2003.

The memory controller 2002 can write data to the semiconductor package 2003 or read data from the semiconductor package 2003, and can improve the operating speed of the memory system 2000.

DRAM (2004) may be a buffer memory to alleviate the speed difference between the semiconductor package (2003), which is a data storage space, and an external host. The DRAM 2004 included in the memory system 2000 may operate as a type of cache memory and may provide a space for temporarily storing data during control operations for the semiconductor package 2003. When the memory system 2000 includes the DRAM 2004, the memory controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b that are spaced apart from each other. The first and second semiconductor packages 2003a and 2003b may each include a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b includes a package substrate 2100, a plurality of semiconductor chips 2200 on the package substrate 2100, and an adhesive layer disposed on the lower surfaces of each of the plurality of semiconductor chips 2200. 2300), a connection structure 2400 that electrically connects the plurality of semiconductor chips 2200 and the package substrate 2100, and molding that covers the plurality of semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100. It may include a layer 2500.

The package substrate 2100 may be a printed circuit board including a plurality of package upper pads 2130. Each of the plurality of semiconductor chips 2200 may include an input/output pad 2210. The input/output pad 2210 may correspond to the input/output pad 294 or the external connection pad 296 of FIGS. 4A and 5B. Each of the plurality of semiconductor chips 2200 may include at least one of the non-volatile memory elements 100 to 900 described with reference to FIGS. 4 to 12 .

In example embodiments, the connection structure 2400 may be a bonding wire that electrically connects the input/output pad 2210 and the package top pad 2130. Therefore, in the first and second semiconductor packages 2003a and 2003b, the plurality of semiconductor chips 2200 may be electrically connected to each other using a bonding wire method and may be electrically connected to the package upper pad 2130 of the package substrate 2100. You can. In example embodiments, in the first and second semiconductor packages 2003a and 2003b, the plurality of semiconductor chips 2200 include a through silicon via (TSV) instead of the bonding wire-type connection structure 2400. They may be electrically connected to each other through a connection structure.

In example embodiments, the memory controller 2002 and the plurality of semiconductor chips 2200 may be included in one package. In an exemplary embodiment, a memory controller 2002 and a plurality of semiconductor chips 2200 are mounted on a separate interposer substrate different from the main substrate 2001, and the memory controller (2002) is formed by wiring formed on the interposer substrate. 2002) and a plurality of semiconductor chips 2200 may be connected to each other.

Referring to FIG. 17, in the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 includes a package substrate body 2120, a plurality of package upper pads 2130 disposed on the upper surface of the package substrate body 2120, and disposed on or through the lower surface of the package substrate body 2120. A plurality of exposed lower pads 2125, and a plurality of internal wirings 2135 electrically connecting the plurality of upper pads 2130 (see FIG. 10) and the plurality of lower pads 2125 inside the package substrate body 2120. ) may include. As shown in FIG. 16, the plurality of upper pads 2130 may be electrically connected to the plurality of connection structures 2400. The plurality of lower pads 2125 may be connected to the plurality of wiring patterns 2005 on the main board 2001 of the memory system 2000 shown in FIG. 16 through the plurality of conductive bumps 2800. Each of the plurality of semiconductor chips 2200 may include the non-volatile memory elements 100 to 900 described with reference to FIGS. 4 to 12 .

Above, the present invention has been described in detail with preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes can be made by those skilled in the art within the technical spirit and scope of the present invention. Change is possible.

100 to 900: non-volatile memory element, 210 to 910: first semiconductor structure, 230 to 930: second semiconductor structure, 211 to 911: first bonding layer, 231 to 913: second bonding layer, 212 to 912: first 1 junction insulator, 232 to 932: second junction insulator, 213 to 913: first junction line, 233 to 933: second junction line, 214 to 914: first dummy junction line, 234 to 934: second dummy junction line , 215 to 915: first liner film, 235 to 935: second liner film, 216 to 916: first wiring layer, 217 to 917: first pad insulator, 218 to 918: first wiring pad, 238 to 938: Second wiring pad, 219 to 919: first device layer, 239 to 939: second device layer, 220: junction interface

Claims (10)

a first semiconductor structure;
a second semiconductor structure vertically stacked on the first semiconductor structure; and
Comprising a junction interface between the first semiconductor structure and the second semiconductor structure,
The first semiconductor structure is,
A first bond insulator, a plurality of first bond lines vertically penetrating the first bond insulator, and at least one first dummy bond vertically penetrating the first bond insulator and horizontally parallel with the plurality of first bond lines. a first bonding layer comprising lines;
a first wiring layer including a first pad insulator on which a plurality of first wiring pads are disposed and vertically stacked on the first bonding layer; and
a first liner film between the first bonding layer and the first wiring layer,
The plurality of first bonding lines vertically penetrate the first wiring layer and the first liner film, and lower surfaces of the plurality of first bonding lines are in contact with the plurality of first wiring pads,
the at least one first dummy bond line passes vertically through the first liner membrane,
The second semiconductor structure is,
A second bond insulator, a plurality of second bond lines vertically penetrating the second bond insulator, and at least one second dummy bond vertically penetrating the second bond insulator and horizontally parallel with the plurality of second bond lines. a second bonding layer comprising a line and facing the first bonding layer;
a second wiring layer including a second pad insulator on which a plurality of second wiring pads are disposed and vertically stacked on the second bonding layer; and
a second liner film between the second bonding layer and the second wiring layer,
The plurality of second bonding lines vertically penetrate the second wiring layer and the second liner film, and the upper surface of the plurality of second bonding lines contacts the plurality of second wiring pads,
the at least one second dummy bond line vertically penetrating the second liner membrane,
The upper surface of the plurality of first bonding lines contacts the lower surface of the plurality of second bonding lines at the bonding interface,
A non-volatile memory device wherein an upper surface of the at least one first dummy bond line is in contact with a lower surface of the at least one second dummy bond line at the bonding interface. According to claim 1,
Some of the at least one first dummy bond line do not contact the plurality of first wiring pads,
A non-volatile memory device in which a portion of the at least one second dummy junction line does not contact the plurality of second wiring pads. According to claim 1,
The horizontal width of the plurality of first bonding lines and the horizontal width of the at least one first dummy bonding line are substantially the same,
A non-volatile memory device wherein the horizontal width of the plurality of second bond lines and the horizontal width of the at least one second dummy bond line are substantially equal. According to claim 1,
The plurality of first bond lines and the at least one first dummy bond line are formed through a first single damascene process,
The plurality of second bond lines and the at least one second dummy bond line are formed through a second single damascene process. According to claim 1,
A horizontal width of the plurality of first bond lines and the at least one first dummy bond line is tapered,
A non-volatile memory device wherein the horizontal width of the plurality of second bond lines and the at least one second dummy bond line is reverse tapered. According to claim 1,
A non-volatile memory device wherein a portion of the upper surface of the plurality of first bonding lines does not contact the lower surface of the plurality of second bonding lines at the bonding interface. According to claim 1,
A memory device wherein a portion of a second surface of the at least one first dummy bond line does not contact a second surface of the at least one second dummy bond line at the bonding interface. According to claim 1,
The non-volatile memory device includes: a first device layer having a NAND memory string and vertically stacked on the first wiring layer; and
It further includes a second element layer having peripheral elements and being stacked perpendicularly to the second wiring layer,
the at least one first dummy junction line is not electrically connected to the NAND memory string,
A non-volatile memory device wherein the at least one second dummy junction line is not electrically connected to the peripheral device. According to claim 1,
A non-volatile memory device comprising an interface between the first bonding layer and the first liner film and an interface between the second bonding layer and the second liner film. According to claim 1,
The number of the plurality of first bonding lines is equal to the number of the plurality of second bonding lines,
A non-volatile memory device wherein the number of the at least one first dummy junction line is equal to the number of the at least one second dummy junction line.

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