KR20220013949A - Semiconductor devices and data storage systems including the same - Google Patents

Abstract

According to an embodiment of the present invention, a semiconductor device comprises: a peripheral circuit structure including a substrate, a circuit element on the substrate, a circuit line structure electrically connected to the circuit element on the substrate and including connection patterns disposed at different height levels from each other, and a peripheral area insulating structure for covering the circuit element and the circuit line structure on the substrate; a memory cell structure disposed on the peripheral circuit structure, and including gate electrodes stacked to be spaced apart from each other in a first direction perpendicular to the substrate, a channel structure penetrating the gate electrodes, and an upper line electrically connected to the channel structure on the channel structure; and a through-contact plug for electrically connecting at least one of the gate electrodes and the upper line to at least one of the connection patterns. The connection patterns include an upper connection pattern in contact with the through-contact plug. Also, the peripheral area insulating structure includes a first lower insulating layer for covering the circuit element, a second lower insulating layer on the first lower insulating layer, and a buffer insulating structure between the first and second lower insulating layers. In addition, the buffer insulating structure includes an insulating pattern on the upper connection pattern, a first buffer layer disposed on the first lower insulating layer and covering a side surface of the insulating pattern, and a second buffer layer on the first buffer layer and the insulating pattern. Therefore, the production yield is improved.

Description

Semiconductor device and data storage system including same

The present invention relates to a semiconductor device and a data storage system including the same.

In a data storage system requiring data storage, a semiconductor device capable of storing high-capacity data is required. Accordingly, a method for increasing the data storage capacity of a semiconductor device is being studied. For example, as a method for increasing the data storage capacity of a semiconductor device, a semiconductor device including memory cells arranged three-dimensionally instead of two-dimensionally arranged memory cells has been proposed.

One of the technical problems to be achieved by the technical idea of the present invention is to provide a semiconductor device and a data storage system with improved production yield.

A semiconductor device according to example embodiments may include a substrate, a circuit element on the substrate, a circuit wiring structure including connection patterns electrically connected to the circuit element on the substrate and disposed at different height levels, and on the substrate A peripheral circuit structure including a peripheral region insulating structure covering the circuit element and the circuit wiring structure, gate electrodes disposed on the peripheral circuit structure and spaced apart from each other and stacked in a first direction perpendicular to the substrate, the gate A memory cell structure including a channel structure passing through electrodes, an upper wiring electrically connected to the channel structure on the channel structure, and connecting at least one of the gate electrodes and the upper wiring to at least one of the connection patterns through contact plugs electrically connecting the through contact plugs, wherein the connection patterns include upper connection patterns in contact with the through contact plugs, and the peripheral region insulating structure includes a first lower insulating layer covering the circuit element, and the first lower portion a second lower insulating layer on the insulating layer, and a buffer insulating structure between the first and second lower insulating layers, wherein the buffer insulating structure is formed on the insulating pattern on the upper connection pattern and the first lower insulating layer and a first buffer layer disposed on the insulating pattern and covering a side surface of the insulating pattern, and a second buffer layer on the first buffer layer and the insulating pattern.

A semiconductor device according to example embodiments may include a substrate, a circuit element on the substrate, a circuit wiring structure including connection patterns electrically connected to the circuit element on the substrate and disposed at different height levels, and on the substrate A lower structure including a peripheral region insulating structure covering the circuit element and the circuit wiring structure, an upper structure disposed on the lower structure and including an upper wiring, and a through contact electrically connecting the upper wiring and the connection patterns a plug, wherein the connection patterns include upper connection patterns contacting the through contact plug, and the peripheral region insulating structure includes a first lower insulating layer covering the circuit element, and a second lower portion on the first lower insulating layer an insulating layer and a buffer insulating structure between the first and second lower insulating layers, wherein the buffer insulating structure is disposed on the insulating pattern on the upper connection pattern and the first lower insulating layer, A first buffer layer covering a side surface, and a second buffer layer on the first buffer layer and the insulating pattern, the insulating pattern may include silicon oxide, and the first and second buffer layers may include silicon nitride.

A data storage system according to example embodiments includes a substrate, a circuit element on the substrate, a circuit wiring structure including connection patterns electrically connected to the circuit element on the substrate and arranged at different height levels, and the substrate; a peripheral circuit structure including a peripheral region insulating structure covering the circuit element and the circuit wiring structure on the upper surface, gate electrodes disposed on the peripheral circuit structure and spaced apart from each other and stacked in a first direction perpendicular to the substrate; A memory cell structure including a channel structure passing through gate electrodes, an upper wiring electrically connected to the channel structure on the channel structure, and at least one of the gate electrodes and the upper wiring connected to at least one of the connection patterns A semiconductor storage device comprising a through contact plug electrically connected to the circuit element, an input/output pad electrically connected to the circuit element, and a controller electrically connected to the semiconductor storage device through the input/output pad and controlling the semiconductor storage device. wherein the connection patterns include an upper connection pattern in contact with the through contact plug, and the peripheral region insulating structure includes a first lower insulating layer covering the circuit element and a second lower insulating layer on the first lower insulating layer , and a buffer insulating structure between the first and second lower insulating layers, wherein the buffer insulating structure is disposed on the insulating pattern on the upper connection pattern and the first lower insulating layer, the side surface of the insulating pattern It may include a first buffer layer to cover, and a second buffer layer on the first buffer layer and the insulating pattern.

A semiconductor device in which problems such as bridging defects and mold tearing are improved by including buffer layers covering the upper connection pattern and an insulating pattern disposed only on the upper connection pattern to space the buffer layers and the upper connection pattern apart, and a semiconductor device comprising the same A data storage system may be provided.

Various and advantageous advantages and effects of the present invention are not limited to the above, and will be more easily understood in the course of describing specific embodiments of the present invention.

1A and 1B are schematic cross-sectional views of semiconductor devices according to example embodiments.
2 and 3 are schematic partial enlarged views of semiconductor devices according to example embodiments.
4 is a schematic partially enlarged view of a semiconductor device according to example embodiments.
5 is a schematic partially enlarged view of a semiconductor device according to example embodiments.
6 is a schematic partially enlarged view of a semiconductor device according to example embodiments.
7 to 11 are schematic cross-sectional views and partially enlarged views for explaining a method of manufacturing a semiconductor device according to example embodiments.
12 is a diagram schematically illustrating a data storage system including a semiconductor device according to example embodiments.
13 is a schematic perspective view of a data storage system including a semiconductor device according to an exemplary embodiment.
14 is a cross-sectional view schematically illustrating a semiconductor package according to an exemplary embodiment.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

Hereinafter, terms such as "upper", "middle" and "lower" are replaced with other terms, for example, "first", "second" and "third" to describe the elements of the specification. may be used to Terms such as “first”, “second” and “third” may be used to describe various components, but the components are not limited by the terms, and “first component” means “ may be referred to as "second component".

1A and 1B are schematic cross-sectional views of a semiconductor device 100 according to example embodiments.

2 and 3 are schematic partial enlarged views of a semiconductor device 100 according to example embodiments. 2 is an enlarged view of area 'A' of FIG. 1A, and FIG. 3 is an enlarged view of area 'B' of FIG. 1A.

1A to 3 , the semiconductor device 100 may include a peripheral circuit structure PERI including a first substrate 201 and a memory cell structure CELL including a second substrate 101 . have. The memory cell structure CELL may be disposed on the peripheral circuit PERI. Conversely, in example embodiments, the memory cell structure CELL may be disposed under the peripheral circuit structure PERI. Also, according to embodiments, the memory cell structure CELL and the peripheral circuit structure PERI may be bonded by, for example, copper (Cu)-copper (Cu) bonding. .

In an exemplary embodiment, the semiconductor device 100 further includes through interconnection regions TA1 and TA2 disposed to pass through the memory cell structure CELL to connect the memory cell structure CELL and the peripheral circuit structure PERI. can do. The through wiring areas TA1 and TA2 may include through contact plugs 174a and 174b disposed in the through wiring areas TA1 and TA2 to electrically connect the peripheral circuit structure PERI and the memory cell structure CELL. can

The peripheral circuit structure PERI includes a first substrate 201 , source/drain regions 205 and device isolation layers 210 in the first substrate 201 , and a circuit disposed on the first substrate 201 . The elements 220 , the circuit wiring structure INT electrically connected to the circuit elements 220 , and a peripheral region insulation covering the circuit elements 220 and the circuit wiring structure INT on the first substrate 201 . A structure 230 may be included.

The first substrate 201 may have an upper surface extending in the x-direction and the y-direction. The first substrate 201 may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The first substrate 201 may be provided as a bulk wafer or an epitaxial layer.

An active region may be defined in the first substrate 201 by the device isolation layers 210 . The device isolation layers 210 may be formed of shallow trench isolation. The source/drain regions 205 may be regions including impurities in a portion of the active region. The source/drain regions 205 may be spaced apart from each other in the active region.

The circuit elements 220 may include planar transistors. Each of the circuit elements 220 may include a circuit gate dielectric layer 222 , a spacer layer 224 , and a circuit gate electrode 225 . The source/drain regions 205 may be disposed in the first substrate 201 at both sides of the circuit gate electrode 225 .

In an exemplary embodiment, each of the circuit elements 220 may further include a circuit gate capping layer 226 on the circuit gate electrode 225 . The circuit gate capping layer 226 may include a material such as silicon nitride.

In an exemplary embodiment, the peripheral circuit structure PERI may further include an insulating liner 217 covering the circuit elements 220 . The insulating liner 217 may include silicon nitride.

The circuit wiring structure INT may apply an electrical signal to the circuit elements 220 . The circuit wiring structure INT may be electrically connected to the source/drain regions 205 , but may also be connected to the circuit gate electrode 225 in some embodiments.

The circuit wiring structure INT may include a plurality of connection patterns INT1 , INT2 , and INT3 disposed at different height levels. For example, the plurality of connection patterns INT1 , INT2 , and INT3 may be electrically connected to lower connection patterns INT1 and lower connection patterns INT1 electrically connected to the circuit elements 220 and lower Intermediate connection patterns INT2 disposed at a level higher than connection patterns INT1 , and upper connection patterns electrically connected to intermediate connection patterns INT2 and disposed at a higher level than intermediate connection patterns INT2 (INT3) may be included. Although the plurality of connection patterns INT1 , INT2 , and INT3 are illustrated with three levels, the number of layers of the plurality of connection patterns INT1 , INT2 , and INT3 is not limited thereto and may be variously changed.

Each of the plurality of connection patterns INT1 , INT2 , and INT3 may include a wiring portion INT_I and a via portion INT_V extending downward from a portion of the wiring portion INT_I.

In an exemplary embodiment, at least one of the plurality of connection patterns INT1 , INT2 , and INT3 may have a dual damascene structure formed by a dual damascene process of simultaneously forming the interconnection portion INT_I and the via portion INT_V have. Here, the damascene process may include forming an insulating layer, forming an opening in the insulating layer, and forming a connection pattern in the opening. In some embodiments, at least one of the plurality of connection patterns INT1 , INT2 , and INT3 may have a single damascene structure for forming the via portion INT_V by a single damascene process and a single damascene process for the interconnection portion INT_I by a single damascene process It may include a single damascene structure formed by Also, according to embodiments, the connection patterns disposed at different levels among the plurality of connection patterns INT1 , INT2 , and INT3 may be formed in a form in which a single damascene structure and a dual damascene structure are combined.

As shown in FIG. 2 , each of the plurality of connection patterns INT1 , INT2 , and INT3 includes a metal material pattern PL and a conductive barrier layer BM covering side surfaces and bottom surfaces of the metal material pattern PL. may include In an exemplary embodiment, the metal material pattern PL may include a metal material such as tungsten (W), and the conductive barrier layer BM may include a metal nitride such as titanium nitride (TiN).

The peripheral region insulating structure 230 may cover the circuit elements 220 on the first substrate 201 . In an exemplary embodiment, the perimeter region insulating structure 230 may be disposed on the insulating liner 217 . The circuit wiring structure INT may be connected to the source/drain regions 205 or the circuit elements 220 through the peripheral region insulating structure 230 .

The peripheral region insulating structure 230 may include first to fourth insulating layers 231 , 232 , 233 , and 236 sequentially stacked on the first substrate 201 . The first insulating layer 231 may surround side surfaces of the lower connection patterns INT1 . The second insulating layer 232 may surround side surfaces of the intermediate connection patterns INT2 . The third insulating layer 233 may surround side surfaces of the upper connection patterns INT3 . The fourth insulating layer 236 may be disposed on the third insulating layer 233 .

Referring to FIG. 2 , the peripheral region insulating structure 230 may further include buffer insulating structures 234 , 235 , and 239 disposed between the third insulating layer 233 and the fourth insulating layer 236 . . The buffer insulating structures 234 , 235 , and 239 include a first buffer layer 234 , a second buffer layer 235 on the first buffer layer 234 , and insulation between the upper connection patterns INT3 and the second buffer layer 235 . A pattern 239 may be included.

The first buffer layer 234 may be disposed on the third insulating layer 233 . The first buffer layer 234 may cover at least a portion of the exposed side surfaces of the upper connection patterns INT3 having a top surface higher than that of the third insulating layer 233 . The upper surface of the first buffer layer 234 may be located at a level higher than the upper surface of the upper connection patterns INT3 , and the lower surface of the first buffer layer 234 may be located at a lower level than the upper surface of the upper connection patterns INT3 . .

The insulating pattern 239 may be disposed on the upper connection patterns INT3 . In an exemplary embodiment, the insulating pattern 239 may be disposed only on the upper surface of the upper connection patterns INT3 and may not be disposed on the first buffer layer 234 . The insulating pattern 239 and the upper connection patterns INT3 may completely overlap in the z direction. However, in some embodiments, the insulating pattern 239 may include a lower surface having a width wider than that of the upper connection patterns INT3 and contacting the first buffer layer 234 . In this case, a portion of the insulating pattern 239 may not overlap the upper connection patterns INT3 in the z direction.

The upper surface of the insulating pattern 239 may be substantially coplanar with the upper surface of the first buffer layer 234 . That is, the upper surface of the insulating pattern 239 may be positioned at substantially the same level as the upper surface of the first buffer layer 234 . The first buffer layer 234 may cover a side surface of the insulating pattern 239 together with the upper connection patterns INT3 .

In an exemplary embodiment, the insulating pattern 239 may include a plurality of insulating layers in contact with the top surface of each of the plurality of upper connection patterns INT3 disposed to be spaced apart from each other. The plurality of insulating layers may be spaced apart from each other by the first buffer layer 234 .

The second buffer layer 235 may cover the first buffer layer 234 and the insulating pattern 239 . The lower surface of the second buffer layer 235 may contact the upper surface of the first buffer layer 234 and the upper surface of the insulating pattern 239 . The upper connection patterns INT3 may be spaced apart from the second buffer layer 235 by the insulating pattern 239 .

The first buffer layer 234 may contact the top surface of the third insulating layer 233 and have a first thickness t1 that is thinner than the thickness of the third insulating layer 233 . The first thickness t1 may range from about 300 Å to about 600 Å. The second buffer layer 235 may contact the lower surface of the fourth insulating layer 236 and may have a second thickness t2 that is smaller than the thickness of the fourth insulating layer 236 . The second thickness t2 may range from about 200 Å to about 400 Å. The third thickness t3 of the insulating pattern 239 may be smaller than the first thickness t1 of the first buffer layer 234 . For example, the third thickness t3 may range from about 100 Å to about 300 Å.

The first and second buffer layers 234 and 235 may include an insulating material, for example, silicon nitride or a nitride-based material. In an exemplary embodiment, the first and second buffer layers 234 and 235 may include the same material, but are not limited thereto and may include different materials. In addition, even if the first and second buffer layers 234 and 235 include the same material, boundaries may be distinguished. The insulating pattern 239 may include an insulating material different from that of the first and second buffer layers 234 and 235 . The insulating pattern 239 may include, for example, silicon oxide or an oxide-based material.

As the insulating pattern 239 disposed on the upper connection patterns INT3 is included, the semiconductor device 100 having improved bridging defects and mold torn phenomena may be provided. The insulating pattern 239 may separate the upper connection patterns INT3 from the second buffer layer 235 . Accordingly, in the deposition process for forming the second buffer layer 235 , it is possible to prevent bridging defects caused by diffusion of conductive material or residual materials in the upper connection patterns INT3 . In addition, since the insulating pattern 239 is selectively disposed only on the upper connection patterns INT3 , the silicon oxide layer is removed together in a cleaning process performed after forming a contact hole exposing the upper connection pattern INT3 . It is possible to prevent mold tearing and the like.

The memory cell structure CELL includes a second substrate 101 disposed on the peripheral region insulating structure 230 and having a first region R1 and a second region R2 , and a first of the second substrate 101 . The first horizontal conductive layer 102 on the region R1, the horizontal insulating layer 110 disposed in parallel with the first horizontal conductive layer 102 on the second region R2 of the second substrate 101, the first The second horizontal conductive layer 104 on the horizontal conductive layer 102 and the horizontal insulating layer 110 , the gate electrodes 130a and 130b and the interlayer insulating layers alternately stacked on the second horizontal conductive layer 104 . The stacked structure GS including 120a and 120b, the capping insulating layers 181a and 181b covering the stacked structure GS, the separation structures MS extending through the stacked structure GS, and the stacked structure ( It may include upper separation structures SS penetrating a portion of the GS, and channel structures CH disposed to penetrate the stack structure GS and including the channel layer 140 .

In an exemplary embodiment, the memory cell structure CELL may further include upper insulating layers 182 , 183 , and 184 , a gate contact plug 161 , wiring lines 192 , and a wiring via 193 . have.

The first region R1 of the second substrate 101 is a region in which the gate electrodes 130 are vertically stacked and the channel structures CH are disposed, and may be a region in which memory cells are disposed, and the second region ( R2) is a region in which the gate electrodes 130 extend to have different lengths, and may correspond to a region for electrically connecting the memory cells to the peripheral circuit structure PERI. The second region R2 may be disposed at at least one end of the first region R1 in at least one direction, for example, the x-direction.

The second substrate 101 may have an upper surface extending in the x-direction and the y-direction. The second substrate 101 may be provided of a semiconductor material, for example, a polycrystalline semiconductor layer such as a polycrystalline silicon layer or an epitaxial layer.

The first and second horizontal conductive layers 102 and 104 may be sequentially stacked and disposed on the top surface of the first region R1 of the second substrate 101 . The first horizontal conductive layer 102 may not extend to the second region R2 of the second substrate 101 , and the second horizontal conductive layer 104 may extend to the second region R2 .

The first horizontal conductive layer 102 may function as a part of the common source line of the semiconductor device 100 , for example, as a common source line together with the second substrate 101 . As shown in the enlarged view of FIG. 3 , the first horizontal conductive layer 102 may be directly connected to the channel layer 140 around the channel layer 140 .

The second horizontal conductive layer 104 may contact the second substrate 101 in some regions where the first horizontal conductive layer 102 and the horizontal insulating layer 110 are not disposed. The second horizontal conductive layer 104 may cover an end of the first horizontal conductive layer 102 or the horizontal insulating layer 110 in the above regions, and may be bent to extend onto the second substrate 101 . That is, the second horizontal conductive layer 104 may fill a space spaced apart between the first horizontal conductive layer 102 and the horizontal insulating layer 110 .

The first and second horizontal conductive layers 102 , 104 may include a semiconductor material, for example, both the first and second horizontal conductive layers 102 , 104 may include polycrystalline silicon.

The horizontal insulating layer 110 may be disposed on the second substrate 101 in parallel to the first horizontal conductive layer 102 in at least a portion of the second region R2 . The horizontal insulating layer 110 may be layers remaining after a part of the first horizontal conductive layer 102 is replaced with the first horizontal conductive layer 102 in the manufacturing process of the semiconductor device 100 .

The horizontal insulating layer 110 may include silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. In an exemplary embodiment, the horizontal insulating layer 110 may include first to third horizontal insulating layers sequentially stacked, wherein the first and third horizontal insulating layers are silicon oxide layers and the second horizontal insulating layer may be a silicon nitride layer.

In an exemplary embodiment, the memory cell structure CELL includes a second substrate 101 , a first horizontal conductive layer 102 , a second horizontal conductive layer 104 , and a horizontal insulating layer on the peripheral region insulating structure 230 . It may further include inner insulating layers 109a and 109b penetrating 110 and an outer insulating layer 109c disposed outside the second substrate 101 .

The gate electrodes 130 may be vertically spaced apart and stacked on the second substrate 101 to form a stacked structure GS. The gate electrodes 130 are stacked vertically spaced apart from each other on the first region R1 , and extend from the first region R1 to the second region R2 at different lengths to form a stepped structure in the form of a step. can As shown in FIG. 1A , the gate electrodes 130 may form a stepped structure between the gate electrodes 130 in the x direction. Due to the stepped structure, the gate electrodes 130 form a step shape in which the lower gate electrode 130 extends longer than the upper gate electrode 130, and ends exposed upward from the interlayer insulating layers 120 are formed. can provide The ends may be gate pads GP in which the gate electrodes 130 and the gate contact plug 161 contact each other. In example embodiments, the gate pads GP may have a relatively increased thickness compared to the remaining regions of the gate electrodes 130 .

As shown in FIG. 1B , the gate electrodes 130 may be disposed to be separated from each other in the y direction by separation structures MS extending in the x direction. The gate electrodes 130 between the pair of isolation structures MS may form one memory block, but the scope of the memory block is not limited thereto.

The gate electrodes 130 may include a metal material, for example, tungsten (W). In some embodiments, the gate electrodes 130 may include polycrystalline silicon or a metal silicide material. In an exemplary embodiment, the gate electrodes 130 may further include a gate electrode layer 131 and a gate dielectric layer 132 covering side surfaces, upper surfaces, and lower surfaces of the gate electrode layer. The gate dielectric layer 132 may be disposed between the interlayer insulating layers 120 and the channel structures CH and the gate electrode layer 131 . The gate dielectric layer 132 may include, for example, aluminum oxide (AlO).

The interlayer insulating layers 120 may be alternately stacked with the gate electrodes 130 on the second substrate 101 to form a stacked structure GS. The interlayer insulating layers 120 may be disposed between the gate electrodes 130 . Like the gate electrodes 130 , the interlayer insulating layers 120 may be spaced apart from each other in a direction perpendicular to the top surface of the second substrate 101 and may be disposed to extend in the x direction. The interlayer insulating layers 120 may include an insulating material such as silicon oxide or silicon nitride.

In an exemplary embodiment, the stacked structure GS may include a lower stacked structure GS1 and an upper stacked structure GS2 . The lower stacked structure GS1 may include first gate electrodes 130a and first interlayer insulating layers 120a that are alternately stacked. The upper stacked structure GS2 may include second gate electrodes 130b and second interlayer insulating layers 120b that are alternately stacked. In an exemplary embodiment, the number of the first gate electrodes 130a may be greater than the number of the second gate electrodes 130b, but the number of the first and second gate electrodes 130a and 130b is not limited thereto. The number may be variously changed. The lower stacked structure GS1 may further include an intermediate insulating layer 125 in contact with the upper stacked structure GS2 . The intermediate insulating layer 125 may be disposed under the upper stacked structure GS2 .

The capping insulating layers 181a and 181b may cover the stacked structure GS on the second substrate 101 . In an exemplary embodiment, the capping insulating layers 181a and 181b may include the same material as the interlayer insulating layers 120a and 120b, for example, silicon oxide. In an exemplary embodiment, the capping insulating layers 181a and 181b cover the lower capping insulating layer 181a covering the side surface of the lower stacked structure GS1 and the side surface of the upper stacked structure GS2 on the lower capping insulating layer 181a. It may include an upper capping insulating layer 181b covering it.

The upper insulating layers 182 , 183 , and 184 are disposed on the capping insulating layers 181a and 181b and may include an insulating material such as silicon oxide. In an exemplary embodiment, the upper insulating layers 182 , 183 , and 184 are a first upper insulating layer 182 and a second upper insulating layer 183 sequentially stacked on the top surfaces of the capping insulating layers 181a and 181b. , and a third upper insulating layer 184 .

The isolation structures MS may be disposed to extend in the x-direction through the gate electrodes 130 as shown in FIG. 1B . The isolation structures MS may penetrate the entire gate electrodes 130 stacked on the second substrate 101 to be connected to the second substrate 101 . The isolation structures MS may penetrate the first horizontal conductive layer 102 on the first region R1 and penetrate the horizontal insulating layer 110 on the second region R2 . The separation structures MS may be spaced apart from each other in the y-direction and disposed in parallel. In an exemplary embodiment, the isolation structures MS may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. It may include layers.

The upper separation structures SS may extend in the x direction between the separation structures MS in the first region R1 . The upper isolation structures SS may be disposed to penetrate a portion of the gate electrodes 130 including the uppermost gate electrode among the gate electrodes 130 . The upper isolation structures SS may separate the at least one gate electrodes 130 from each other in the y-direction. However, the number of gate electrodes 130 separated by the upper isolation structures SS may be variously changed in embodiments. The gate electrodes 130 separated by the upper isolation structures SS may form different string selection lines. The upper isolation structures SS may include an insulating material, for example, silicon oxide, silicon nitride, or silicon oxynitride.

The channel structures CH penetrate the gate electrodes 130 , the second horizontal conductive layer 104 , and the first horizontal conductive layer 102 on the first region R1 to contact the second substrate 101 . can do. The channel structures CH may extend into the second substrate 101 to contact the second substrate 101 , but is not limited thereto. The channel structures CH may have a columnar shape, and may have inclined sides that become narrower as they get closer to the second substrate 101 according to an aspect ratio. The channel structures CH may each form one memory cell string, and may be disposed to be spaced apart from each other while forming rows and columns on the first region R1 . The channel structures CH may be disposed to form a grid pattern or may be disposed in a zigzag shape in one direction.

Referring to FIG. 3 , the channel layer 140 may be disposed in the channel structures CH. In the channel structures CH, the channel layer 140 may be formed in an annular shape surrounding the channel filling insulating layer 144 therein. Alternatively, it may have a columnar shape such as a prism. The channel filling insulating layer 144 may include an insulating material such as silicon oxide. The channel layer 140 may be connected to the first horizontal conductive layer 102 at a lower portion. The channel layer 140 may include a semiconductor material such as polycrystalline silicon or single crystal silicon.

In an exemplary embodiment, each of the channel structures CH may further include a dielectric layer 142 and a conductive pad 145 . The dielectric layer 142 may be disposed between the gate electrodes 130 and the channel layer 140 . The dielectric layer 142 may surround at least a portion of an outer surface of the channel layer 140 . As shown in the enlarged view of FIG. 3 , the dielectric layer 142 may include a tunneling layer 142a, a charge storage layer 142b, and a blocking layer 142c sequentially stacked from the channel layer 140 . The tunneling layer 142a may tunnel charges into the charge storage layer 142b, for example, silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), or a combination thereof. may include The charge storage layer 142b may be a charge trap layer or a floating gate conductive layer. The blocking layer 142c may block charges trapped in the charge storage layer 142b from moving to the gate electrodes 130 , for example, silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ). , silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof.

As illustrated in the enlarged view of FIG. 3 , the first horizontal conductive layer 102 may include a portion penetrating through the dielectric layer 142 and in contact with the channel layer 140 . The contact portion may cover at least a portion of a side surface of the second horizontal conductive layer 104 and at least a portion of a side surface of the second substrate 101 .

The conductive pad 145 may be disposed to be electrically connected to the channel layer 140 . In an exemplary embodiment, the conductive pad 145 covers the top surface of the channel filling insulating layer 144 on the top surface of the channel filling insulating layer 144 , and the channel layer 140 surrounds the side surface of the conductive pad 145 . Alternatively, the conductive pad 145 may be disposed on the channel layer 140 . The conductive pad 145 may include, for example, doped polycrystalline silicon.

In an exemplary embodiment, each of the channel structures CH may include a first channel structure penetrating the lower stacked structure GS1 and a second channel structure penetrating the upper stacked structure GS2 . The first and second channel structures may be connected to each other to extend integrally, and each of the channel structures CH may include a channel bending portion CH_V in a region where the first and second channel structures contact each other. can

As shown in FIG. 1A , the gate contact plug 161 includes the first upper insulating layer 182 , the second upper insulating layer 183 , and the capping insulating layers 181a and 181b in the second region R2 . It may pass through and be connected to the gate pads GP.

In an exemplary embodiment, the memory cell structure CELL may further include a source contact plug 162 spaced apart from the gate electrodes 130a and 130b and in contact with the second substrate 101 .

The through contact plugs 174 may pass through the capping insulating layers 181a and 181b, the first upper insulating layer 182 , and the second upper insulating layer 183 , and may be connected to the upper connection patterns INT3 .

As shown in FIG. 2 , the through contact plugs 174 may penetrate the fourth insulating layer 236 , the second buffer layer 235 , and the insulating pattern 239 to contact the upper connection patterns INT3 . have. The through contact plugs 174 extend a predetermined depth into the upper connection patterns INT3 to increase a contact area with the upper connection patterns INT3 , thereby improving contact resistance characteristics.

The through contact plugs 174 may include a first portion P1 surrounded by the second buffer layer 235 and a second portion P2 surrounded by the insulating pattern 239 . The second portion P2 may be spaced apart from the first buffer layer 234 by the insulating pattern 239 .

The through contact plugs 174 may include a conductive material, for example, tungsten (W), copper (Cu), aluminum (Al), or the like. In an exemplary embodiment, each of the through contact plugs 174 covers the plug layer 174 - 1 having a metal material and side and bottom surfaces of the metal plug layer 174 - 1 , and includes a barrier layer including a metal nitride. (174-2).

In an exemplary embodiment, the through contact plugs 174 penetrate the first and second through contact plugs 174a and 174b penetrating the inner insulating layers 109a and 109b, and the outer insulating layer 109c. and a third through contact plug 174c.

The wiring lines 192 and the wiring via 193 may constitute an upper wiring structure electrically connected to memory cells in the memory cell structure CELL. The wiring lines 192 may be electrically connected to, for example, through contact plugs 174 , the gate electrodes 130 , and the channel structures CH. The wiring via 193 passes through the third upper insulating layer 184 , and connects the wiring lines 192 , the gate contact plug 161 , the channel structures CH, and/or the through contact plugs 174 . It can be electrically connected. The number of contact plugs and wiring lines constituting the wiring structure may be variously changed in some embodiments. The wiring lines 192 and the wiring via 193 may include metal, for example, tungsten (W), copper (Cu), aluminum (Al), or the like.

The through wiring areas TA1 and TA2 may be areas including wiring structures for electrically connecting the memory cell structure CELL and the peripheral circuit structure PERI to each other. The gate electrodes 130 may not be disposed in the through wiring areas TA1 and TA2 . The through wiring areas TA1 and TA2 may include sacrificial insulating layers 118a and 118b disposed in parallel with the gate electrodes 130 . The sacrificial insulating layers 118a and 118b may be insulating layers remaining without being replaced by gate electrodes during the gate electrode forming process. The sacrificial insulating layers 118a and 118b may include an insulating material different from that of the interlayer insulating layers 120 , for example, silicon nitride.

The through wiring areas TA1 and TA2 include the sacrificial insulating layers 118a, the first inner insulating layer 109a, and the sacrificial insulating layers 118a and the first inner insulating layer 109a on the second region R2. The first through wiring area TA1 including the first through contact plug 174a passing through the sacrificial insulating layers 118a and 118b on the first region R1, the second inner insulating layer 109b, and A second through interconnection area TA2 including a second through contact plug 174b passing through the sacrificial insulating layers 118a and 118b and the second inner insulating layer 109b may be included.

In an exemplary embodiment, the through wiring areas TA1 and TA2 may further include a barrier structure disposed on the second substrate 101 to surround the through wiring areas TA1 and TA2 .

4 is a schematic partially enlarged view of a semiconductor device 100a according to example embodiments. 4 is a partially enlarged view corresponding to area 'A' of FIG. 1A .

Referring to FIG. 4 , the semiconductor device 100a may include buffer insulating structures 234 , 235 , 239 different from the semiconductor device 100 of FIG. 2 and upper connection patterns INT3 .

The upper surface of the insulating pattern 239 may be positioned at substantially the same level as the upper surface of the first buffer layer 234 , but the lower surface of the insulating pattern 239 may be positioned at a lower level than the lower surface of the first buffer layer 234 . That is, the third thickness t3 of the insulating pattern 239 may be greater than the first thickness t1 of the first buffer layer 234 . This may be a structure generated by forming the recess portion RP by etching relatively deeper in the process of forming the recess portion RP (refer to FIG. 9 ) for forming the insulating pattern 239 . Accordingly, the upper surface of the upper connection patterns INT3 may be positioned at a level lower than the upper surface of the first buffer layer 234 .

5 is a schematic partially enlarged view of a semiconductor device 100b according to example embodiments. FIG. 5 is a partially enlarged view corresponding to area 'A' of FIG. 1A .

Referring to FIG. 5 , the semiconductor device 100b may include through contact plugs 174 different from those of the semiconductor device 100 of FIG. 2 .

The through contact plugs 174 may include a protrusion 174p convexly protruding from the side contacting the buffer insulating structures 234 , 235 , and 239 .

In an exemplary embodiment, the through contact plugs 174 may include a first portion P1 surrounded by the second buffer layer 235 and a second portion P2 surrounded by the insulating pattern 239 . have. The protrusion 174p may be a portion of a side surface that convexly protrudes from the second portion P2 toward the insulating pattern 239 . That is, the second portion P2 may have a larger plan area than the area of the adjacent through contact plug 174 .

6 is a schematic partially enlarged view of a semiconductor device 100c according to example embodiments. FIG. 6 is a partially enlarged view corresponding to area 'A' of FIG. 1A .

Referring to FIG. 6 , the semiconductor device 100c may include through contact plugs 174 different from those of the semiconductor device 100 of FIG. 2 .

The through contact plugs 174 may be misaligned during a manufacturing process of a semiconductor device, so that side surfaces of the through contact plugs 174 may contact the first buffer layer 134 . That is, at a level at which the insulating pattern 239 is located, a portion of the side surfaces of the through contact plugs 174 is surrounded by the insulating pattern 239 , and the remaining part of the side surface is surrounded by the first buffer layer 234 . can be

The through contact plugs 174 may include a protrusion 174p convexly protruding from the side contacting the buffer insulating structures 234 , 235 , and 239 . However, unlike the protrusion 174p of FIG. 5 , the protrusion 174p may be formed only on a part of the side surface surrounded by the insulating pattern 239 and the protrusion 174p may not be formed on the other part of the side surface. This may be a structure in which the insulating pattern 239 and the first buffer layer 234 have different etching rates under specific etching conditions.

7 to 11 are schematic cross-sectional views and partially enlarged views for explaining a method of manufacturing the semiconductor device 100 according to example embodiments. 8B to 11 are enlarged views of a region corresponding to region 'C' of FIG. 8A .

Referring to FIG. 7 , circuit elements 220 are formed on a first substrate 201 , and first to third insulating layers 231 , 232 , 233 and first A buffer layer 234 may be formed.

First, device isolation layers 210 defining an active region are formed in a first substrate 201 , and a circuit gate dielectric layer 222 , a circuit gate electrode 225 , and a circuit gate are formed on the first substrate 201 . The circuit elements 220 may be formed by sequentially forming the capping layer 226 . The device isolation layers 210 may be formed by, for example, a shallow trench isolation (STI) process. The circuit gate dielectric layer 222 , the circuit gate electrode 225 , and the circuit gate capping layer 226 may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). have. The circuit gate dielectric layer 222 may be formed of silicon oxide, the circuit gate electrode 225 may be formed of at least one of polycrystalline silicon or metal silicide layer, and the circuit gate capping layer 226 may be formed of silicon nitride, but is not limited thereto. does not Next, a spacer layer 224 and source/drain regions 205 may be formed on both sidewalls of the circuit gate dielectric layer 222 and the circuit gate electrode 225 . In some embodiments, the spacer layer 224 may include a plurality of layers. Next, an ion implantation process may be performed to form the source/drain regions 205 .

Next, an insulating liner 217 covering the circuit elements 220 may be formed on the first substrate 201 . The insulating liner 217 may have a substantially uniform thickness and may be conformally formed.

Next, the first insulating layer 231 and the lower connection patterns INT1 buried in the first insulating layer 231 on the insulating liner 217 and having an upper surface coplanar with the upper surface of the first insulating layer 231 INT1 ) can be formed. The lower connection patterns INT1 may be electrically connected to the circuit elements 220 .

Next, the second insulating layer 232 and the second insulating layer 232 are buried on the first insulating layer 231 and the lower connection patterns INT1 and are coplanar with the upper surface of the second insulating layer 232 . Intermediate connection patterns INT2 having an upper surface may be formed. The intermediate connection patterns INT2 may be electrically connected to the lower connection patterns INT1 .

Next, the third insulating layer 233 may be formed on the second insulating layer 232 and the intermediate connection patterns INT2 , and the first buffer layer 234 may be formed on the third insulating layer 233 . have. For example, the third insulating layer 233 may be a silicon oxide layer, and the first buffer layer 234 may be a silicon nitride layer having a thickness smaller than that of the third insulating layer 233 .

8A and 8B , upper connection patterns INT3 penetrating the first buffer layer 234 may be formed.

An opening extending into the third insulating layer 233 may be formed through the first buffer layer 234 , and a conductive barrier layer BM and a metal material pattern PL may be sequentially formed in the opening. A conductive barrier layer BM and a metal material pattern PL are formed in the opening and on the first buffer layer 234 using an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process. After performing a chemical mechanical polishing (CMP) process, the barrier material and the metal material formed on the first buffer layer 234 may be removed. Accordingly, the upper surface of the first buffer layer 234 and the upper surface of the upper connection patterns INT3 may be positioned at substantially the same level.

The upper connection patterns INT3 may include a wiring portion INT_I and a via portion INT_V extending downward from a portion of the wiring portion INT_I. In an exemplary embodiment, the upper connection patterns INT3 may be formed by simultaneously etching regions corresponding to the wiring portion INT_I and the via portion INT_V to form an opening and depositing the barrier material and the metal material. have. However, in some embodiments, an opening is formed by etching a region corresponding to the via portion INT_V, the barrier material and the metal material are deposited, and then the region corresponding to the wiring portion INT_I is etched to form an opening. , and depositing the barrier material and the metal material to form upper connection patterns INT3 .

Referring to FIG. 9 , a portion of the upper connection patterns INT3 may be selectively removed to form the recess portion RP.

With respect to the first buffer layer 234 , only the upper connection patterns INT3 may be selectively removed to form the recessed portion RP recessed by a predetermined depth. In an exemplary embodiment, the recess portion RP may be formed by etching the upper connection patterns INT3 through a separate etching process, but in some embodiments, the barrier material and It may be formed by additionally performing a chemical mechanical polishing process for removing the metal material.

The recess portion RP may completely overlap the upper connection patterns INT3 on the upper connection patterns INT3 , but in some embodiments, a portion of the first buffer layer 234 is etched together to form the upper connection patterns. A portion that does not overlap with the INT3 may be included. In this case, the recess RP may have a width greater than the width in the x-direction of the upper connection patterns INT3 .

In this step, when the recess portion RP is formed to be relatively deeper than the lower surface level of the first buffer layer 234 , the semiconductor device 100a of FIG. 4 may be provided.

Referring to FIG. 10 , an insulating pattern 239 filling the recess RP may be formed.

After depositing an insulating material, for example, a silicon oxide layer conformally covering the recess portion RP and the first buffer layer 234 , a chemical mechanical polishing (CMP) process is performed to form the first buffer layer 234 on the first buffer layer 234 . The insulating pattern 239 may be formed by removing the insulating materials. Accordingly, the upper surface of the insulating pattern 239 may be positioned at substantially the same level as the upper surface of the first buffer layer 234 , and the side surface of the insulating pattern 239 may be covered by the first buffer layer 234 .

Referring to FIG. 11 , a second buffer layer 235 may be formed on the insulating pattern 239 and the first buffer layer 234 .

The second buffer layer 235 may conformally cover the insulating pattern 239 and the first buffer layer 234 by performing a deposition process, for example, an atomic layer deposition or a chemical vapor deposition process.

In the deposition process, a conductive material of the upper connection patterns INT3 or a material remaining in the process may be diffused, thereby causing a bridging defect. However, in the deposition process, the insulating pattern 239 is formed on the upper connection patterns INT3 to protect the upper connection patterns INT3 , so that the bridge defect problem may be improved.

Next, referring to FIGS. 1A and 1B , the fourth insulating layer 236 is formed on the second buffer layer 235 to form the peripheral circuit structure PERI, and the same as described with reference to FIGS. 1A to 3 . The same memory cell structure CELL and through contact plugs 174 may be formed.

The through contact plugs 174 perform an etching process to form contact holes penetrating the second buffer layer 235 and the insulating pattern 239 , and then perform a cleaning process to remove residues from the etching process. and can be formed by filling a conductive material. In the cleaning process, a portion of the insulating pattern 239 may be removed together. However, since the insulating pattern 239 is selectively formed only on the upper connection patterns INT3 , it is possible to provide a semiconductor device having an improved mold tear problem. For example, even if the entire insulating pattern 239 is removed in the cleaning process, a mold tearing phenomenon may be prevented by the first buffer layer 234 of a nitride-based type different from the insulating pattern 239 .

12 is a diagram schematically illustrating a data storage system including a semiconductor device according to example embodiments.

Referring to FIG. 12 , the data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100 . The data storage system 1000 may be a storage device including one or a plurality of semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be a solid state drive device (SSD) including one or a plurality of semiconductor devices 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device. .

The semiconductor device 1100 may be a nonvolatile memory device, for example, the NAND flash memory device described above with reference to FIGS. 1 to 6 . The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In example embodiments, the first structure 1100F may be disposed next to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110 , a page buffer 1120 , and a logic circuit 1130 . The second structure 1100S includes a bit line BL, a common source line CSL, word lines WL, first and second gate upper lines UL1 and UL2, and first and second gate lower lines. It may be a memory cell structure including the memory cell strings CSTR between the bits LL1 and LL2 and the bit line BL and the common source line CSL.

In the second structure 1100S, each of the memory cell strings CSTR includes lower transistors LT1 and LT2 adjacent to the common source line CSL, and upper transistors UT1 adjacent to the bit line BL. UT2) and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be variously modified according to embodiments.

In example embodiments, the upper transistors UT1 and UT2 may include a string select transistor, and the lower transistors LT1 and LT2 may include a ground select transistor. The gate lower lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, and the gate upper lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

In example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT1 may be used for an erase operation of erasing data stored in the memory cell transistors MCT using the GIDL phenomenon.

The common source line CSL, the first and second gate lower lines LL1 and LL2, the word lines WL, and the first and second gate upper lines UL1 and UL2 are connected to the first structure ( It may be electrically connected to the decoder circuit 1110 through first connection wires 1115 extending from the inside 1100F to the second structure 1100S. The bit lines BL may be electrically connected to the page buffer 1120 through second connection lines 1125 extending from the first structure 110F to the second structure 1100S.

In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by the logic circuit 1130 . The semiconductor device 1000 may communicate with the controller 1200 through the input/output pad 1101 electrically connected to the logic circuit 1130 . The input/output pad 1101 may be electrically connected to the logic circuit 1130 through an input/output connection line 1135 extending from the first structure 1100F to the second structure 1100S.

The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In some embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100 , and in this case, the controller 1200 may control the plurality of semiconductor devices 1000 .

The processor 1210 may control the overall operation of the data storage system 1000 including the controller 1200 . The processor 1210 may operate according to a predetermined firmware, and may access the semiconductor device 1100 by controlling the NAND controller 1220 . The NAND controller 1220 may include a NAND interface 1221 that handles communication with the semiconductor device 1100 . Through the NAND interface 1221 , a control command for controlling the semiconductor device 1100 , data to be written to the memory cell transistors MCT of the semiconductor device 1100 , and memory cell transistors ( Data to be read from the MCT) may be transmitted. The host interface 1230 may provide a communication function between the data storage system 1000 and an external host. When receiving a control command from an external host through the host interface 1230 , the processor 1210 may control the semiconductor device 1100 in response to the control command.

13 is a schematic perspective view of a data storage system including a semiconductor device according to an exemplary embodiment.

13, a data storage system 2000 according to an exemplary embodiment of the present invention includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and DRAM 2004 . The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 by wiring patterns 2005 formed on the main board 2001 .

The main board 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on a communication interface between the data storage system 2000 and the external host. In example embodiments, the data storage system 2000 includes an M-Phy for Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), Universal Flash Storage (UFS), etc. can communicate with an external host according to any one of the interfaces of In example embodiments, the data storage system 2000 may operate by power supplied from an external host through the connector 2006 . The data storage system 2000 may further include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the controller 2002 and the semiconductor package 2003 .

The controller 2002 may write data to or read data from the semiconductor package 2003 , and may improve the operating speed of the data storage system 2000 .

The DRAM 2004 may be a buffer memory for mitigating a speed difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the data storage system 2000 may operate as a kind of cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package 2003 . When the data storage system 2000 includes the DRAM 2004 , the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003 .

The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b spaced apart from each other. Each of the first and second semiconductor packages 2003a and 2003b may be a semiconductor package including a plurality of semiconductor chips 2200 . Each of the first and second semiconductor packages 2003a and 2003b includes the package substrate 2100 , the semiconductor chips 2200 on the package substrate 2100 , and adhesive layers 2300 disposed on lower surfaces of the semiconductor chips 2200 , respectively. ), a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100. may include

The package substrate 2100 may be a printed circuit board including package upper pads 2130 . Each semiconductor chip 2200 may include an input/output pad 2210 . The input/output pad 2210 may correspond to the input/output pad 1101 of FIG. 12 . Each of the semiconductor chips 2200 may include gate stack structures 3210 and channel structures 3220 . Each of the semiconductor chips 2200 may include the semiconductor device described above with reference to FIGS. 1 to 6 .

In example embodiments, the connection structure 2400 may be a bonding wire electrically connecting the input/output pad 2210 and the package upper pads 2130 . Accordingly, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other by a bonding wire method, and may be electrically connected to the package upper pads 2130 of the package substrate 2100 and may be electrically connected. According to embodiments, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be formed through a through-electrode (TSV) instead of the bonding wire-type connection structure 2400 . It may be electrically connected to each other by a connection structure comprising a.

In example embodiments, the controller 2002 and the semiconductor chips 2200 may be included in one package. In an exemplary embodiment, the controller 2002 and the semiconductor chips 2200 are mounted on a separate interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chips are formed by wiring formed on the interposer substrate. 2200 may be connected to each other.

14 is a cross-sectional view schematically illustrating a semiconductor package according to an exemplary embodiment. 14 illustrates an exemplary embodiment of the semiconductor package 2003 of FIG. 13 , and conceptually shows a region cut along the cutting line I-I' of the semiconductor package 2003 of FIG. 13 .

Referring to FIG. 14 , in the semiconductor package 2003 , the package substrate 2100 may be a printed circuit board. The package substrate 2100 is disposed on the package substrate body 2120 , the package upper pads 2130 (refer to FIG. 13 ) disposed on the upper surface of the package substrate body 2120 , and the lower surface of the package substrate body 2120 . lower pads 2125 exposed through the lower surface or through the lower surface, and internal wirings 2135 electrically connecting the upper pads 2130 and the lower pads 2125 in the package substrate body 2120. can The upper pads 2130 may be electrically connected to the connection structures 2400 . The lower pads 2125 may be connected to the wiring patterns 2005 of the main board 2010 of the data storage system 2000 as shown in FIG. 13 through conductive connectors 2800 .

Each of the semiconductor chips 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 that are sequentially stacked on the semiconductor substrate 3010 . The first structure 3100 may include a peripheral circuit region including peripheral wirings 3110 . The second structure 3200 includes a common source line 3205 , a gate stack structure 3210 on the common source line 3205 , channel structures 3220 passing through the gate stack structure 3210 , isolation regions, and a memory channel. bit lines 3240 electrically connected to the structures 3220 , and gate contact plugs 3235 electrically connected to the word lines WL (refer to FIG. 12 ) of the gate stacked structure 3210 . can As described above with reference to FIGS. 1 to 6 , the isolation insulating structures 234 , 235 , and 239 in each of the semiconductor chips 2200 may separate the upper connection patterns INT3 from the fourth insulating layer 236 . and the first buffer layer 234 may cover the side surface of the insulating pattern 239 .

Each of the semiconductor chips 2200 may include a through wiring 3245 electrically connected to the peripheral wirings 3110 of the first structure 3100 and extending into the second structure 3200 . The through wiring 3245 may be disposed outside the gate stacked structure 3210 , and may be further disposed to pass through the gate stacked structure 3210 . Each of the semiconductor chips 2200 may further include an input/output pad 2210 (refer to FIG. 13 ) electrically connected to the peripheral wirings 3110 of the first structure 3100 .

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited by the appended claims. Accordingly, various types of substitutions, modifications and changes and combinations of embodiments will be possible by those of ordinary skill in the art within the scope without departing from the spirit of the present invention described in the claims, and this is also the present invention will be said to be within the scope of

CELL: memory cell structure PERI: peripheral circuit structure
INT: circuit wiring structure INT3: upper connection patterns
CH: channel structure GS: laminate structure
GS1: lower stacked structure GS2: upper stacked structure
MS: separation structures SS: upper separation structures
101: second substrate 102, 104: horizontal conductive layer
110: horizontal insulating layers 118a, 118b: sacrificial insulating layers
120a, 120b: interlayer insulating layers 130a, 130b: gate electrodes
140: channel layer 174: through contact plug
201: first substrate 220: circuit elements
230: peripheral region structure 234: first buffer layer
235: second buffer layer 239: insulating pattern

Claims (10)

A circuit wiring structure including a substrate, a circuit element on the substrate, connection patterns electrically connected to the circuit element on the substrate and arranged at different height levels, and a periphery covering the circuit element and the circuit wiring structure on the substrate a peripheral circuit structure comprising a region insulating structure;
Gate electrodes disposed on the peripheral circuit structure and stacked apart from each other in a first direction perpendicular to the substrate, a channel structure penetrating the gate electrodes, and an upper portion electrically connected to the channel structure on the channel structure a memory cell structure including wiring; and
a through contact plug electrically connecting at least one of the gate electrodes and the upper wiring to at least one of the connection patterns;
the connection patterns include upper connection patterns in contact with the through contact plug;
The peripheral region insulating structure includes a first lower insulating layer covering the circuit element, a second lower insulating layer on the first lower insulating layer, and a buffer insulating structure between the first and second lower insulating layers,
The buffer insulating structure includes an insulating pattern on the upper connection pattern, a first buffer layer disposed on the first lower insulating layer and covering a side surface of the insulating pattern, and a second buffer layer on the first buffer layer and the insulating pattern semiconductor device.
According to claim 1,
The upper surface of the first buffer layer is located at a level higher than the upper surface of the upper connection pattern,
The first buffer layer covers a portion of a side surface of the upper connection pattern and a side surface of the insulating pattern.
According to claim 1,
A top surface of the insulating pattern is positioned at the same level as a top surface of the first buffer layer.
According to claim 1,
The upper connection pattern is spaced apart from the second buffer layer by the insulating pattern.
According to claim 1,
The upper connection pattern includes a plurality of upper connection patterns spaced apart from each other,
The insulating pattern includes a plurality of insulating layers in contact with the upper surfaces of each of the plurality of upper connection patterns,
The plurality of insulating layers are spaced apart from each other by the first buffer layer.
According to claim 1,
The through contact plug,
a first portion surrounded by the second buffer layer; and
and a second portion surrounded by the insulating pattern and spaced apart from the first buffer layer.
7. The method of claim 6,
The second portion of the through contact plug has a side convexly protruding in a direction toward the insulating pattern.
According to claim 1,
The insulating pattern may include a material different from that of the first and second buffer layers.
According to claim 1,
The first and second buffer layers include silicon nitride or a nitride-based material,
The insulating pattern is a semiconductor device including silicon oxide.
A circuit wiring structure including a substrate, a circuit element on the substrate, connection patterns electrically connected to the circuit element on the substrate and arranged at different height levels, and a periphery covering the circuit element and the circuit wiring structure on the substrate a substructure comprising a region insulating structure;
an upper structure disposed on the lower structure and including an upper wiring; and
a through contact plug electrically connecting the upper wiring and the connection patterns;
the connection patterns include upper connection patterns in contact with the through contact plug;
The peripheral region insulating structure includes a first lower insulating layer covering the circuit element, a second lower insulating layer on the first lower insulating layer, and a buffer insulating structure between the first and second lower insulating layers,
The buffer insulating structure includes an insulating pattern on the upper connection pattern, a first buffer layer disposed on the first lower insulating layer and covering a side surface of the insulating pattern, and a second buffer layer on the first buffer layer and the insulating pattern, ,
The insulating pattern includes silicon oxide,
The first and second buffer layers include silicon nitride.

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