KR20220159313A - Semiconductor devices and data storage systems including the same - Google Patents

Abstract

A semiconductor device according to an embodiment of the present invention comprises: a first substrate structure including a substrate, circuit elements disposed on the substrate, and first bonding metal layers disposed on the circuit elements; and a second substrate structure connected to the first substrate structure on the first substrate structure and having a first region and a second region. The second substrate structure comprises: a plate layer; gate electrodes stacked under the plate layer to be spaced apart from each other in a first direction vertical to the lower surface of the plate layer and extended to different lengths in a second direction on the second region to form pad regions of different levels; channel structures, on the first region, penetrating the gate electrodes, extended in the first direction, and including channel layers; vertical structures, on the second region, penetrating the pad regions of the gate electrodes and extended in the first direction; input/output pad structures at least partially disposed on the plate layer; and second bonding metal layers disposed under the gate electrodes and connected to the first bonding metal layers. The vertical structures include: gate contact plugs connected to the gate electrodes on the pad regions; input/output contact plugs connected to the input/output pad structures; and dummy vertical structures each including an insulation layer, The pad regions include a first pad region. At least one of the gate contact plugs and at least one of the input/output contact plugs are disposed to penetrate the first pad region. The degree of integration can be enhanced.

Description

Semiconductor device and data storage system including the same

The present invention relates to a semiconductor device and a data storage system including the same.

In a data storage system requiring data storage, a semiconductor device capable of storing high-capacity data is required. Accordingly, a method for increasing the data storage capacity of the semiconductor device is being studied. For example, as one of the methods for increasing the data storage capacity of a semiconductor device, a semiconductor device including three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells has been proposed.

One of the technical problems to be achieved by the present invention is to provide a semiconductor device with an improved degree of integration.

One of the technical problems to be achieved by the present invention is to provide a data storage system including a semiconductor device having an improved degree of integration.

A semiconductor device according to example embodiments includes a first substrate structure including a substrate, circuit elements disposed on the substrate, and first bonding metal layers disposed on the circuit elements, and the first substrate structure. connected to the first substrate structure on the top and including a second substrate structure having a first region and a second region, the second substrate structure comprising: a plate layer, perpendicular to a lower surface of the plate layer below the plate layer; gate electrodes spaced apart from each other along a first direction and extending to different lengths along a second direction in the second region to form pad regions of different levels; in the first region, the gate electrodes Channel structures penetrating and extending along the first direction and each including a channel layer, vertical structures penetrating pad areas of the gate electrodes in the second region and extending along the first direction, the plate layer input/output pad structures having at least a portion disposed thereon, and second bonding metal layers disposed below the gate electrodes and connected to the first bonding metal layers, the vertical structures comprising the gate electrodes in the pad regions. dummy vertical structures each including gate contact plugs connected to electrodes, input/output contact plugs connected to the input/output pad structures, and an insulating layer, wherein the pad areas include a first pad area; At least one of the gate contact plugs and at least one of the input/output contact plugs may be disposed to pass through the first pad region.

A data storage system according to example embodiments includes a first substrate structure including circuit elements and first bonding metal layers, gate electrodes, second bonding metal layers connected to the first bonding metal layers, and the A semiconductor storage device including an input/output pad electrically connected to circuit elements and including a second substrate structure having a first region and a second region, and electrically connected to the semiconductor storage device through the input/output pad, and a controller for controlling the semiconductor storage device, wherein the second substrate structure is spaced apart from each other and stacked along a first direction perpendicular to a lower surface of the plate layer below the plate layer, and the second substrate structure gate electrodes extending from a region to different lengths along a second direction to form pad regions; a channel structure in the first region, penetrating the gate electrodes and extending along the first direction, each including a channel layer; gate contact plugs, in the second region, connected to the gate electrodes in the pad regions and extending along the first direction, penetrating the pad regions in the second region and extending in the first direction; input/output contact plugs extending along, in the second region, dummy vertical structures penetrating the pad regions and extending along the first direction, each including an insulating layer, and disposed below the gate electrodes and Second bonding metal layers may be connected to the first bonding metal layers, and upper ends of the gate contact plugs, the input/output contact plugs, and the dummy vertical structures may be positioned on a lower surface of the plate layer.

In a structure in which two or more substrate structures are bonded, gate contact plugs, input/output contact plugs, and dummy vertical structures are arranged to pass through gate pads, thereby providing a semiconductor device with improved integration and a data storage system including the same. have.

The various beneficial advantages and effects of the present invention are not limited to the above, and will be more easily understood in the process of describing specific embodiments of the present invention.

1A and 1B are schematic plan views and partially enlarged views of a semiconductor device according to example embodiments.
2A and 2B are schematic cross-sectional and partially enlarged views of a semiconductor device according to example embodiments.
3A to 3C are schematic partial enlarged views of a semiconductor device according to example embodiments.
4A and 4B are schematic partial enlarged views of a semiconductor device according to example embodiments.
5A to 5J are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments.
6 is a diagram schematically illustrating a data storage system including a semiconductor device according to example embodiments.
7 is a perspective view schematically illustrating a data storage system including a semiconductor device according to an exemplary embodiment.
8 is a schematic cross-sectional view of a semiconductor package according to an exemplary embodiment.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described as follows. Hereinafter, terms such as 'upper', 'top', 'top', 'bottom', 'bottom', 'bottom', and 'side' are indicated by reference numerals and are based on drawings, except where otherwise indicated. It can be understood as referring to.

1A and 1B are schematic plan views and partially enlarged views of a semiconductor device according to example embodiments. FIG. 1B is an enlarged view of area 'A' of FIG. 1A.

2A and 2B are schematic cross-sectional and partially enlarged views of a semiconductor device according to example embodiments. FIG. 2B is an enlarged view of area 'B' of FIG. 2A.

Referring to FIGS. 1A to 2B , the semiconductor device 100 includes first and second substrate structures S1 and S2 stacked vertically. The first substrate structure S1 may include a peripheral circuit area. The second substrate structure S2 may include a memory cell area. 1A and 1B show a plane viewed from the interface of the first and second substrate structures S1 and S2 toward the second substrate structure S2, and the cell contact plugs 170 and the cell wiring. It is shown except for some configurations including lines 180 .

The first substrate structure S1 includes a substrate 201, source/drain regions 205 and device isolation layers 207 in the substrate 201, and circuit elements 220 disposed on the substrate 201. , circuit contact plugs 270, circuit wiring lines 280, peripheral region insulating layer 290, first bonding vias 295, first bonding metal layers 298, and first bonding insulating layer ( 299) may be included.

The substrate 201 may have an upper surface extending in the x and y directions. Device isolation layers 207 may be formed on the substrate 201 to define an active region. Source/drain regions 205 containing impurities may be disposed in a portion of the active region. The substrate 201 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the substrate 201 may be provided as a single crystal bulk wafer.

The circuit elements 220 may include planar transistors. Each of the circuit elements 220 may include a circuit gate dielectric layer 222 , spacer layers 224 , and a circuit gate electrode 225 . Source/drain regions 205 may be disposed in the substrate 201 at both sides of the circuit gate electrode 225 .

A peripheral region insulating layer 290 may be disposed on the circuit element 220 on the substrate 201 . The circuit contact plugs 270 and the circuit wiring lines 280 may constitute a first wiring structure of the first substrate structure S1. The circuit contact plugs 270 may have a cylindrical shape and may be connected to the source/drain regions 205 by penetrating the peripheral insulating layer 290 . Electrical signals may be applied to the circuit element 220 through the circuit contact plugs 270 . In an area not shown, circuit contact plugs 270 may also be connected to the circuit gate electrode 225 . The circuit wiring lines 280 may be connected to the circuit contact plugs 270, have a line shape, and may be arranged in a plurality of layers. In example embodiments, the number of layers of the circuit contact plugs 270 and the circuit wiring lines 280 may be variously changed.

The first bonding vias 295, the first bonding metal layers 298, and the first bonding insulating layer 299 constitute a first bonding structure, and are formed on a part of the uppermost circuit wiring lines 280. can be placed. The first bonding vias 295 may have a cylindrical shape, and the first bonding metal layers 298 may have a line shape. Top surfaces of the first bonding metal layers 298 and top surfaces of the first bonding insulating layer 299 may be exposed as a top surface of the first substrate structure S1 . The first bonding vias 295, the first bonding metal layers 298, and the first bonding insulating layer 299 are bonding structures or bonding layers of the first substrate structure S1 and the second substrate structure S2. can function Also, the first bonding vias 295 and the first bonding metal layers 298 may provide an electrical connection path with the second substrate structure S2. In example embodiments, some of the first bonding metal layers 298 may be disposed only for bonding without being connected to the lower circuit wiring lines 280 . The first bonding vias 295 and the first bonding metal layers 298 may include a conductive material, such as copper (Cu). The first bonding insulating layer 299 may be disposed around the first bonding metal layers 298 . The first bonding insulating layer 299 may also function as a diffusion barrier layer of the first bonding metal layers 298, and may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN. have.

The second substrate structure S2 may have a first region R1 and a second region R2, a plate layer 101, gate electrodes 130 stacked on a lower surface of the plate layer 101, interlayer insulating layers 120 alternately stacked with the gate electrodes 130, first and second separation regions MS1, MS2a, and MS2b extending in one direction through the gate electrodes 130; Channel structures CH disposed to penetrate the gate electrodes 130 in the first region R1, and vertical channels disposed to pass through the plate layer 101 and the gate electrodes 130 in the second region R2. structures 150 and input/output pad structures 210 . The second substrate structure S2 is a second wiring structure, and further includes cell contact plugs 170 and cell wiring lines 180 connected to the gate electrodes 130 in the second region R2. , as the second bonding structure, second bonding vias 195 , second bonding metal layers 198 , and a second bonding insulating layer 199 may be further included. The second substrate structure S2 includes first contact insulating layers 160, upper contact insulating layers 161, second contact insulating layers 162, a cell region insulating layer 190, an upper interlayer insulating layer ( 202), and a passivation layer 204 may be further included.

The first region R1 is a region in which the gate electrodes 130 are vertically stacked and the channel structures CH are disposed, and may be a region in which memory cells are disposed. The second region R2 is a region in which the gate electrodes 130 extend to different lengths to form pad regions PAD at different levels, and electrically connects the memory cells to the first substrate structure S1. It may correspond to the area for The second region R2 may be positioned at at least one end of the first region R1 in at least one direction, for example, the x direction.

The plate layer 101 may have upper surfaces extending in the x and y directions. The plate layer 101 may function as a common source line of the semiconductor device 100 . The plate layer 101 may include a conductive material. For example, the plate layer 101 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The plate layer 101 may further include impurities. The plate layer 101 may be provided with a polycrystalline semiconductor layer such as a polycrystalline silicon layer or an epitaxial layer.

The gate electrodes 130 may be vertically spaced apart and stacked on the lower surface of the plate layer 101 to form a stacked structure together with the interlayer insulating layers 120 . The stacked structure may include lower and upper stacked structures that are vertically stacked and surround the first and second channel structures CH1 and CH2, respectively. However, according to embodiments, the laminated structure may be formed of a single laminated structure.

The gate electrodes 130 include at least one lower gate electrode 130L forming a gate of a ground select transistor, memory gate electrodes 130M forming a plurality of memory cells, and upper gate electrodes forming gates of string select transistors. (130U). Here, the lower and upper stacked structures, the lower gate electrode 130L, and the upper gate electrodes 130U may be referred to as "lower" and "upper" based on a direction during a manufacturing process. The number of memory gate electrodes 130M constituting memory cells may be determined according to the capacity of the semiconductor device 100 . According to exemplary embodiments, the number of upper and lower gate electrodes 130U and 130L may be 1 to 4 or more, and may have the same structure as or a different structure from the memory gate electrodes 130M. In example embodiments, the gate electrodes 130 are disposed under the upper gate electrodes 130U and/or on the lower gate electrode 130L to prevent a gate induced drain leakage (GIDL) phenomenon. A gate electrode 130 constituting an erase transistor used for an erase operation may be further included. Also, some of the gate electrodes 130 , eg, memory gate electrodes 130M adjacent to the upper or lower gate electrodes 130U and 130L may be dummy gate electrodes.

As shown in FIG. 1A , the gate electrodes 130 are separated from each other in the y direction by first separation regions MS1 continuously extending from the first region R1 and the second region R2. can be placed. The gate electrodes 130 between the pair of first separation regions MS1 may form one memory block, but the range of the memory block is not limited thereto. Some of the gate electrodes 130, eg, the memory gate electrodes 130M, may each form one layer within one memory block.

The gate electrodes 130 are vertically spaced apart from each other and stacked on the first region R1 and the second region R2, and extend with different lengths from the first region R1 to the second region R2. In a part of the second region R2, a stepped structure may be formed. The gate electrodes 130 may be arranged to have a stepped structure in the y-direction as well. Due to the stepped structure, in the gate electrodes 130, the upper gate electrode 130 extends longer than the lower gate electrode 130, so that the interlayer insulating layers 120 and the other gate electrodes 130 are below the gate electrodes 130. Each of the lower surfaces may have areas exposed, and the areas may be referred to as pad areas PAD. In each gate electrode 130 , the pad area PAD may be an area including an end of the gate electrode 130 along the x direction. The pad region PAD may correspond to one region of the gate electrode 130 positioned at the lowermost part of each region among the gate electrodes 130 constituting the stacked structure in the second region R2 . The gate electrodes 130 may be physically and electrically connected to the gate contact plugs 152 of the vertical structures 150 in the pad regions PAD, respectively. The gate electrodes 130 may have an increased thickness in the pad areas PAD.

The gate electrodes 130 may include a metal material, such as tungsten (W). Depending on the embodiment, the gate electrodes 130 may include polycrystalline silicon or a metal silicide material. In example embodiments, the gate electrodes 130 may further include a diffusion barrier. For example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), or titanium nitride (TiN). , or a combination thereof.

The interlayer insulating layers 120 may be disposed between the gate electrodes 130 . Like the gate electrodes 130 , the interlayer insulating layers 120 may be spaced apart from each other in a direction perpendicular to the lower surface of the plate layer 101 and may be disposed to extend in the x direction. The interlayer insulating layers 120 may include an insulating material such as silicon oxide or silicon nitride.

The first and second isolation regions MS1 , MS2a , and MS2b may pass through the gate electrodes 130 and extend along the x direction. The first and second separation regions MS1 , MS2a , and MS2b may be disposed parallel to each other. The first and second separation regions MS1 , MS2a , and MS2b may pass through the entirety of the gate electrodes 130 stacked on the plate layer 101 and be connected to the plate layer 101 . The first separation regions MS1 extends as one along the x direction, and the second separation regions MS2a and MS2b intermittently extend between the pair of first separation regions MS1 or only in a partial region. can be placed. For example, the second central separation regions MS2a may extend as one in the first region R1 and intermittently extend in the x direction in the second region R2. The second auxiliary separation regions MS2b may be disposed only in the second region R2 and intermittently extend along the x direction. However, in embodiments, the arrangement order and number of the first and second separation regions MS1 , MS2a , and MS2b are not limited to those shown in FIG. 1A . The first and second separation regions MS1 , MS2a , and MS2b may include an insulating material, for example, silicon oxide, silicon nitride, or silicon oxynitride.

The channel structures CH form one memory cell string, and may be spaced apart from each other while forming rows and columns on the lower surface of the plate layer 101 in the first region R1 . The channel structures CH may be arranged to form a lattice pattern or may be arranged in a zigzag shape in one direction. The channel structures CH may have a columnar shape and may have inclined side surfaces such that the width becomes narrower closer to the plate layer 101 according to an aspect ratio. In example embodiments, some of the channel structures CH may be dummy channels that do not substantially form memory cell strings. For example, some of the channel structures CH disposed adjacent to the second region R2 may be dummy channels. can

Each of the channel structures CH may have a shape in which first and second channel structures CH1 and CH2 penetrating the lower and upper stacked structures of the gate electrodes 130 are connected, and have a width in the connection region. may have a bent part due to a difference or change of However, according to embodiments, the number of channel structures stacked along the z-direction may be variously changed.

Each of the channel structures CH may include a channel layer 140 , a gate dielectric layer 145 , a channel filling insulating layer 147 , and a channel pad 149 disposed in a channel hole. The channel layer 140 may be formed in an annular shape surrounding the inner channel filling insulating layer 147, but may have a columnar shape such as a cylinder or a prism without the channel filling insulating layer 147 according to an embodiment. may be The channel layer 140 may include a semiconductor material such as polycrystalline silicon or single crystal silicon. The channel layer 140 may be exposed through the top and connected to the plate layer 101 .

The gate dielectric layer 145 may be disposed between the gate electrodes 130 and the channel layer 140 . Although not specifically illustrated, the gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a blocking layer sequentially stacked from the channel layer 140 . The tunneling layer may tunnel charges into the charge storage layer, and may include, for example, silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), or a combination thereof. have. The charge storage layer may be a charge trap layer or a floating gate conductive layer. The blocking layer may include silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. In example embodiments, at least a portion of the gate dielectric layer 145 may extend in a horizontal direction along the gate electrodes 130 .

The channel pad 149 may be disposed only on the lower end of the lower second channel structure CH2 . The channel pad 149 may include, for example, doped polycrystalline silicon.

The channel layer 140 , the gate dielectric layer 145 , and the channel filling insulating layer 147 may be connected to each other between the first channel structure CH1 and the second channel structure CH2 . An interlayer insulating layer 120 having a relatively thick thickness may be disposed between the first channel structure CH1 and the second channel structure CH2. However, the thickness and shape of the interlayer insulating layers 120 may be variously changed in the embodiments.

The vertical structures 150 may pass through the pad regions PAD of the gate electrodes 130 in the second region R2 . As shown in FIG. 1A , the vertical structures 150 may be regularly arranged in the whole or at least a part of the second region R2 and may be arranged in a regular pattern. For example, in one pad area PAD having a minimum size, the vertical structures 150 may be respectively disposed in four corner areas and a central area, and a total of five may be disposed. The vertical structures 150 may be arranged to extend from the bottom through the pad areas PAD to the plate layer 101 through the area where the gate electrodes 130 form a stepped structure in the second area R2. can The vertical structures 150 may have inclined side surfaces such that their width narrows as they are closer to the plate layer 101 .

The vertical structures 150 may include gate contact plugs 152 , input/output contact plugs 154 , and dummy vertical structures 156 . The gate contact plugs 152 may electrically connect the gate electrodes 130 to circuit wiring lines 280 in the first substrate structure S1 . The gate contact plugs 152 may be physically and electrically connected to the gate electrodes 130 and each pad area PAD, and may apply electrical signals to the gate electrodes 130 . The input/output contact plugs 154 may electrically connect the circuit elements 220 of the first substrate structure S1 and the input/output pad structures 210 . The dummy vertical structures 156 are disposed in the second region R2 together with the gate contact plugs 152 and the input/output contact plugs 154 to form interlayer insulating layers ( 120) may support the mold structure.

The gate contact plugs 152 , the input/output contact plugs 154 , and the dummy vertical structures 156 may be disposed on the same or similar levels. Lower ends of the gate contact plugs 152 , the input/output contact plugs 154 , and the dummy vertical structures 156 may be located on substantially the same level. Upper ends of the gate contact plugs 152, input/output contact plugs 154, and dummy vertical structures 156 are located on the lower surface of the plate layer 101, for example, on the lower surface or within the plate layer 101. can do.

In FIG. 1B , three pad regions PAD _n+1 , PAD _n , and PAD _n−1 successively positioned between the first and second separation regions MS1 , MS2a , and MS2b adjacent to each other along the y direction are shown in FIG. The arrangement form of the vertical structures 150 in ) is shown in detail. Each of the gate contact plugs 152, the input/output contact plugs 154, and the dummy vertical structures 156 is a central area or a corner area in each pad area (PAD _n+1 , PAD _n , PAD _n−1 ). can be placed in Through-holes in which the gate contact plugs 152 , the input/output contact plugs 154 , and the dummy vertical structures 156 are disposed may have the same or similar sizes in a plan view.

For example, one gate contact plug 152 may be disposed in each of the pad regions PAD _n+1 , PAD _n , and PAD _n−1 . The input/output contact plug 154 may be disposed in some of the pad regions PAD _n+1 , PAD _n , and PAD _n−1 . A plurality of dummy vertical structures 156 may be disposed in each of the pad areas PAD _n+1 , PAD _n , and PAD _n−1 , but are not limited thereto. For example, as in some pad regions PAD _n and PAD _n−1 , the gate contact plug 152 and the input/output contact plug 154 may be disposed together in one pad region, and the dummy vertical structure (156) may be further arranged. However, in embodiments, specific arrangements of the gate contact plugs 152 , the input/output contact plugs 154 , and the dummy vertical structures 156 may be variously changed.

In this embodiment, the input/output contact plugs 154 may be disposed in the pad areas PAD to pass through the pad areas PAD together with the gate contact plugs 152 . Therefore, the degree of integration of the semiconductor device 100 can be improved compared to the case where the input/output contact plugs 154 are disposed outside the gate electrodes 130, for example, in an area where the gate electrodes 130 are not disposed. . In addition, since through-holes in which the gate contact plugs 152, the input/output contact plugs 154, and the dummy vertical structures 156 are disposed are formed together, the manufacturing process can be simplified.

The gate contact plugs 152, the input/output contact plugs 154, and the dummy vertical structures 156 may have different internal structures. As shown in FIG. 2B , the gate contact plugs 152 may have a shape extending horizontally from the pad areas PAD. The gate contact plugs 152 may be spaced apart from the gate electrodes 130 on the pad regions PAD by the first contact insulating layers 160 . The first contact insulating layers 160 may be disposed to be separated from each other along the z direction. Upper contact insulating layers 161 may be disposed on upper ends of the gate contact plugs 152 , thereby electrically separating them from the plate layer 101 .

Second contact insulating layers 162 surrounding the input/output contact plugs 154 may be included on side surfaces of the input/output contact plugs 154 . The second contact insulating layer 162 may be disposed to cover sidewalls of contact holes where the input/output contact plugs 154 are disposed. The second contact insulating layer 162 may be disposed to extend in the z direction between the input/output contact plug 154 and the gate electrodes 130 . The second contact insulating layers 162 may also extend to cover upper ends of the input/output contact plugs 154 .

The dummy vertical structures 156 may not be connected to the lower second wiring structure or may be connected to the dummy wiring structure. The dummy vertical structures 156 may be made of an insulating material. The dummy vertical structures 156 may not perform electrical functions within the semiconductor device 100 .

The first contact insulating layers 160, the upper contact insulating layers 161, the second contact insulating layers 162, and the dummy vertical structures 156 are made of an insulating material such as silicon oxide or silicon nitride. , or silicon oxynitride. The gate contact plugs 152 and the input/output contact plugs 154 are made of a conductive material, for example, doped silicon (Si), tungsten (W), aluminum (Al), copper (Cu), or tungsten nitride (WN). , tantalum nitride (TaN), titanium nitride (TiN), or combinations thereof.

The input/output pad structures 210 may be disposed on the input/output contact plugs 154 in the second region R2 . A plurality of input/output pad structures 210 may be spaced apart from each other in the second region R2 . However, the arrangement form of the input/output pad structures 210, the specific arrangement position and size on the second region R2 may be variously changed in the embodiments.

The input/output pad structures 210 may include input/output vias 212 on the input/output contact plugs 154 and input/output pads 214 on the input/output vias 212 . However, according to embodiments, the depth of the input/output vias 212 may be variously changed. For example, lower ends of the input/output vias 212 may be positioned within the plate layer 101 , and in this case, upper ends of the input/output contact plugs 154 may also be positioned within the plate layer 101 . In some embodiments, input/output vias 212 may be omitted. In this case, the input/output contact plugs 154 may be directly connected to the input/output pads 214 . The input/output pads 214 may be connected to an electrical connection structure, such as a signal transmission medium of a device such as a package in which the semiconductor device 100 is mounted, through a top surface.

The input/output vias 212 may have side surfaces that are inclined toward the plate layer 101 and narrow in width. The input/output pads 214 may have side surfaces inclined toward the plate layer 101 to widen. The input/output pad structures 210 may include a metal material, for example, tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), titanium nitride ( TiN), or a combination thereof.

The cell region insulating layer 190 may be disposed to cover the lower surface of the plate layer 101 and the gate electrodes 130 on the lower surface of the plate layer 101 . The upper interlayer insulating layer 202 may be disposed on the upper surface of the plate layer 101 and may surround at least a portion of the input/output pad structures 210 . The passivation layer 204 may be disposed on top surfaces of the input/output pads 214 . The passivation layer 204 may function as a layer protecting the semiconductor device 100 . The passivation layer 204 may have openings exposing at least a portion of the input/output pads 214 .

The cell region insulating layer 190, the upper interlayer insulating layer 202, and the passivation layer 204 may include at least one of an insulating material such as silicon oxide, silicon nitride, and silicon carbide. It may be made of a plurality of insulating layers according to the.

The second wiring structure includes cell contact plugs 170 and cell wiring lines 180 and may electrically connect the second substrate structure S2 to the first substrate structure S1.

The cell contact plugs 170 include first to third cell contact plugs 172, 174, and 176, and the cell wiring lines 180 include first and second cell wiring lines 182 and 184. can include The channel pads 149 , the gate contact plugs 152 , and the input/output contact plugs 154 may be connected to the first cell contact plugs 172 at the bottom. The first cell contact plugs 172 may be connected to the second cell contact plugs 174 at the bottom, and the second cell contact plugs 174 may be connected to the first cell wiring lines 182 at the bottom. . The third cell contact plugs 176 may vertically connect the first and second cell wiring lines 182 and 184 . The cell contact plugs 170 may have a cylindrical shape. The cell contact plugs 170 may have different lengths. For example, the first cell contact plugs 172 may have a relatively long length. In embodiments, the cell contact plugs 170 may have inclined side surfaces such that the width decreases as they are closer to the plate layer 101 and increases toward the first substrate structure S1 according to the aspect ratio. .

The first cell wiring lines 182 include bit lines of the first region R1 connected to the channel structures CH and wiring lines of the second region R2 disposed at the same height level as the bit lines. may include The second cell wiring lines 184 may be wiring lines disposed below the first cell wiring lines 182 . The cell wiring lines 180 may have a line shape extending in at least one direction. In example embodiments, the second cell wiring lines 184 may have a greater thickness than the first cell wiring lines 182 . The cell wiring lines 180 may have side surfaces that are inclined toward the plate layer 101 to become narrower.

The cell contact plugs 170 and the cell wiring lines 180 may be formed of, for example, tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), or titanium nitride. (TiN), or a combination thereof.

The second bonding vias 195 of the second bonding structure are disposed below the second cell wiring lines 184 and connected to the second cell wiring lines 184, and the second bonding vias 195 of the second bonding structure The bonding metal layers 198 may be connected to the second bonding vias 195 . Lower surfaces of the second bonding metal layers 198 and the second bonding insulating layer 199 may be exposed to the lower surface of the second substrate structure S2 . The second bonding metal layers 198 may be bonded and connected to the first bonding metal layers 298 of the first substrate structure S1, and the second bonding insulating layer 199 may be connected to the first bonding metal layers 298 of the first substrate structure S1. 1 may be bonded and connected to the bonding insulating layer 299 . The second bonding vias 195 and the second bonding metal layers 198 may include a conductive material, such as copper (Cu). The second bonding insulating layer 199 may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

The first and second substrate structures S1 and S2 include the bonding of the first bonding metal layers 298 and the second bonding metal layers 198 and the first bonding insulating layer 299 and the second bonding insulating layer ( 199) may be bonded. The bonding between the first bonding metal layers 298 and the second bonding metal layers 198 may be, for example, copper (Cu)-copper (Cu) bonding, and the first bonding insulating layer 299 and the second bonding. The bonding of insulating layer 199 may be dielectric-dielectric bonding, such as SiCN-SiCN bonding, for example. The first and second substrate structures S1 and S2 may be bonded by hybrid bonding including copper (Cu)-copper (Cu) bonding and dielectric-dielectric bonding.

3A to 3C are schematic partial enlarged views of a semiconductor device according to example embodiments. 3A to 3C show areas corresponding to FIG. 1B.

Referring to FIG. 3A , in the semiconductor device 100a , gate contact plugs 152 may be disposed in central regions of respective pad regions PADn+1 , PADn , and PADn−1 . The input/output contact plugs 154 may be disposed in corner regions of some of the pad regions PADn+1, PADn, and PADn−1. The dummy vertical structures 156 may be disposed in corner regions of the pad regions PADn+1, PADn, and PADn−1.

Referring to FIG. 3B , in the semiconductor device 100b, at least one of the input/output contact plugs 154 may be disposed in a central region of at least one of the pad regions PADn+1, PADn, and PADn−1. . The gate contact plugs 152 and the dummy vertical structures 156 may be disposed in a central region or a corner region of each of the pad regions PADn+1, PADn, and PADn−1.

As shown in FIGS. 3A and 3B , in embodiments, specific arrangements of the gate contact plugs 152 , the input/output contact plugs 154 , and the dummy vertical structures 156 may be variously changed.

Referring to FIG. 3C , in the semiconductor device 100c, some of the vertical structures 150 may be disposed to penetrate end portions of the gate electrodes 130 in the x direction. Accordingly, three vertical structures 150 may be disposed in a net number in each of the pad areas PADn+1, PADn, and PADn−1. In this embodiment, the gate contact plugs 152 may be disposed in the central region of each of the pad regions PADn+1, PADn, and PADn−1. The input/output contact plugs 154 may be disposed on end regions of some of the pad regions PADn+1, PADn, and PADn−1. The dummy vertical structures 156 may be disposed in end regions of at least some of the pad regions PADn+1 , PADn , and PADn−1 .

4A and 4B are schematic partial enlarged views of a semiconductor device according to example embodiments. 4a and 4b show the area corresponding to FIG. 1b.

Referring to FIG. 4A , in the semiconductor device 100d, at least some of the vertical structures 150 may have different sizes in a plan view. For example, the size D1 of the through holes in which the gate contact plugs 152 are disposed is larger than the size D2 of the through holes in which the input/output contact plugs 154 and the dummy vertical structures 156 are disposed. can

Referring to FIG. 4B , in the semiconductor device 100e, the gate contact plugs 152, the input/output contact plugs 154, and the dummy vertical structures 156, in a plan view, have different shapes according to an area in which they are disposed. can have For example, the vertical structures 150 may have a circular shape in central regions of the pad regions PADn+1, PADn, and PADn−1, and may have an elliptical shape or a similar shape in corner regions. . The diameter or maximum width D3 of the vertical structures 150 in the central region may be smaller than the diameter or maximum width D4 of the corner regions.

5A to 5J are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments.

Referring to FIG. 5A , a first substrate structure S1 including circuit elements 220 , first wiring structures, and a first bonding structure may be formed on a substrate 201 .

First, device isolation layers 207 may be formed in the substrate 201 , and then a circuit gate dielectric layer 222 and a circuit gate electrode 225 may be sequentially formed on the substrate 201 . The device isolation layers 207 may be formed by, for example, a shallow trench isolation (STI) process. The circuit gate dielectric layer 222 and the circuit gate electrode 225 may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 222 may be formed of silicon oxide, and the circuit gate electrode 225 may be formed of at least one of polycrystalline silicon or a metal silicide layer, but is not limited thereto. Next, a spacer layer 224 and source/drain regions 205 may be formed on both sidewalls of the circuit gate dielectric layer 222 and the circuit gate electrode 225 . According to embodiments, the spacer layer 224 may include a plurality of layers. Next, the source/drain regions 205 may be formed by performing an ion implantation process.

In the circuit contact plugs 270 of the first wiring structure and the first bonding vias 295 of the first bonding structure, a peripheral insulating layer 290 is partially formed, and then partially removed by etching, and a conductive material is formed. It can be formed by burying. The circuit wiring lines 280 of the first wiring structure and the first bonding metal layers 298 of the first bonding structure may be formed by, for example, depositing a conductive material and then patterning it. The first bonding metal layers 298 and the first bonding insulating layer 299 may be formed such that upper surfaces are exposed.

The peripheral region insulating layer 290 may include a plurality of insulating layers. A portion of the peripheral region insulating layer 290 may be formed in each step of forming the first wiring structure and the first bonding structure. A first bonding insulating layer 299 may be formed on the peripheral region insulating layer 290 . Through this step, the first substrate structure S1 may be prepared.

Referring to FIG. 5B , a manufacturing process of the second substrate structure S2 may be started. First, after the sacrificial insulating layers 118 and the interlayer insulating layers 120 are alternately stacked on the base substrate SUB, the channel sacrificial layers 129 may be formed.

The base substrate SUB is a layer removed through a subsequent process and may be a semiconductor substrate such as silicon (Si).

First, in order to form a lower stacked structure, sacrificial insulating layers 118 and interlayer insulating layers 120 may be alternately stacked in an area where the first channel structures CH1 (see FIG. 2A ) are disposed. The sacrificial insulating layers 118 may be replaced with the gate electrodes 130 (see FIG. 2A ) through a subsequent process. The sacrificial insulating layers 118 may be formed of a material that can be etched with etch selectivity with respect to the interlayer insulating layers 120 . For example, the interlayer insulating layer 120 may be formed of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layers 118 may include an interlayer insulating layer 120 selected from silicon, silicon oxide, silicon carbide, and silicon nitride. and may be made of other materials. In embodiments, the thickness of the interlayer insulating layers 120 and the number of films constituting them may be variously changed from those shown.

Next, the sacrificial insulating layers 118 and the interlayer insulating layers 120 are applied so that the upper sacrificial insulating layers 118 extend shorter than the lower sacrificial insulating layers 118 in the second region R2. A photolithography process and an etching process may be repeatedly performed. Accordingly, the sacrificial insulating layers 118 may form a stepped shape. The sacrificial insulating layers 118 may be formed to have a relatively thick thickness at the ends, and a process for this may be further performed. Next, a portion of the cell region insulating layer 190 covering the lower stacked structure of the sacrificial insulating layers 118 and the interlayer insulating layers 120 may be formed.

After the channel sacrificial layers 129 form lower channel holes to pass through the lower stacked structure in an area corresponding to the first channel structures CH1 , the channel sacrificial layers 129 are formed in the lower channel holes. ) can be formed by depositing a material. The channel sacrificial layers 129 may include, for example, polycrystalline silicon.

An upper stacked structure may be formed on the lower stacked structure in the same manner as the lower stacked structure. Next, upper channel holes may be formed in regions corresponding to the second channel structures CH2 (see FIG. 2A ) to pass through the upper stacked structure, and channel sacrificial layers may be further formed.

Referring to FIG. 5C , channel structures CH penetrating the stacked structure of the sacrificial insulating layers 118 and the interlayer insulating layers 120 may be formed.

In order to form the channel structures CH, channel holes may be formed by removing the channel sacrificial layers 129 . A gate dielectric layer 145, a channel layer 140, a channel filling insulating layer 147, and a channel pad 149 are sequentially formed in each of the channel holes to form first and second channel structures CH1 and CH2. It is possible to form channel structures (CH) including. The channel layer 140 may be formed on the gate dielectric layer 145 within the channel structures CH. The channel filling insulating layer 147 is formed to fill the channel structures CH and may be an insulating material. However, according to embodiments, the space between the channel layers 140 may be filled with a conductive material instead of the channel filling insulating layer 147 . The channel pads 149 may be made of a conductive material, for example polycrystalline silicon.

Referring to FIG. 5D , through-holes OP extending to the base substrate SUB are formed through the laminated structure of the sacrificial insulating layers 118 and the interlayer insulating layers 120, and the vertical sacrificial layers 119 can fill

Through-holes OP may be formed at positions corresponding to the vertical structures 150 of FIG. 2A by using a mask layer. The through holes OP may be formed to completely penetrate the stacked structure of the sacrificial insulating layers 118 and the interlayer insulating layers 120 . Lower ends of the through holes OP may be located in the base substrate SUB, but are not limited thereto.

The vertical sacrificial layers 119 may be formed to fill the through holes OP. The vertical sacrificial layers 119 may include materials different from those of the sacrificial insulating layers 118 and the interlayer insulating layers 120, and may include, for example, polycrystalline silicon, metal materials such as tungsten (W), and carbon. It may contain one of the group materials.

Referring to FIG. 5E , dummy vertical structures 156 may be formed in some of the through holes OP.

After the through holes OP are exposed in regions where the dummy vertical structures 156 are formed by using a mask layer, the vertical sacrificial layers 119 in the through holes OP may be selectively removed. Dummy vertical structures 156 may be formed by depositing an insulating material in the through holes OP from which the vertical sacrificial layers 119 are removed. In some embodiments, when the vertical sacrificial layers 119 include an insulating material, this step may be omitted, and some of the vertical sacrificial layers 119 may form the dummy vertical structures 156 .

Referring to FIG. 5F , preliminary first contact insulating layers 160P and vertical sacrificial layers 119' may be formed in some of the through holes OP.

First, by using a mask layer, through-holes OP are exposed in regions where gate contact plugs 152 (see FIG. 2A ) are formed, and then vertical sacrificial layers 119 are formed in the through-holes OP. Can be selectively removed.

Next, some of the sacrificial insulating layers 118 exposed through the through holes OP may be removed. The sacrificial insulating layers 118 may be removed to a predetermined length around the through holes OP to form tunnel portions. The tunnel portions may be formed to have a relatively short length in the uppermost sacrificial insulating layers 118 and to have a relatively long length in the lower sacrificial insulating layers 118 .

An insulating material may be deposited in the through holes OP and the tunnel portions to form preliminary first contact insulating layers 160P. The preliminary first contact insulating layers 160P may be formed on sidewalls of the through holes OP and fill the tunnel portions. In the uppermost sacrificial insulating layers 118 , the preliminary first contact insulating layers 160P may not completely fill the tunnel portions.

Vertical sacrificial layers 119 ′ may be formed on the preliminary first contact insulating layers 160P to fill the through holes OP and the uppermost tunnel portions. The vertical sacrificial layers 119 ′ may include a material different from that of the preliminary first contact insulating layers 160P, and may include, for example, polycrystalline silicon.

Referring to FIG. 5G , input/output contact plugs 154 and second contact insulating layers 162 may be formed in some of the through holes OP.

After exposing the through holes OP in regions where the input/output contact plugs 154 are formed by using the mask layer, the vertical sacrificial layers 119 in the through holes OP may be selectively removed. After the second contact insulating layers 162 are formed by depositing an insulating material in the through holes OP from which the vertical sacrificial layers 119 are removed, a conductive material is deposited to form the input/output contact plugs 154. can

Referring to FIG. 5H, after forming separate openings, the sacrificial insulating layers 118 are removed through the openings, and gate electrodes 130 are formed in regions where the sacrificial insulating layers 118 are removed. , gate contact plugs 152 may be formed.

The openings may be formed in regions corresponding to the first and second isolation regions MS1 , MS2a , and MS2b (see FIG. 1A ) and may be formed in a trench shape extending in the x direction. The sacrificial insulating layers 118 may be selectively removed with respect to the interlayer insulating layers 120 using, for example, wet etching. Accordingly, tunnel portions may be formed between the interlayer insulating layers 120 .

Before forming the gate electrodes 130 , if the gate dielectric layers 145 include a horizontally extending region, they may be formed first. The gate electrodes 130 may be formed by filling the tunnel portions with a conductive material. The gate electrodes 130 may include metal, polysilicon or metal silicide materials. Next, first and second separation regions MS1 , MS2a , and MS2b may be formed by filling the openings with an insulating material.

Next, the vertical sacrificial layers 119' in the through holes OP may be removed. The vertical sacrificial layers 119 ′ may be selectively removed with respect to the interlayer insulating layers 120 and the gate electrodes 130 . After the vertical sacrificial layers 119' are removed, some of the exposed preliminary contact insulating layers 160P may also be removed. In this case, all of the preliminary contact insulating layers 160P may be removed from the pad regions PAD, and the first contact insulating layers 160 may be formed by remaining below them. In the pad regions PAD, when the gate dielectric layer 145 is exposed after the preliminary contact insulating layers 160P are removed, the gate dielectric layer 145 may also be removed to expose the side surfaces of the gate electrodes 130 . have.

The gate contact plugs 152 may be formed by depositing a conductive material in the through holes OP. The gate contact plugs 152 may have regions extending horizontally from the pad regions PAD, and thereby may be physically and electrically connected to the gate electrodes 130 . By forming the gate contact plugs 152 , vertical structures 150 including the gate contact plugs 152 , the input/output contact plugs 154 , and the dummy vertical structures 156 may be formed.

In some embodiments, the formation order of the gate contact plugs 152, the input/output contact plugs 154, and the dummy vertical structures 156 constituting the vertical structures 150 may be variously changed, and the gate The order of forming the electrodes 130 may also be changed. However, the gate contact plugs 152 may be formed after forming the gate electrodes 130 . For example, in some embodiments, after the process of forming the dummy vertical structures 156 and the preliminary first contact insulating layers 160P described above with reference to FIGS. 5E and 5F is performed, a gate gate in this step is performed. The process of forming the electrodes 130 and the gate contact plugs 152 may be performed, and then the process of forming the input/output contact plugs 154 described above with reference to FIG. 5G may be performed.

Referring to FIG. 5I , a second wiring structure and a second bonding structure may be formed on the gate electrodes 130 and the first substrate structure S1 and the second substrate structure S2 may be bonded.

In the second wiring structure, the cell contact plugs 170 may be formed by etching the cell region insulating layer 190 and depositing a conductive material on the channel pads 149 and the vertical structures 150 . The cell wiring lines 180 may be formed through a process of depositing and patterning a conductive material, or may be formed by partially forming an insulating layer constituting the cell region insulating layer 190, patterning the insulating layer, and depositing a conductive material.

The second bonding vias 195 and the second bonding metal layers 198 constituting the second bonding structure include a cell region insulating layer 190 and a second bonding insulating layer 199 on the cell wiring lines 180. ) may be further formed and then partially removed. Top surfaces of the second bonding metal layers 198 and top surfaces of the second bonding insulating layer 199 may be exposed from the cell region insulating layer 190 .

Next, the first substrate structure S1 and the second substrate structure S2 are bonded by bonding the first bonding metals 298 and the second bonding metal layers 198 by annealing and/or pressing. can connect At the same time, the first bonding insulating layer 299 and the second bonding insulating layer 199 may also be bonded. After turning the second substrate structure S2 over the first substrate structure S1 so that the second bonding metal layers 198 face downward, bonding may be performed. In the drawings, for ease of understanding, it is shown that the second substrate structure S2 is bonded in the form of a mirror image of the structure shown in FIG. 5H.

The first substrate structure S1 and the second substrate structure S2 may be directly bonded without an adhesive such as a separate adhesive layer. According to embodiments, before bonding, a surface treatment process such as hydrogen plasma treatment may be further performed on the upper surface of the first substrate structure S1 and the lower surface of the second substrate structure S2 in order to enhance bonding strength. .

Referring to FIG. 5J , after the base substrate SUB is removed and the plate layer 101 is formed, the input/output pad structures 210 may be formed.

A portion of the base substrate SUB may be removed from the upper surface by a polishing process such as a grinding process, and the remaining portion may be removed by an etching process such as a wet etching process. By removing the base substrate SUB of the second substrate structure S2 , the total thickness of the semiconductor device may be minimized. As the base substrate SUB is removed, upper ends of the channel structures CH and the vertical structures 150 may be exposed.

The channel dielectric layers 145 may be removed from upper ends of the exposed channel structures CH. Accordingly, the channel layers 140 may be connected to the plate layer 101 . Upper contact insulating layers 161 may be formed on upper ends of the gate contact plugs 152 of the vertical structures 150 .

However, in some embodiments, at least a portion of the base substrate SUB may form the plate layer 101 without being entirely removed. In this case, the channel layers 140 may be electrically connected to the plate layer 101 through a separate conductive layer disposed on the lower surface of the plate layer 101 . Also, in this case, the upper contact insulating layers 161 may be first formed before forming the gate contact plugs 152 in a previous process step.

The input/output pad structures 210 may be formed from an upper portion of the plate layer 101 . First, a portion of the upper interlayer insulating layer 202 may be formed, via holes may be formed, and then input/output vias 212 may be formed by filling the via holes with a conductive material. The input/output pads 214 may be formed by depositing and patterning a conductive material on the input/output vias 212 .

Next, with reference to FIG. 2A , a passivation layer 204 is formed on the top surfaces of the input/output pads 214 and the upper interlayer insulating layer 202, so that the semiconductor device 100 of FIG. 2A is finally manufactured. can

6 is a diagram schematically illustrating a data storage system including a semiconductor device according to example embodiments.

Referring to FIG. 6 , the data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100 . The data storage system 1000 may be a storage device including one or a plurality of semiconductor devices 1100 or an electronic device including the storage device. For example, the data storage system 1000 may be a solid state drive device (SSD) including one or a plurality of semiconductor devices 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device. .

The semiconductor device 1100 may be a non-volatile memory device, and may be, for example, the NAND flash memory device described above with reference to FIGS. 1A to 4B . The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In example embodiments, the first structure 1100F may be disposed next to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110 , a page buffer 1120 , and a logic circuit 1130 . The second structure 1100S includes a bit line BL, a common source line CSL, word lines WL, first and second gate upper lines UL1 and UL2, and first and second gate lower lines. LL1 and LL2, and memory cell strings CSTR between the bit line BL and the common source line CSL.

In the second structure 1100S, each of the memory cell strings CSTR includes lower transistors LT1 and LT2 adjacent to the common source line CSL and upper transistors UT1 adjacent to the bit line BL. UT2), and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may be variously modified according to embodiments.

In example embodiments, the upper transistors UT1 and UT2 may include string select transistors, and the lower transistors LT1 and LT2 may include ground select transistors. The gate lower lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, and the gate upper lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

In example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used for an erase operation of erasing data stored in the memory cell transistors MCT by using the GIDL phenomenon.

The common source line CSL, the first and second gate lower lines LL1 and LL2, the word lines WL, and the first and second gate upper lines UL1 and UL2 have a first structure ( 1100F) may be electrically connected to the decoder circuit 1110 through first connection wires 1115 extending to the second structure 1100S. The bit lines BL may be electrically connected to the page buffer 1120 through second connection wires 1125 extending from the first structure 1100F to the second structure 1100S.

In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may execute a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by the logic circuit 1130 . The semiconductor device 1100 may communicate with the controller 1200 through the input/output pad 1101 electrically connected to the logic circuit 1130 . The input/output pad 1101 may be electrically connected to the logic circuit 1130 through an input/output connection wire 1135 extending from the first structure 1100F to the second structure 1100S. In example embodiments, the input/output connection wire 1135 may include the input/output contact plugs 154 of FIG. 2A .

The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . According to example embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100 , and in this case, the controller 1200 may control the plurality of semiconductor devices 1100 .

The processor 1210 may control overall operations of the data storage system 1000 including the controller 1200 . The processor 1210 may operate according to predetermined firmware and may access the semiconductor device 1100 by controlling the NAND controller 1220 . The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor device 1100 . Through the NAND interface 1221, a control command for controlling the semiconductor device 1100, data to be written to the memory cell transistors MCT of the semiconductor device 1100, and memory cell transistors of the semiconductor device 1100 ( Data to be read from the MCT) may be transmitted. The host interface 1230 may provide a communication function between the data storage system 1000 and an external host. When a control command is received from an external host through the host interface 1230 , the processor 1210 may control the semiconductor device 1100 in response to the control command.

7 is a perspective view schematically illustrating a data storage system including a semiconductor device according to an exemplary embodiment.

Referring to FIG. 7 , a data storage system 2000 according to an exemplary embodiment of the present invention includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through wiring patterns 2005 formed on the main substrate 2001 .

The main board 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In example embodiments, the data storage system 2000 may include Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Storage (UFS), and the like. Can communicate with an external host according to any one of the interfaces. In example embodiments, the data storage system 2000 may be operated by power supplied from an external host through the connector 2006 . The data storage system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003 .

The controller 2002 can write data to the semiconductor package 2003 or read data from the semiconductor package 2003 and can improve the operating speed of the data storage system 2000 .

The DRAM 2004 may be a buffer memory for mitigating a speed difference between the semiconductor package 2003, which is a data storage space, and an external host. The DRAM 2004 included in the data storage system 2000 may also operate as a kind of cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package 2003 . When the data storage system 2000 includes the DRAM 2004 , the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003 .

The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b spaced apart from each other. Each of the first and second semiconductor packages 2003a and 2003b may be a semiconductor package including a plurality of semiconductor chips 2200 . Each of the first and second semiconductor packages 2003a and 2003b includes a package substrate 2100 , semiconductor chips 2200 on the package substrate 2100 , and adhesive layers 2300 disposed on a lower surface of each of the semiconductor chips 2200 . ), a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100. can include

The package substrate 2100 may be a printed circuit board including package upper pads 2130 . Each semiconductor chip 2200 may include an input/output pad 2210 . The input/output pad 2210 may correspond to the input/output pad 1101 of FIG. 6 . Each of the semiconductor chips 2200 may include gate stack structures 3210 and channel structures 3220 . Each of the semiconductor chips 2200 may include the semiconductor device described above with reference to FIGS. 1A to 4B .

In example embodiments, the connection structure 2400 may be a bonding wire electrically connecting the input/output pad 2210 and the package upper pads 2130 . Accordingly, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other using a bonding wire method, and the package upper pads 2130 of the package substrate 2100 and can be electrically connected. According to example embodiments, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 include through silicon vias (TSVs) instead of the bonding wire type connection structure 2400. It may be electrically connected to each other by a connection structure including a.

In example embodiments, the controller 2002 and the semiconductor chips 2200 may be included in one package. In an exemplary embodiment, the controller 2002 and the semiconductor chips 2200 are mounted on a separate interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chips are connected by wires formed on the interposer substrate. 2200 may be connected to each other.

8 is a schematic cross-sectional view of a semiconductor package according to an exemplary embodiment. FIG. 8 describes an exemplary embodiment of the semiconductor package 2003 of FIG. 7 and conceptually shows a region obtained by cutting the semiconductor package 2003 of FIG. 7 along the cutting line II-II'.

Referring to FIG. 8 , in a semiconductor package 2003A, each of the semiconductor chips 2200b is bonded to a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a wafer bonding method on the first structure 4100. This may include a second structure 4200 bonded to the first structure 4100.

The first structure 4100 may include a peripheral circuit area including the peripheral wiring 4110 and the first junction structures 4150 . The second structure 4200 includes a common source line 4205, a gate stack structure 4210 between the common source line 4205 and the first structure 4100, and channel structures 4220 penetrating the gate stack structure 4210. ), an isolation region 4230, and second junction structures 4250 electrically connected to word lines (WL in FIG. 6) of the memory channel structures 4220 and the gate stack structure 4210, respectively. can For example, the second junction structures 4250 may include bit lines 4240 electrically connected to the memory channel structures 4220 and gate contact plugs 152 electrically connected to word lines (and gate contact plugs 152 ( 2A), it may be electrically connected to the memory channel structures 4220 and the word lines, respectively. The two junction structures 4250 may be bonded while contacting each other.The junctions of the first junction structures 4150 and the second junction structures 4250 may be formed of, for example, copper (Cu). have.

As shown in the enlarged view, the second structure 4200 includes the gate contact plugs 152, the input/output contact plugs 154, and the vertical structures 150 including the dummy vertical structures 156. It may be disposed to pass through the pad areas PAD of the electrodes 130 .

The semiconductor chips 2200b may be electrically connected to each other by connection structures 2400 in the form of bonding wires (see FIG. 10 ). However, in example embodiments, semiconductor chips in one semiconductor package, such as the semiconductor chips 2200b, may be electrically connected to each other by a connection structure including a through electrode (TSV).

The present invention is not limited by the above-described embodiments and accompanying drawings, but is intended to be limited by the appended claims. Therefore, various forms of substitution, modification, and change will be possible by those skilled in the art within the scope of the technical spirit of the present invention described in the claims, which also falls within the scope of the present invention. something to do.

201: substrate 202: upper interlayer insulating layer
204: passivation layer 205: source/drain regions
207: device isolation layer 210: input/output pad structure
212: I/O vias 214: I/O pads
220 circuit element 222 circuit gate dielectric layer
224 spacer layer 225 circuit gate electrode
270 circuit contact plug 280 circuit wiring line
290: peripheral area insulating layer 295: first bonding via
298: first bonding metal layer 299: first bonding insulating layer
101: plate layer 120: interlayer insulating layer
130: gate electrode 140: channel layer
145: gate dielectric layer 147: channel buried insulating layer
149: channel pad 150: vertical structure
152: gate contact plug 154: input/output contact plug
156: dummy vertical structure 160: first contact insulating layer
161: upper contact insulating layer 162: second contact insulating layer
170 cell contact plug 180 cell wiring line
190: cell region insulating layer 195: second bonding via
198: second bonding metal layer 199: second bonding insulating layer

Claims (10)

a first substrate structure including a substrate, circuit elements disposed on the substrate, and first bonding metal layers disposed on the circuit elements; and
A second substrate structure connected to the first substrate structure on the first substrate structure and having a first region and a second region,
The second substrate structure,
plate layer;
Gates are spaced apart from each other and stacked under the plate layer in a first direction perpendicular to the lower surface of the plate layer, and extend from the second region to different lengths along the second direction to form pad regions of different levels. electrodes;
channel structures in the first region, penetrating the gate electrodes and extending along the first direction, each including a channel layer;
vertical structures extending along the first direction and penetrating the pad regions of the gate electrodes in the second region;
input/output pad structures, at least partially disposed on the plate layer; and
Second bonding metal layers disposed under the gate electrodes and connected to the first bonding metal layers,
The vertical structures include gate contact plugs connected to the gate electrodes in the pad regions, input/output contact plugs connected to the input/output pad structures, and dummy vertical structures each including an insulating layer,
The pad regions include a first pad region,
At least one of the gate contact plugs and at least one of the input/output contact plugs are disposed to pass through the first pad region.
According to claim 1,
At least one of the dummy vertical structures is disposed to pass through the first pad region.
According to claim 1,
The semiconductor device of claim 1 , wherein the vertical structures are arranged in a regular pattern in the pad regions.
According to claim 3,
The vertical structures are disposed in four corner regions and a central region of each of the pad regions.
According to claim 1,
The semiconductor device of claim 1 , wherein the gate contact plugs and the input/output contact plugs have different internal structures.
According to claim 1,
The second substrate structure,
first contact insulating layers surrounding each of the gate contact plugs on the pad regions; and
The semiconductor device further includes a second contact insulating layer surrounding side surfaces of each of the input/output contact plugs.
According to claim 1,
Each of the input/output pad structures,
input/output vias penetrating the plate layer and disposed on the input/output contact plugs; and
A semiconductor device comprising an input/output pad on the input/output via.
According to claim 1,
The gate contact plugs, the input/output contact plugs, and lower ends of the dummy vertical structures are positioned on the same level as the semiconductor device.
A first substrate structure including circuit elements and first bonding metal layers, gate electrodes, second bonding metal layers connected to the first bonding metal layers, and input/output pads electrically connected to the circuit elements a semiconductor storage device including a second substrate structure having a first region and a second region; and
a controller electrically connected to the semiconductor storage device through the input/output pad and controlling the semiconductor storage device;
The second substrate structure,
plate layer;
gate electrodes spaced apart from each other and stacked under the plate layer along a first direction perpendicular to a lower surface of the plate layer, and extending from the second region to different lengths along a second direction to form pad regions;
channel structures in the first region, penetrating the gate electrodes and extending along the first direction, each including a channel layer;
gate contact plugs connected to the gate electrodes in the pad regions in the second region and extending along the first direction;
input/output contact plugs extending along the first direction and penetrating the pad regions in the second region;
dummy vertical structures in the second area, penetrating the pad areas and extending along the first direction, each including an insulating layer; and
Second bonding metal layers disposed under the gate electrodes and connected to the first bonding metal layers,
Upper ends of the gate contact plugs, the input/output contact plugs, and the dummy vertical structures are positioned on the lower surface of the plate layer.
According to claim 9,
One gate contact plug of the gate contact plugs, one of the input/output contact plugs, and at least one dummy vertical structure of the dummy vertical structures form at least one pad area of the pad areas. A data storage system arranged to pass through.

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