KR20230122839A - Intelligent system and method for manufacturing multilayer pcb - Google Patents

Abstract

It relates to an intelligent multi-layer PCB (MLB) manufacturing system and method, wherein the intelligent multi-layer PCB (MLB) manufacturing system acquires drawing information including shape information of a target PCB, and the drawing information A shape analysis unit for deriving arrangement information for a plurality of chips, a plurality of elements, and a plurality of layers based on the shape analysis unit; a manufacturing unit that manufactures the multi-layer PCB (MLB) based on the arrangement information; an image acquiring unit acquiring an image of the target PCB on which the plurality of chips, the plurality of elements, and the plurality of layers are disposed; and a vision inspection unit configured to detect a defect associated with attachment of each of the plurality of chips, insertion of each of the plurality of elements, and arrangement of each of the plurality of layers based on the arrangement information and the image, wherein the vision inspection unit When detecting the defect, the shape analysis unit corrects the layout information to derive first corrected layout information to prevent the defect, and the manufacturing unit derives first corrected layout information based on the first corrected multilayer PCB (Multi-layer PCB). Layer PCB, MLB) can be manufactured.

Description

Intelligent multilayer PCB manufacturing system and method {INTELLIGENT SYSTEM AND METHOD FOR MANUFACTURING MULTILAYER PCB}

The present application relates to an intelligent multi-layer PCB (MLB) manufacturing system and method.

In general, on a printed circuit board (PCB), which is embedded as a major part of electrical and electronic products such as home appliances and computers, semiconductor chips, capacitors, resistors, etc., passive elements or electronic components are mounted. It becomes.

In particular, Multi-Layer PCB (MLB) is applied with various structures, high density and surface coating technology to safely guarantee the quality of the circuit board and to be easy to use.

However, Multi-Layer PCB (MLB) can cause problems such as electrical connection during actual use, blowing or degassing, assembly, or failure possibility under load conditions. problems may arise.

Therefore, more precision is required in manufacturing a conventional multi-layer PCB (MLB).

The background technology of the present application is disclosed in Korean Patent Registration No. 10-1452190.

The present application is to solve the problems of the prior art described above, and an intelligent multi-layer PCB (Multi-Layer PCB, MLB) manufacturing system and method capable of solving the defect generation problem during conventional multi-layer PCB (Multi-Layer PCB, MLB) manufacturing It aims to provide

However, the technical problem to be achieved by the embodiments of the present application is not limited to the technical problems described above, and other technical problems may exist.

As a technical means for achieving the above technical problem, an intelligent multi-layer PCB (MLB) manufacturing system according to an embodiment of the present application acquires drawing information including shape information of a target PCB, and the drawing information A shape analysis unit for deriving arrangement information for a plurality of chips, a plurality of elements, and a plurality of layers based on the shape analysis unit; a manufacturing unit that manufactures the multi-layer PCB (MLB) based on the arrangement information; an image acquiring unit acquiring an image of the target PCB on which the plurality of chips, the plurality of elements, and the plurality of layers are disposed; and a vision inspection unit configured to detect a defect associated with attachment of each of the plurality of chips, insertion of each of the plurality of elements, and arrangement of each of the plurality of layers based on the arrangement information and the image, wherein the vision inspection unit When detecting the defect, the shape analysis unit corrects the layout information to derive first corrected layout information to prevent the defect, and the manufacturing unit derives first corrected layout information based on the first corrected multilayer PCB (Multi-layer PCB). Layer PCB, MLB) can be manufactured.

According to an embodiment of the present application, the intelligent multi-layer PCB manufacturing system, a cutting image collection unit for collecting a chip cutting image of a cutting machine for cutting a bundle of chips to which the plurality of chips are connected into individual chips having a certain width and a certain length ; a fixing image collection unit that collects chip fixing images of a press machine that fixes the plurality of chips to a target PCB board through a press fit process; and a detection unit configured to detect defects in the target PCB board and the chip fixing through the chip cutting image and the chip fixing image, wherein when the detection unit detects defects in the target PCB board and the chip fixing, The shape analysis unit derives second corrected layout information by modifying the layout information to prevent defects in fixing the board for the target PCB and the chip, and the manufacturing unit derives second corrected layout information based on the second corrected layout information. (Multi-Layer PCB, MLB) can be manufactured.

According to an embodiment of the present application, the cutting image collection unit further collects device cutting images of a cutting machine that cuts the device bundle to which the plurality of devices are connected into each device having a certain width and a certain length, and collects the fixed image The unit further collects an element fixing image of a press machine for fixing the plurality of elements to the target PCB board through the press fit process, and the detection unit, through the element cutting image and the element fixing image, for the target PCB Further detecting defects in the board and the device fixing, and when detecting defects in the board for the target PCB and the device fixing, the shape analysis unit corrects the arrangement information to prevent defects in the board for the target PCB and the device fixation. Third correction placement information is derived, and the manufacturing unit may manufacture a third correction multi-layer PCB (MLB) based on the third correction placement information.

According to an embodiment of the present application, the detection unit receives the chip cutting image, the chip fixing image, the device cutting image, and the device fixing image as inputs, and a defect detection result of the target PCB board and the chip fixing Based on the artificial neural network built through learning that outputs the defect detection result of the board for the target PCB and the device fixation, the defect of the board for the target PCB and the chip fixation or the defect of the board for the target PCB and the device fixation When detecting, the shape analysis unit corrects the placement information to derive fourth corrected placement information to prevent a defect in fixing the board for the target PCB and the chip or a defect in fixing the board for the target PCB and the device, and The manufacturing unit may manufacture a fourth modified multi-layer PCB (MLB) based on the fourth modified layout information.

According to an embodiment of the present application, the output is a detection result of a chip fixing defect and a device based on the chip fixing image and the device fixing image on the assumption that the cutting of the chip bundle and the device bundle by the cutting machine is normal. It may include detection results of poor coupling.

According to an embodiment of the present application, the detection unit is configured to an artificial neural network built through learning that takes the chip fixation image and the device fixation image as inputs, and outputs a detection result of chip fixation failure and a result of device fixation failure. Based on this, if the chip fixing defect and the element fixing defect are detected, the shape analysis unit corrects the arrangement information to prevent a defect in fixing the target PCB board and the chip or a defect in the target PCB board and the device fixing. 5th correction placement information is derived, and the manufacturing unit may manufacture a 5th correction multi-layer PCB (MLB) based on the 5th correction placement information.

According to an embodiment of the present application, the detecting unit determines the defect cause type through an artificial neural network that takes the chip cutting image and the device cutting image associated with the fixing defect detection as inputs, and the shape analysis unit determines the defect cause type. It is possible to derive the arrangement information by avoiding.

According to an embodiment of the present application, the shape analyzer analyzes chips for deriving first placement information including area information and location information of the chip attachment region corresponding to each of the plurality of chips, based on the drawing information. wealth; a device analyzer for deriving second arrangement information including area information, location information, and device color information of the device coupling region corresponding to each of the plurality of devices, based on the drawing information; and n (n is a positive integer, n>1) layer type information and n (n is a positive integer, n>1) layer order information corresponding to each of the plurality of layers, based on the drawing information. It may include a layer analyzer for deriving third arrangement information to include.

According to an embodiment of the present application, the vision inspection unit identifies one chip among the plurality of chips in the image, and based on the first placement information derived for the chip attachment region corresponding to the corresponding chip, Determining the adhesion strength and surface contamination of the corresponding chip, but if the adhesion strength of the chip is less than or equal to a predetermined level or the degree of surface contamination is greater than or equal to a predetermined level, the shape analysis unit determines that the adhesion strength of the chip exceeds the predetermined strength, The first batch information is modified so that the surface contamination is less than a predetermined level to derive chip modified batch information, and the manufacturing unit manufactures a chip modified multi-layer PCB (MLB) based on the chip modified batch information. can do.

According to an embodiment of the present application, the vision inspection unit identifies any one element among the plurality of elements in the image, and based on the second arrangement information derived for the element coupling region corresponding to the corresponding element, An insertion defect associated with misinsertion or reverse insertion of the corresponding element is determined, and if the insertion defect exists, the shape analyzer corrects the second arrangement information to avoid the insertion defect, and derives corrected arrangement information for the first element. The manufacturing unit may manufacture a first element modified multi-layer PCB (MLB) based on the first element modified arrangement information.

According to an embodiment of the present application, the element analysis unit derives reference color information of a merge inspection area including at least two or more device coupling areas, and actual color information of a portion corresponding to the merge inspection area in the image is If it is out of a preset color range based on the reference color information, the vision inspection unit determines that the insertion defect has occurred, and the shape analyzer determines that the actual color information is within a preset color range based on the reference color information. Modify the second arrangement information to derive second element modified arrangement information, and the manufacturing unit may manufacture a second element modified multi-layer PCB (MLB) based on the second element modified arrangement information. .

According to one embodiment of the present application, the vision inspection unit may include the device in which the insertion defect has occurred based on the second arrangement information of each of the at least two or more device coupling regions included in the merge inspection area in which the insertion defect is detected; and While specifying the type of the insertion defect, the shape analysis unit may derive the placement information so that the specified device and the type of the insertion defect do not occur.

According to an embodiment of the present application, the vision inspection unit identifies any one of the plurality of layers in the image, and based on the third arrangement information derived for the layer arrangement area corresponding to the layer, Determines the shape accuracy of the corresponding layer, but if the shape accuracy of the layer is less than a preset level, the shape analyzer modifies the third arrangement information so that the shape accuracy of the layer is equal to or greater than a preset level, and obtains layer corrected arrangement information. derived, and the manufacturing unit may manufacture a layer-modified multi-layer PCB (MLB) based on the layer-modified arrangement information.

According to an embodiment of the present application, in an intelligent multi-layer PCB (MLB) manufacturing method, a shape analysis unit obtains drawing information including shape information of a target PCB, and a plurality of chips and a plurality of chips based on the drawing information. deriving arrangement information for an element of and a plurality of layers; manufacturing the multi-layer PCB (Multi-Layer PCB, MLB) based on the arrangement information by a manufacturing unit; Acquiring an image of the target PCB on which the plurality of chips, the plurality of devices, and the plurality of layers are disposed by an image acquisition unit; detecting, by a vision inspector, a defect associated with the attachment of each of the plurality of chips, the insertion of each of the plurality of elements, and the arrangement of each of the plurality of layers, based on the arrangement information and the image; deriving first corrected placement information by modifying the placement information so that the shape analyzer prevents the defect when the vision inspection unit detects the defect; and manufacturing, by the manufacturing unit, a first modified multi-layer PCB (MLB) based on the first modified arrangement information.

The above-described problem solving means are merely exemplary and should not be construed as intended to limit the present disclosure. In addition to the exemplary embodiments described above, additional embodiments may exist in the drawings and detailed description of the invention.

According to the problem-solving means of the present application described above, by providing an intelligent multi-layer PCB manufacturing system and method, it is possible to solve the defect generation problem during conventional multi-layer PCB (Multi-Layer PCB, MLB) manufacturing.

However, the effects obtainable herein are not limited to the effects described above, and other effects may exist.

1 is a schematic configuration diagram of an intelligent multi-layer PCB manufacturing system according to an embodiment of the present application.
Figure 2 is a schematic block diagram of an intelligent multi-layer PCB manufacturing apparatus according to an embodiment of the present application.
3 is a schematic block diagram of an extended configuration of an intelligent multi-layer PCB manufacturing apparatus according to an embodiment of the present disclosure.
4 is a conceptual diagram for explaining an embodiment in which a spray pattern of a waterproof material is changed according to spray control information.
5 is an operation flow chart for an intelligent multi-layer PCB manufacturing method according to an embodiment of the present application.

Hereinafter, embodiments of the present application will be described in detail so that those skilled in the art can easily practice with reference to the accompanying drawings. However, the present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. And in order to clearly describe the present application in the drawings, parts irrelevant to the description are omitted, and similar reference numerals are attached to similar parts throughout the specification.

Throughout the present specification, when a part is said to be “connected” to another part, it is not only “directly connected”, but also “electrically connected” or “indirectly connected” with another element in between. "Including cases where

Throughout the present specification, when a member is referred to as being “on,” “above,” “on top of,” “below,” “below,” or “below” another member, this means that a member is located in relation to another member. This includes not only the case of contact but also the case of another member between the two members.

Throughout the present specification, when a certain component is said to "include", it means that it may further include other components without excluding other components unless otherwise stated.

1 is a schematic configuration diagram of an intelligent multi-layer PCB manufacturing system according to an embodiment of the present application.

Referring to FIG. 1, an intelligent multi-layer PCB manufacturing system 1 (hereinafter, referred to as 'this system 1') is a multi-layer PCB (Multi-Layer PCB, MLB) (hereinafter, also referred to as 'target PCB'.) A multi-layer PCB manufacturing line 10 (hereinafter referred to as 'this processing line 10') for manufacturing (A) and an intelligent multi-layer PCB manufacturing device 100 controlling this processing line 10 through the network 20 ) (hereinafter referred to as 'this device 100'). The apparatus 100 acquires drawing information of a multi-layer PCB (MLB), derives placement information for a plurality of chips, elements, and layers based on the acquired drawing, and based on the derived placement information. to control the processing line 10 to manufacture a multi-layer PCB (Multi-Layer PCB, MLB), and a target PCB on which a plurality of chips, elements, and layers are disposed by the processing line 10 (hereinafter referred to as 'multi-layer PCB (Multi-Layer PCB, MLB)'), and based on the derived placement information and the acquired image, attaching each of a plurality of chips, inserting each of a plurality of elements, and each of a plurality of layers A defect associated with the layout is detected, and if the defect is detected, the processing line 10 is controlled to re-manufacture the multi-layer PCB (target PCB) based on the corrected layout information by correcting the batch information to prevent the aforementioned defect. can

In addition, although not shown in the drawing, the present system 1 disclosed herein uses a user terminal (not shown) provided to express control parameters, state information, etc. of the processing line 10 set by the present apparatus 100. can include

According to one embodiment of the present application, the apparatus 100 may provide a multi-layer PCB manufacturing menu and an emergency transfer menu to a user terminal (not shown). For example, a user terminal (not shown) downloads and installs an application program provided by the device 100, and a multi-layer PCB manufacturing menu and an emergency transfer menu may be provided through the installed application.

The apparatus 100 may include all kinds of servers, terminals, or devices that transmit and receive data, contents, and various communication signals with a user terminal (not shown) through the network 20 and have functions of storing and processing data. can

A user terminal (not shown) is a device that interworks with the device 100 through the network 20, and is, for example, a smartphone, a smart pad, a tablet PC, a wearable device, and the like, and a PCS (Personal Communication System), GSM (Global System for Mobile communication), PDC (Personal Digital Cellular), PHS (Personal Handyphone System), PDA (Personal Digital Assistant), IMT (International Mobile Telecommunication)-2000, CDMA (Code Division Multiple Access) -2000, W-CDMA (W-Code Division Multiple Access), Wibro (Wireless Broadband Internet) terminals, and all kinds of wireless communication devices, desktop computers, and fixed terminals such as smart TVs.

Examples of the network 20 for sharing information between the apparatus 100, the process line 10, and a user terminal (not shown) include a 3rd Generation Partnership Project (3GPP) network, a Long Term Evolution (LTE) network, and 5G Network, WIMAX (World Interoperability for Microwave Access) network, wired and wireless Internet, LAN (Local Area Network), Wireless LAN (Wireless Local Area Network), WAN (Wide Area Network), PAN (Personal Area Network), Bluetooth ( A Bluetooth) network, a Wifi network, a Near Field Communication (NFC) network, a satellite broadcasting network, an analog broadcasting network, a Digital Multimedia Broadcasting (DMB) network, and the like may be included, but are not limited thereto.

In the description of the embodiment of the present application, the processing line 10 includes a loader for supplying a target PCB, a solder printer for applying solder cream to the upper surface of the target PCB, and a plurality of chips on the target PCB. Chip mounter attached to each corresponding position, heating/cooling means, facilities for inserting various elements such as elements and condensers arranged on the target PCB, coating machine spraying waterproof material on the target PCB, etc. It may include at least some of the modules, but is not limited thereto. Illustratively, depending on whether the electronic device on which the target PCB is mounted is a device (eg, a bidet) driven in an environment where water may intrude into the inside, the coating machine for spraying the waterproof material is in this processing line ( 10) may optionally be included.

Figure 2 is a schematic block diagram of an intelligent multi-layer PCB manufacturing apparatus 100 according to an embodiment of the present application.

Referring to FIG. 2 , the device 100 may obtain a shape analysis unit 110, a manufacturing unit 120, an image acquisition unit 130, and a vision inspection unit 140.

According to one embodiment of the present application, the shape analysis unit 110 obtains drawing information including shape information of a target PCB, and arranges a plurality of chips, a plurality of elements, and a plurality of layers based on the obtained drawing information. information can be derived.

For example, drawing information including shape information of a target PCB may mean a CAD program file including 3D shape information of a target PCB to be manufactured through the processing line 10 .

In this regard, according to the type of target PCB to be manufactured through this processing line 10, various elements placed on the target PCB, the number, position, size, type, number of layers of the target PCB, etc. of elements attached to the target PCB This can be determined in various ways, and in this regard, the apparatus 100, through analysis of drawing information, after the process of attaching a plurality of chips and inserting a plurality of elements according to the layer configuration to the target PCB is completed, layer configuration, Detailed settings for vision inspection can be customized according to the target PCB so that it can be determined whether chip attachment and device insertion have been performed correctly through vision inspection of an image captured through the camera module.

According to one embodiment of the present application, the manufacturing unit 120 may manufacture a multi-layer PCB (MLB) based on the arrangement information.

For example, the manufacturing unit 120 manufactures a target PCB based on the layout information derived by the shape analysis unit 110, and the control unit allows the processing line 10 to manufacture the target PCB according to the derived layout information. It may mean controlling this processing line 10 .

According to one embodiment of the present application, the image acquisition unit 130 may acquire an image of a target PCB on which a plurality of chips, a plurality of devices, and a plurality of layers are disposed.

For example, the present processing line 10 photographs a manufactured target PCB and includes a photographing device provided in the present processing line 10 (hereinafter, referred to as 'this photographing apparatus'), and an image acquisition unit 130 Controls the photographing device so that the photographing device photographs the target PCB manufactured in the processing line 10 under the control of the manufacturing unit 120 to generate an image of the target PCB, and generates an image of the target PCB The image acquiring unit 130 may acquire. The image of the target PCB obtained by the image acquisition unit 130 may be image information obtained by photographing the entire manufacturing process of the target PCB. In addition, the image of the target PCB obtained by the image acquisition unit 130 may include a third perspective image capable of confirming a combination state of layers, chips, and devices.

According to an embodiment of the present application, the vision inspection unit 140 may detect defects associated with the attachment of each of a plurality of chips, the insertion of each of a plurality of elements, and the arrangement of each of a plurality of layers, based on the arrangement information and the image. .

For example, the vision inspection unit 140 determines the placement information derived based on the drawing information of the target PCB and the attachment of each of the plurality of chips of the target PCB manufactured based on the image of the target PCB manufactured based on the placement information. , whether the insertion of each of a plurality of elements is made in accordance with the arrangement information, and whether the arrangement of each of the plurality of layers is made in conformity with the arrangement information, etc. can detect

According to one embodiment of the present application, when the vision inspection unit 140 detects a defect, the shape analyzer 110 may derive first corrected placement information by correcting the placement information to prevent the defect.

For example, the vision inspection unit 140 determines the placement information derived based on the drawing information of the target PCB and the attachment of each of the plurality of chips of the target PCB manufactured based on the image of the target PCB manufactured based on the placement information. , whether the insertion of each of a plurality of elements is made in accordance with the arrangement information, and whether the arrangement of each of the plurality of layers is made in conformity with the arrangement information, etc. , the shape analysis unit 110 determines whether the attachment of each of a plurality of chips of the target PCB manufactured to prevent the above-mentioned defects is made consistent with the placement information, and whether the insertion of each of the plurality of elements coincides with the placement information. First corrected arrangement information may be derived by modifying the arrangement information for a matter corresponding to a defect among whether or not the arrangement of each of the plurality of layers is made consistent with the arrangement information.

For example, when the vision inspection unit 140 detects an attachment defect of one chip a in the attachment of a plurality of chips on the target PCB, the shape analysis unit 110 determines the attachment method, attachment location, etc. of chip a in the arrangement information. First modified arrangement information may be derived by modifying .

According to an embodiment of the present application, the manufacturing unit 120 may manufacture a first-modified multi-layer PCB (MLB) based on the derived first-modified placement information.

For example, the manufacturing unit 120 performs a first correction multi-layer PCB (MLB) based on the first correction placement information derived by the shape analysis unit 110 (hereinafter referred to as 'first correction subject PCB'). Also referred to as.) can be controlled so that this processing line 10 manufactures.

3 is a schematic block diagram of an extended configuration of an intelligent multi-layer PCB manufacturing apparatus 100 according to an embodiment of the present application.

Referring to FIG. 3 , the apparatus 100 includes a shape analysis unit 110, a manufacturing unit 120, an image acquisition unit 130, a vision inspection unit 140, a cut image collection unit 150, A fixed image collection unit 160 and a detection unit 170 may be included. The shape analyzer 110 may include a chip analyzer 111 , a device analyzer 112 , and a layer analyzer 113 .

According to an embodiment of the present application, the cutting image collection unit 150 may collect chip cutting images of a cutting machine that cuts a bundle of chips in which a plurality of chips are connected into individual chips having a certain width and a certain length.

For example, the photographing device provided in the present processing line 10 may include a chip cutting photographic device for capturing a process in which the cutter provided in the present processing line 10 cuts a bunch of chips. The cutter cuts a bundle of chips in which a plurality of chips are connected into individual chips having a predetermined width and a predetermined length, and may be controlled by the apparatus 100 . The cutter may include a lower jig for supporting and guiding the lower portion of the chip bundle and an upper jig for cutting the chip bundle into individual chips. That is, the chip bunches are seated on the lower jig, and the upper jig applies pressure from the top of the chip bundles, so that the chip bundles can be cut into individual chips. At this time, the cutting image collection unit 150 may collect cutting images including images of a lower jig supporting the chip bundle and an upper jig cutting the chip bundle. If the lower jig is not properly seated in the chip bundle or if the upper jig fails to accurately cut the chip bundle (for example, if the chip is incorrectly cut so that the width between the chips is different), the chip may be defective, and the chip may Defects may occur in fixing the target PCB board and chip. Therefore, the cut image can be used for defect detection. The bundle of chips may be manufactured in the present processing line 10 under the control of the apparatus 100 based on arrangement information. The cutting image collecting unit 150 may collect chip cutting images by controlling the chip cutting imaging device.

According to an embodiment of the present application, the fixing image collection unit 160 may collect chip fixing images of a press machine that fixes a plurality of chips to a target PCB board through a press-fit process.

For example, the present photographing device provided in the present processing line 10 is a chip fixation photographing the process of fixing a plurality of chips to a target PCB board through a press fit process by a press provided in the present processing line 10 device may be included. The press machine can be controlled by the device 100. The fixation image collection unit 160 may collect a chip fixation image by controlling a chip fixation imaging device.

According to an embodiment of the present application, the detection unit 170 may detect defects in a target PCB board and chip fixing through a chip cutting image and a chip fixing image.

For example, the detection unit 170 determines whether or not the chip has been cut to correspond to the derived placement information based on the collected chip cutting image and chip fixing image, and fixes the cut chip to the target PCB board to correspond to the derived placement information. It is possible to detect a defect in fixing the chip on the target PCB board by determining whether or not the

According to one embodiment of the present application, when the detection unit 170 detects defects in fixing boards and chips for a target PCB, the shape analysis unit 110 corrects placement information to prevent defects in fixing boards and chips for a target PCB. Second modified arrangement information may be derived.

Based on the chip cutting image and the chip fixing image, the detection unit 170 determines whether the chip has been cut to correspond to the derived placement information and whether the cut chip has been fixed to the target PCB board to correspond to the derived placement information. When detecting a defect in chip fixation on the target PCB board, the shape analysis unit 110 corrects the cutting width or cutting length of the chip bundle in the arrangement information so that the chip fixation defect does not occur on the target PCB board, or cut the chip The second corrected arrangement information may be derived by modifying the fixing method or the fixing position of .

According to an embodiment of the present application, the manufacturing unit 120 may manufacture a second modified multi-layer PCB (MLB) based on the second modified layout information.

The manufacturing unit 120 may control the processing line 10 to manufacture a second modified multi-layer PCB based on the second modified arrangement information derived by the shape analysis unit 110 . This processing line 10 may include a cutting machine, a press machine, etc., but is not limited thereto.

According to an embodiment of the present application, the cutting image collection unit 150 may collect a device cutting image of a cutting machine that cuts a bundle of devices in which a plurality of devices are connected into each device having a certain width and a certain length.

For example, the present photographing device provided in the present processing line 10 may include a device cutting and photographing device for photographing a process in which the cutter provided in the present processing line 10 cuts the element bundle. The cutter cuts a bundle of elements in which a plurality of elements are connected into individual elements having a predetermined width and a predetermined length, and may be controlled by the device 100 . The cutter may include a lower jig for supporting and guiding a lower portion of the element bundle and an upper jig for cutting the element bundle into individual elements. That is, the element bundle may be seated on the lower jig, and the upper jig may apply pressure from the top of the element bundle to cut the element bundle into individual elements. At this time, the cut image collection unit 150 may collect the cut image including images of the lower jig supporting the element bundle and the upper jig cutting the element bundle. If the lower jig is not properly seated in the element bundle or if the upper jig fails to accurately cut the element bundle (for example, if the element is incorrectly cut so that the width between elements is different), defects may occur in the element, and A defect may occur in the fixation of the board for the target PCB and the device. Therefore, the cut image can be utilized for defect detection. The element cluster may be manufactured in the present processing line 10 under the control of the apparatus 100 based on arrangement information. The cutout image collection unit 150 may collect the cutout images by controlling the device cutout photographing device.

According to an embodiment of the present application, the fixing image collection unit 160 may collect device fixing images of a press machine that fixes a plurality of devices to a target PCB board through a press-fit process.

For example, the present photographing device provided in the present processing line 10 is a device fixation photographing for photographing the process of fixing a plurality of elements to a target PCB board through a press fit process by a press provided in the present processing line 10 device may be included. The press machine can be controlled by the device 100. The fixation image collection unit 160 may collect device fixation images by controlling the device fixation imaging device.

According to an embodiment of the present application, the detection unit 170 may detect a defect in a target PCB board and device fixing through an image of device cutting and an image of device fixing.

For example, the detection unit 170 determines whether or not the device has been cut to correspond to the derived placement information based on the collected device cutting image and device fixing image, and fixes the cut device to the target PCB board to correspond to the derived placement information. It is possible to detect defects in device fixation on the target PCB board by determining whether or not the

According to one embodiment of the present application, when the detection unit 170 detects a defect in the target PCB board and device fixation, the shape analysis unit 110 corrects the placement information to prevent the target PCB board and device fixation defect. Third correction arrangement information may be derived.

When the detection unit 170 determines whether or not the device is fixed to the target PCB board based on the device cutting image and the device fixing image to correspond to the derived placement information and detects a defect in device fixation on the target PCB board, shape analysis The unit 110 corrects the cutting width or cutting length of the element bundle in the placement information or the fixing method or fixing position of the cut devices to obtain third corrected placement information so that defective device fixing does not occur on the target PCB board. can be derived

According to an embodiment of the present application, the manufacturing unit 120 may manufacture a third-correction multi-layer PCB (MLB) based on the third-correction placement information.

The manufacturing unit 120 may control the processing line 10 to manufacture a third correction multi-layer PCB based on the third correction arrangement information derived by the shape analysis unit 110 . This processing line 10 may include a cutting machine, a press machine, etc., but is not limited thereto.

According to an embodiment of the present application, the detection unit 170 receives a chip cutting image, a chip fixing image, a device cutting image, and a device fixing image as inputs, and a defect detection result of a target PCB board and chip fixing and a target PCB board and If a defect in fixing a board and a chip for a target PCB or a defect in fixing a board and an element for a target PCB is detected based on the artificial neural network built through learning with the result of detecting a defect in device fixing as an output, the shape analysis unit 110 Fourth corrected placement information may be derived by modifying the placement information to prevent a defect in fixing the board and chip for the target PCB or a defect in fixing the board and device for the target PCB.

For example, the detection unit 170 receives a chip cutting image, a chip fixing image, a device cutting image, and a device fixing image as inputs, and detects a defect detection result of a target PCB board and chip fixing and a defect detection of a target PCB board and device fixing. At least one of a chip cutting image, a chip fixing image, a device cutting image, and a device fixing image is input to the artificial neural network (hereinafter referred to as 'artificial neural network a') built through learning with the result as an output, and then output If at least one of chip cutting defects, chip fixing defects on the target PCB board, element cutting defects, and element fixation defects on the target PCB board is detected, the shape analysis unit 110 is Fourth corrected placement information can be derived by correcting a part corresponding to the defective part detected in the placement information (eg, modifying the cutting width or length of the chip) to prevent defects or defects in target PCB board and device fixation. there is.

In addition to the LSTM algorithm, the artificial neural network a analyzes time-series data that reflects the chip cutting process, chip settling process, device cutting process, and device settling process, such as the Attention algorithm, Transformer algorithm, and BERT (Bidirectional Encoder Representations from Transformers) algorithm. It may include an artificial intelligence algorithm based on time-series data analysis that identifies types of defects related to chips or devices on the target PCB. That is, the present application may include algorithm models based on various time-series data analysis that are previously known or developed in the future.

According to an embodiment of the present application, the manufacturing unit 120 may manufacture a fourth modified multi-layer PCB (MLB) based on the fourth modified batch information.

The manufacturing unit 120 may control the processing line 10 to manufacture a fourth correction multilayer PCB based on the fourth correction arrangement information derived by the shape analysis unit 110 . This processing line 10 may include a cutting machine, a press machine, etc., but is not limited thereto.

According to one embodiment of the present application, the output includes a detection result of a chip fixation defect and a detection result of an element coupling defect based on the chip fixation image and the device fixation image under the assumption that the cutting of the chip bundle and the device bundle by the cutter is normal. can do.

For example, in relation to the artificial neural network a, it is assumed that the chip bundle and the device bundle are cut without defects by the cutting machine, and then, when the chip fixing image and the device fixing image are input to the artificial neural network a, the output of the artificial neural network a is It may include a detection result of whether or not there is a defect in the chip fixing process on the target PCB board and a detection result of whether or not there is a defect in the device fixing process on the target PCB board.

According to an embodiment of the present application, the detection unit 170 is based on an artificial neural network built through learning that takes a chip fixation image and a device fixation image as inputs, and outputs a detection result of chip fixation failure and a result of device fixation failure. When detecting defective chip fixing and defective device fixing, the shape analysis unit 110 corrects the placement information to prevent defective fixing of the board and chip for the target PCB or defective fixing of the board and element for the target PCB, thereby obtaining a 5th correction arrangement information can be derived.

For example, the detection unit 170 calculates an artificial neural network b assuming that the chip bundle and the element bundle are cut without defects in the artificial neural network a, and inputs the chip fixation image and the device fixation image to the artificial neural network b. And learning to output the detection result of chip fixation failure and whether or not the device fixation failure result is performed, and at least one of chip fixation failure and device fixation failure in the output of the chip fixation image and device fixation image as input to the artificial neural network b. If a defect is detected, the shape analysis unit 110 corrects the portion corresponding to the defective portion detected in the placement information to prevent a defect in fixing the board and chip for the target PCB or a defect in fixing the board and device for the target PCB (eg For example, correcting the chip fixing position or correcting the device fixing position) may derive fifth corrected arrangement information.

In addition to the LSTM algorithm, artificial neural network b analyzes time-series data that reflects the process of fixing chips and devices, such as the Attention algorithm, Transformer algorithm, and Bidirectional Encoder Representations from Transformers (BERT) algorithm. It may include artificial intelligence algorithms based on time-series data analysis to identify defect types. That is, the present application may include algorithm models based on various time-series data analysis that are previously known or developed in the future.

According to one embodiment of the present application, the manufacturing unit 120 may manufacture a fifth correction multi-layer PCB (MLB) based on the fifth correction placement information.

The manufacturing unit 120 may control the processing line 10 to manufacture a fifth correction multilayer PCB based on the fifth correction arrangement information derived by the shape analysis unit 110 . This processing line 10 may include a cutting machine, a press machine, etc., but is not limited thereto.

According to an embodiment of the present application, the detection unit 170 determines the type of defect cause through an artificial neural network that receives chip cutting images and device cutting images associated with fixing defect detection as inputs, and the shape analysis unit 110 determines the defect cause type. Placement information can be derived by avoiding the cause type.

For example, the detection unit 170 may build an artificial neural network c that receives chip cutting images and device cutting images corresponding to fixation defects previously detected through artificial neural network b as inputs and outputs the type of fixation defects detected. The detection unit 170 may input the chip cutting image and the device cutting image in which fixation failure is detected through the artificial neural network b to the artificial neural network c to derive arrangement information corrected to avoid the output cause type of the defect.

The artificial neural network c may include a clustering algorithm based on unsupervised learning. Unsupervised learning refers to an algorithm that learns while analyzing or clustering the data itself, rather than building learning data. The detection unit 170 may determine the defect cause type based on an unsupervised learning-based clustering algorithm. Specifically, the detection unit 170 may calculate the cause type of the defect by clustering the chip cutting image and the device cutting image associated with the detection of the fixing defect based on a clustering algorithm. Illustratively, a logistic regression algorithm, a random forest algorithm, a support vector machine (SVM) algorithm, a decision-making algorithm, and a clustering algorithm may be used as a clustering algorithm for unsupervised learning, but are not limited thereto.

According to an embodiment of the present application, the chip analyzer 111 may derive first placement information including area information and location information of chip attachment regions corresponding to each of a plurality of chips, based on drawing information.

For example, the chip analyzer 111 derives first placement information including area information and location information of a chip attaching region corresponding to each of a plurality of chips based on the obtained drawing information. information can be included.

According to an embodiment of the present application, the element analyzer 112 derives second arrangement information including area information, location information, and element color information of element coupling regions corresponding to each of a plurality of elements, based on drawing information. can do.

For example, the element analyzer 112 derives second arrangement information including area information, location information, and element color information of an element coupling region corresponding to each of a plurality of elements based on the obtained drawing information. Placement information may be included in the placement information.

According to an embodiment of the present application, the layer analysis unit 113 is based on the drawing information, n (n is a positive integer, n>1) layer layer shape information and n (n is a positive integer) corresponding to each of the plurality of layers An integer of n>1) Third arrangement information including layer order information may be derived.

For example, the layer analyzer 113 may provide n (n is a positive integer, n>1) layer type information and n (n is a positive integer, n corresponding to each of a plurality of layers) based on the obtained drawing information. >1) Derive third arrangement information including layer order information, wherein the third arrangement information may be included in the arrangement information.

According to one embodiment of the present application, the vision inspection unit 140 identifies one chip among a plurality of chips in the image, and based on the first arrangement information derived for the chip attachment region corresponding to the corresponding chip, Adherence strength and surface contamination can be judged.

The vision inspection unit 140 identifies any one chip among a plurality of chips included in the target PCB in the image of the manufactured target PCB, and displays a first arrangement derived for a chip attachment area corresponding to the identified one of the corresponding chips. Based on the information, it is possible to determine the adhesion strength and surface contamination of the corresponding chip.

Exemplarily, the vision inspection unit 140 may include reference information (for example, correct position information of a reference point such as a center or a corner) of a chip location of a corresponding chip attaching area included in the first placement information and a chip identified in the image. The degree of contamination of the surface of the chip can be determined by determining the adhesion strength of the chip based on the deviation of the actual information about the position and determining the presence or absence of foreign substances in the area of the corresponding chip.

When a chip or device defect is detected by the vision inspection unit 140, the corresponding target PCB is preset as an area that is distinguished from an area (defective product loading area) in which a multilayer printed circuit board (target PCB) with no defects is loaded. It may be transferred to a defective product loading unit (not shown). As another example, the image of the target PCB in which the defect is detected by the vision inspection unit 140 and the analysis result of the image are transmitted to a user terminal (not shown) possessed by a manager or operator of the processing line 10. can

In the analysis result of the image transmitted to the user terminal (not shown), information on the area where the defect is detected (in other words, the predetermined chip attachment area, element coupling area, etc. where the defect is identified) is displayed compared to the rest of the area. It may be highlighted to be distinguished by .

The apparatus 100 may perform fluorescence analysis on the manufactured target PCB based on drawing information.

Meanwhile, in the following, an embodiment of generating adjustment information associated with control of a solder printer (not shown) and a coater (not shown) included in the processing line 10 in consideration of the shape analysis result of the target PCB based on the drawing information. to explain about it.

The solder processing control unit (not shown) included in the device 100 generates mask adjustment information for a solder printer that applies solder cream on a target PCB based on the identified chip attachment area and element coupling area placement information. can In addition, the coating processing control unit (not shown) included in the apparatus 100 generates spray adjustment information for a coater spraying a waterproofing material on a target PCB based on the identified chip attachment area and element coupling area arrangement information. can do.

As such, the device 100 disclosed herein is used for vision inspection through analysis of the shape of the target PCB to be manufactured through the processing line 10, as well as various chips, elements, etc. provided on the target PCB. Placement information, which is information on the spatial pattern occupied in can be adjusted to

4 is a conceptual diagram for explaining an embodiment in which a spray pattern of a waterproof material is changed according to spray control information.

Referring to FIG. 4 , the coating module 410 provided in the coating machine according to an embodiment of the present application includes a first discharge portion 410a including a plurality of first holes 411a and a first discharge portion 410a. It may be provided in a double structure including a second discharge part 410b disposed on the lower side and including a plurality of second holes 411b.

In this regard, the first discharge part 410a and the second discharge part 410b are applied to the outer surface of the target PCB through the coating module 410 according to the degree of overlap between the first hole 411a and the second hole 411b. It may be provided so that the area of the hole through which the waterproof coating material sprayed onto is discharged can be adjusted.

For example, in (a) of FIG. 4 , the relative positions of the first discharge part 410a and the second discharge part 410b are adjusted so that the first hole 411a and the second hole 411b overlap to the maximum. The state in which the total hole area through which the coating material is sprayed is relatively increased, and FIG. It may indicate a state in which the total hole area through which the coating material is discharged is relatively reduced by adjusting the relative positions of the first discharge portion 410a and the second discharge portion 410b to decrease compared to .

In this regard, the present apparatus 100 adjusts the relative positions of the first discharge part 410a and the second discharge part 410b based on the layout information of the target PCB derived by the shape analysis unit 110, thereby plural By varying the hole overlapping area of the holes 411a and 411b, the discharge pressure or spray area of the coating material may be increased or decreased for each part.

According to an embodiment of the present application, if the adhesion strength of the chip determined by the vision inspection unit 140 is less than or equal to a predetermined strength or the degree of contamination of the surface is greater than or equal to a predetermined level, the shape analysis unit 110 determines the adhesion strength of the chip to a predetermined level. Chip correction placement information may be derived by modifying the first placement information so that the intensity exceeds the set level and the surface contamination is less than the set level.

If the attachment strength of the chip determined by the vision inspection unit 140 based on the image of the target PCB and the derived first placement information is less than or equal to a predetermined strength or the surface contamination is greater than or equal to a predetermined level, the shape analyzer 110 Corrected chip placement information may be derived by correcting the first arrangement information so that the adhesion strength of the corresponding chip exceeds a predetermined level and the surface contamination level is less than a predetermined level.

According to an embodiment of the present application, the manufacturing unit 120 may manufacture a chip-modified multi-layer PCB (MLB) based on the chip-modified placement information.

The manufacturing unit 120 may control the processing line 10 to manufacture a chip-modified multi-layer PCB based on the chip-modified disposition information derived by the shape analysis unit 110 .

According to an embodiment of the present application, the vision inspection unit 140 identifies any one element among a plurality of elements in the image, and determines the location of the corresponding element based on the second arrangement information derived for the element coupling region corresponding to the corresponding element. Insertion defects associated with misinsertion or reverse insertion can be determined.

The vision inspection unit 140 identifies any one of a plurality of elements included in the target PCB in the image of the manufactured target PCB, and the second arrangement derived for the element coupling region corresponding to the identified one of the corresponding elements. Based on the information, insertion coupling associated with erroneous insertion or reverse insertion of the corresponding element may be determined.

According to an embodiment of the present application, if there is an insertion defect determined by the vision inspection unit 140, the shape analysis unit 110 corrects the second arrangement information to avoid the insertion defect and derives the first element corrected arrangement information. can do.

If there is an insertion defect of the element determined by the vision inspection unit 140 based on the image of the target PCB and the derived second arrangement information, the shape analysis unit 110 performs a second arrangement so that the insertion defect of the corresponding element does not occur. Corrected arrangement information for the first element may be derived by correcting a corresponding portion of information that is incorrectly inserted or reversely inserted.

According to an embodiment of the present application, the manufacturing unit 120 may manufacture a first element modified multi-layer PCB (MLB) based on the first element modified arrangement information.

The manufacturing unit 120 may control the processing line 10 to manufacture a first element modified multilayer PCB based on the first element modified arrangement information derived by the shape analysis unit 110 .

According to an embodiment of the present application, the device analyzer 112 may derive reference color information of a merge inspection region including at least two or more device coupling regions.

The device analyzer 112 may derive reference color information of a merge inspection area including at least two or more device coupling areas among a plurality of devices identified by the vision inspection unit 140 in the image of the target PCB.

The merge inspection area may include a chip attachment area, a device coupling area, and at least two or more device coupling areas. The merge inspection area may be derived by dividing one target PCB into a plurality of areas.

In this regard, various elements such as connectors and capacitors inserted into the target PCB are usually arranged in colors that are distinguished from each other according to the element type. Device color information of the device coupling area may be derived so that a criterion for determining whether a correct device is properly inserted in the device coupling area that varies depending on the type can be variably set in response to a design change of the target PCB.

Recently, a large number of chips and devices have been mounted on printed circuit boards, and when a large number of devices are inserted into a target PCB, and individual vision inspections are performed on each device bonding area, the amount of time required to determine insertion defects of devices Time and computational resources may be excessive.

In consideration of this, the present apparatus 100 partitions a merge inspection area that encompasses at least two or more element coupling areas, and sets reference color information representing the set merge inspection area (for example, a portion (pixel) constituting the merge inspection area). The average value of the color values of , etc.) is derived, and as a primary vision test performed by the vision inspection unit 140, the color of the merge inspection area is recognized as a whole, and the color of the identified merge inspection area is the previously derived reference color. It is possible to quickly determine whether an insertion defect of each element has occurred within a corresponding merge inspection area by determining whether or not it is within a set color range in consideration of the information.

The photographing device may include a camera module that is disposed above the vision inspection jig in the processing line 10 and captures an image of a target PCB inserted (entered) to the lower side.

According to one embodiment of the present application, if the actual color information of the part corresponding to the merge inspection area in the image is out of a preset color range based on the reference color information, the vision inspection unit 140 determines that an insertion defect has occurred, The shape analyzer 110 may derive second element corrected arrangement information by modifying the second arrangement information so that the actual color information is within a preset color range based on the reference color information.

The criterion derived by the device analyzer 112 for actual color information of a portion corresponding to a merge inspection area including at least two or more device coupling areas among a plurality of devices identified by the vision inspection unit 140 in the image of the target PCB. If the color information is out of the preset color range, the vision inspection unit 140 determines that an insertion defect has occurred, and the shape analysis unit 110 determines the actual color information based on the determination result of the vision inspection unit 140. The second element corrected arrangement information may be derived by modifying the second arrangement information such that a is within a preset color range relative to the reference color information.

According to an embodiment of the present application, the manufacturing unit 120 may manufacture a second element modified multi-layer PCB (MLB) based on the second element modified arrangement information.

The manufacturing unit 120 may control the processing line 10 to manufacture a second element modified multilayer PCB based on the second element modified arrangement information derived by the shape analysis unit 110 .

According to an embodiment of the present application, the vision inspection unit 140 determines the type of the insertion defect and the type of the insertion defect based on the second arrangement information of each of the at least two or more element coupling regions included in the merge inspection region in which the insertion defect is detected. can be specified.

The vision inspection unit 140 may specify a device having an insertion defect and an insertion defect type of the corresponding device based on the second arrangement information of each of the at least two device coupling regions included in the merge inspection area in which the insertion defect is detected.

According to an embodiment of the present application, the shape analysis unit 110 may derive arrangement information such that a specific insertion defect occurs and a type of insertion defect does not occur.

The shape analyzer 110 may correct and derive the arrangement information so that the insertion defect type specified by the vision inspection unit 140 does not occur.

According to an embodiment of the present application, the vision inspection unit 140 identifies any one layer among a plurality of layers in the image, and based on the third arrangement information derived for the layer arrangement area corresponding to the corresponding layer, shape accuracy can be judged.

The vision inspection unit 140 identifies any one layer among a plurality of layers included in the target PCB in the image of the manufactured target PCB, and uses the layer analysis unit 113 for a layer arrangement area corresponding to the identified layer. Shape accuracy of the corresponding layer may be determined based on the derived third arrangement information.

According to an embodiment of the present application, if the shape accuracy of the layer determined by the vision inspection unit 140 is less than a predetermined level, the shape analysis unit 110 may perform third arrangement information such that the shape accuracy of the layer is equal to or greater than a predetermined level. It is possible to derive layer modification arrangement information by modifying .

If the shape accuracy of the layer determined by the vision inspection unit 140 is less than the predetermined degree, the shape analysis unit 110 corrects the third arrangement information so that the shape accuracy of the corresponding layer is equal to or greater than the predetermined level, and thus corrects the layer arrangement information. can be derived.

According to an embodiment of the present application, the manufacturing unit 120 may manufacture a layer-corrected multi-layer PCB (MLB) based on the layer-corrected arrangement information.

The manufacturing unit 120 may control the processing line 10 to manufacture a layer-corrected multilayer PCB based on the layer-corrected arrangement information derived by the shape analysis unit 110 .

Hereinafter, based on the details described above, the operation flow of the present application will be briefly reviewed.

5 is an operation flow chart for an intelligent multi-layer PCB manufacturing method according to an embodiment of the present application.

Referring to FIG. 5 as an example, the method for manufacturing an intelligent multi-layer PCB may include steps S11 to S16.

In step S11, the shape analysis unit 110 obtains drawing information including shape information of the target PCB, and derives arrangement information for a plurality of chips, a plurality of elements, and a plurality of layers based on the obtained drawing information. can

Next, in step S12, the manufacturing unit 120 may manufacture a multi-layer PCB (MLB) based on the derived placement information.

Next, in step S13 , the image acquiring unit 130 may acquire an image of a target PCB on which a plurality of chips, a plurality of devices, and a plurality of layers are disposed.

Next, in step S14 , the vision inspection unit 140 may detect defects related to the attachment of each of a plurality of chips, the insertion of each of a plurality of devices, and the arrangement of each of a plurality of layers, based on the arrangement information and the image.

Next, in step S15, when the vision inspection unit 140 detects a defect, the shape analyzer 110 may correct the placement information to derive first corrected placement information to prevent the defect.

If the vision inspection unit 140 does not detect a defect, it may end with step S14 as the last step.

Next, in step S16 , the manufacturing unit 120 may manufacture a first modified multi-layer PCB (MLB) based on the first modified arrangement information.

The intelligent multi-layer PCB manufacturing method shown in FIG. 5 can be performed by the intelligent multi-layer PCB manufacturing system 1 described above. Therefore, even if omitted below, the description of the intelligent multi-layer PCB manufacturing system 1 can be equally applied to the description of the intelligent multi-layer PCB manufacturing method.

In the foregoing description, steps S610 to S650 may be further divided into additional steps or combined into fewer steps, depending on an embodiment of the present invention. Also, some steps may be omitted if necessary, and the order of steps may be changed.

An intelligent multilayer PCB manufacturing method according to an embodiment of the present application may be implemented in the form of program commands that can be executed through various computer means and recorded on a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. Program instructions recorded on the medium may be those specially designed and configured for the present invention or those known and usable to those skilled in computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic media such as floptical disks. - includes hardware devices specially configured to store and execute program instructions, such as magneto-optical media, and ROM, RAM, flash memory, and the like. Examples of program instructions include high-level language codes that can be executed by a computer using an interpreter, as well as machine language codes such as those produced by a compiler. The hardware devices described above may be configured to act as one or more software modules to perform the operations of the present invention, and vice versa.

In addition, the above-described intelligent multi-layer PCB manufacturing method may be implemented in the form of a computer program or application stored in a recording medium and executed by a computer.

The above description of the present application is for illustrative purposes, and those skilled in the art will understand that it can be easily modified into other specific forms without changing the technical spirit or essential features of the present application. Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting. For example, each component described as a single type may be implemented in a distributed manner, and similarly, components described as distributed may be implemented in a combined form.

The scope of the present application is indicated by the following claims rather than the detailed description above, and all changes or modifications derived from the meaning and scope of the claims and equivalent concepts thereof should be construed as being included in the scope of the present application.

1: Intelligent multi-layer PCB manufacturing system
10: multi-layer PCB processing line
20: Network
100: intelligent multi-layer PCB manufacturing device
110: shape analysis unit
111: chip analysis unit 112: device analysis unit 113: layer analysis unit
120: manufacturing unit 130: image acquisition unit
140: vision inspection unit 150: cutting image collection unit
160: fixed image collection unit 170: detection unit

Claims (15)

In an intelligent multi-layer PCB (MLB) manufacturing system,
a shape analyzer that obtains drawing information including shape information of a target PCB and derives arrangement information for a plurality of chips, a plurality of elements, and a plurality of layers based on the drawing information;
a manufacturing unit that manufactures the multi-layer PCB (MLB) based on the arrangement information;
an image acquiring unit acquiring an image of the target PCB on which the plurality of chips, the plurality of elements, and the plurality of layers are disposed; and
A vision inspection unit detecting a defect associated with the attachment of each of the plurality of chips, the insertion of each of the plurality of elements, and the arrangement of each of the plurality of layers based on the arrangement information and the image;
Including,
When the vision inspection unit detects the defect, the shape analysis unit corrects the layout information to derive first corrected layout information to prevent the defect, and the manufacturing unit first corrects the multi-layer structure based on the first corrected layout information. To manufacture PCB (Multi-Layer PCB, MLB),
Intelligent multi-layer PCB manufacturing system. According to claim 1,
The intelligent multilayer PCB manufacturing system,
a cutting image collection unit that collects chip cutting images of a cutting machine that cuts a bundle of chips in which the plurality of chips are connected into individual chips having a certain width and a certain length;
a fixing image collection unit that collects chip fixing images of a press machine that fixes the plurality of chips to a target PCB board through a press fit process; and
Further comprising a detection unit for detecting defects in the target PCB board and the chip fixing through the chip cutting image and the chip fixing image,
When the detection unit detects defects in the board for the target PCB and the fixing of the chip, the shape analysis unit corrects the placement information to derive second corrected placement information to prevent defects in the board for the target PCB and the fixing of the chip, , wherein the manufacturing unit manufactures a second modified multi-layer PCB (MLB) based on the second modified layout information,
Intelligent multi-layer PCB manufacturing system. According to claim 2,
The cut image collection unit,
Further collecting element cutting images of a cutting machine for cutting the element bundle to which the plurality of elements are connected into each element having a certain width and a certain length,
The fixation image collection unit,
Through the press fit process, an image of the device fixing of the press machine for fixing the plurality of devices to the target PCB board is further collected,
The detecting unit,
Further detecting defects in the target PCB board and the device fixing through the device cutting image and the device fixing image, and when detecting defects in the target PCB board and the device fixing, the shape analysis unit for the target PCB In order to prevent a defect in fixing the board and the device, the layout information is corrected to derive third corrected layout information, and the manufacturing unit produces a third corrected multi-layer PCB (MLB) based on the third corrected layout information. to manufacture,
Intelligent multi-layer PCB manufacturing system. According to claim 3,
The detecting unit,
With the chip cutting image, the chip fixing image, the device cutting image, and the device fixing image as inputs, a defect detection result of the target PCB board and the chip fixing and a defect detection of the target PCB board and the device fixing Based on the artificial neural network built through learning that outputs the result, if a defect in fixing the board for the target PCB and the chip or a defect in the board for the target PCB and the fixing of the element is detected, the shape analysis unit for the target PCB In order to prevent a defect in fixing the board and the chip or a defect in the fixing of the target PCB board and the device, the arrangement information is corrected to derive fourth corrected placement information, and the manufacturing unit produces a first correction based on the fourth corrected placement information. To manufacture a 4-modified multi-layer PCB (Multi-Layer PCB, MLB),
Intelligent multi-layer PCB manufacturing system. According to claim 4,
The output is
Based on the chip fixing image and the device fixing image under the assumption that the cutting of the chip bundle and the device bundle by the cutter is normal, a detection result of a chip fixing defect and a detection result of an element coupling defect are included.
Intelligent multi-layer PCB manufacturing system. According to claim 4,
The detecting unit,
The chip fixation defect and the device fixation defect are detected based on an artificial neural network built through learning that takes the chip fixation image and the device fixation image as inputs and outputs a detection result of a chip fixation defect and a result of the device fixation defect. If detected, the shape analysis unit derives fifth corrected placement information by modifying the placement information to prevent a defect in fixing the board for the target PCB and the chip or a defect in fixing the board for the target PCB and the device, and Part is to manufacture a fifth correction multi-layer PCB (MLB) based on the fifth correction placement information,
Intelligent multi-layer PCB manufacturing system. According to claim 6,
The detecting unit,
Determining the type of defect cause through an artificial neural network that takes the chip cutting image and device cutting image associated with the fixing defect detection as input,
The shape analysis unit derives the arrangement information by avoiding the defect cause type,
Intelligent multi-layer PCB manufacturing system. According to claim 1,
The shape analysis unit,
a chip analysis unit deriving first placement information including area information and location information of the chip attachment region corresponding to each of the plurality of chips, based on the drawing information;
a device analyzer for deriving second arrangement information including area information, location information, and device color information of the device coupling region corresponding to each of the plurality of devices, based on the drawing information; and
Based on the drawing information, n (n is a positive integer, n>1) layer layer shape information and n (n is a positive integer, n>1) layer order information corresponding to each of the plurality of layers are included. A layer analysis unit for deriving third arrangement information to
Which includes,
Intelligent multi-layer PCB manufacturing system. According to claim 8,
The vision inspection unit,
Identifying any one chip among the plurality of chips in the image, and determining adhesion strength and surface contamination of the corresponding chip based on the first arrangement information derived for the chip attachment region corresponding to the corresponding chip;
When the adhesion strength of the chip is less than or equal to a predetermined level or the degree of contamination of the surface is greater than or equal to a predetermined level, the shape analysis unit determines that the adhesion strength of the chip exceeds a predetermined level and the degree of contamination of the surface is less than a predetermined level. Deriving chip correction placement information by modifying placement information;
The manufacturing unit manufactures a chip-modified multi-layer PCB (MLB) based on the chip-modified placement information,
Intelligent multi-layer PCB manufacturing system. According to claim 8,
The vision inspection unit,
Any one element among the plurality of elements is identified in the image, and an insertion defect associated with erroneous insertion or reverse insertion of the corresponding element based on the second placement information derived for the element coupling region corresponding to the corresponding element. judge,
If the insertion defect exists, the shape analysis unit corrects the second arrangement information to derive first element corrected arrangement information so as to avoid the insertion defect;
The manufacturing unit manufactures a first element modified multi-layer PCB (MLB) based on the first element modified arrangement information,
Intelligent multi-layer PCB manufacturing system. According to claim 10,
The element analysis unit,
Derive reference color information of a merge inspection region including at least two or more element coupling regions;
If the actual color information of the part corresponding to the merge inspection area in the image is out of a preset color range based on the reference color information, the vision inspection unit determines that the insertion defect has occurred, and the shape analysis unit determines that the actual color information has occurred. The second element correction arrangement information is derived by modifying the second arrangement information so that the color information is within a preset color range based on the reference color information, and the manufacturing unit determines the second element arrangement information based on the second element modified arrangement information. To manufacture a modified multi-layer PCB (Multi-Layer PCB, MLB),
Intelligent multi-layer PCB manufacturing system. According to claim 11,
The vision inspection unit,
Specifying the device where the insertion defect occurs and the type of the insertion defect based on the second arrangement information of each of the at least two element coupling regions included in the merge inspection area in which the insertion defect is detected;
Wherein the shape analysis unit derives the arrangement information so that the specified device having the insertion defect and the type of the insertion defect do not occur;
Intelligent multi-layer PCB manufacturing system. According to claim 8,
The vision inspection unit,
Identifying any one of the plurality of layers in the image, and determining shape accuracy of the corresponding layer based on the third placement information derived for the layer placement area corresponding to the corresponding layer,
If the shape accuracy of the layer is less than a predetermined degree, the shape analysis unit derives layer correction arrangement information by modifying the third arrangement information so that the shape accuracy of the layer is equal to or greater than a predetermined level,
Wherein the manufacturing unit manufactures a layer-modified multi-layer PCB (MLB) based on the layer-modified arrangement information,
Intelligent multi-layer PCB manufacturing system. In the method of manufacturing an intelligent multi-layer PCB (Multi-Layer PCB, MLB),
obtaining, by a shape analysis unit, drawing information including shape information of a target PCB, and deriving arrangement information for a plurality of chips, a plurality of elements, and a plurality of layers based on the drawing information;
manufacturing the multi-layer PCB (Multi-Layer PCB, MLB) based on the arrangement information by a manufacturing unit;
Acquiring an image of the target PCB on which the plurality of chips, the plurality of devices, and the plurality of layers are disposed by an image acquisition unit;
detecting, by a vision inspector, a defect associated with the attachment of each of the plurality of chips, the insertion of each of the plurality of elements, and the arrangement of each of the plurality of layers, based on the arrangement information and the image;
deriving first corrected placement information by modifying the placement information so that the shape analyzer prevents the defect when the vision inspection unit detects the defect; and
manufacturing a first modified multi-layer PCB (MLB) based on the first modified layout information by the manufacturing unit;
including,
Intelligent multi-layer PCB manufacturing system. A computer-readable recording medium on which a program for executing the method of claim 14 is recorded on a computer.

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